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Date: Wed, 18 Dec 2024 14:33:40 +0100 Message-Id: <20241218133340.51003-1-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Raj Vishwanathan4 The riscv MIPS P8700 uses a different opcode for PAUSE. It is a =E2=80=98hint=E2=80=99 encoding of the SLLI instruction, with rd=3D= 0, rs1=3D0 and imm=3D5. It will behave as a NOP instruction if no additional behavior beyond that of SLLI is implemented. Signed-off-by: Raj Vishwanathan4 Signed-off-by: Aleksandar Rikalo --- arch/riscv/Kconfig | 12 ++++++++++++ arch/riscv/include/asm/insn-def.h | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d4a7ca0388c0..07a77fa0a014 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -716,6 +716,18 @@ config RISCV_ISA_ZACAS =20 If you don't know what to do here, say Y. =20 +config RISCV_MIPS_P8700_PAUSE_OPCODE_FIX + bool "Fix the PAUSE Opcode for MIPS P8700" + default n + help + The RISCV MIPS P8700 uses a different opcode for PAUSE. + It is a 'hint' encoding of the SLLI instruction, + with rd=3D0, rs1=3D0 and imm=3D5. It will behave as a NOP + instruction if no additional behavior beyond that of + SLLI is implemented. + + If you are not using the P8700 processor, say n. + config TOOLCHAIN_HAS_ZBB bool default y diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h index 9a913010cdd9..793eedde3516 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -196,7 +196,12 @@ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(4)) =20 +#ifndef CONFIG_RISCV_MIPS_P8700_PAUSE_OPCODE_FIX #define RISCV_PAUSE ".4byte 0x100000f" +#else +#define RISCV_PAUSE ".4byte 0x00501013" +#endif + #define ZAWRS_WRS_NTO ".4byte 0x00d00073" #define ZAWRS_WRS_STO ".4byte 0x01d00073" =20 --=20 2.25.1