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Wed, 18 Dec 2024 11:54:04 +0100 (CET) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, macpaul.lin@mediatek.com Subject: [PATCH] arm64: dts: mediatek: mt8188: Add VDO0's DSC and MERGE block nodes Date: Wed, 18 Dec 2024 11:53:56 +0100 Message-ID: <20241218105356.39111-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.47.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for the DSC0 and MERGE0 blocks, located in VDOSYS0 and necessary to add support for Display Stream Compression with a display pipeline that looks like: [other components] -> DSC0 -> MERGE0 -> Display Interface Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 137bd39808ea..6ef385072c9f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,9 +26,11 @@ / { aliases { dp-intf0 =3D &dp_intf0; dp-intf1 =3D &dp_intf1; + dsc0 =3D &dsc0; ethdr0 =3D ðdr0; gce0 =3D &gce0; gce1 =3D &gce1; + merge0 =3D &merge0; merge1 =3D &merge1; merge2 =3D &merge2; merge3 =3D &merge3; @@ -2880,6 +2882,15 @@ disp_dsi0: dsi@1c008000 { status =3D "disabled"; }; =20 + dsc0: dsc@1c009000 { + compatible =3D "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; + reg =3D <0 0x1c009000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DSC_WRAP0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + disp_dsi1: dsi@1c012000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c012000 0 0x1000>; @@ -2895,6 +2906,17 @@ disp_dsi1: dsi@1c012000 { status =3D "disabled"; }; =20 + merge0: merge0@1c014000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c014000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + dp_intf0: dp-intf@1c015000 { compatible =3D "mediatek,mt8188-dp-intf"; reg =3D <0 0x1c015000 0 0x1000>; --=20 2.46.1