From nobody Thu Dec 18 20:23:59 2025 Received: from thales.epochal.quest (thales.epochal.quest [51.222.15.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CF2F1F63FC; Wed, 18 Dec 2024 13:10:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.222.15.28 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734527407; cv=none; b=fBVpCwVZIm9iN3RhmM9r927LY0Hw/4JW7ui/TtBA66lXM0iTwE50Q1iWZN9ba/Kr8o5KYjnCvCexJwBLsv3kvt5eNqAanPsqri9ObTv4y8ILWDo75Y86ycZ76FW116DoYxTOJbGks/yNif6tcdGmhkbfrr13oOW88V/lQbL4c14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734527407; c=relaxed/simple; bh=UtiFUB7JYOEIMLI78fhF4G8WqBGTAB6l9kQoj2W7g7Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AksKij50QtMay6CReIaGR0eBr6i2sqHOINUklFCt3teI4Teh5e3LDlJxbWuYJ8Kc4TlOh++E3awva2+3HYxj+Hrzg9++BhuRSRBODQ4BI0VUisUBuHDBtt9IxPCzux4/ggDsjA2yQG9I03Oo3eO+s5b69egpzxeUa7dYPHWUReQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest; spf=pass smtp.mailfrom=epochal.quest; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b=jXmM0P56; arc=none smtp.client-ip=51.222.15.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=epochal.quest Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b="jXmM0P56" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=epochal.quest; s=default; t=1734526898; bh=UtiFUB7JYOEIMLI78fhF4G8WqBGTAB6l9kQoj2W7g7Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jXmM0P56xEPCszSNWAG2srnBbfoN63A04qcy47Fnb+SYM/xM1N3rXfL8eSptj4Itz Ruff8oOAfZ/fiDHmUXwEwaydSR6HYm29SJe86oCxB/oumb10a/SB5anIhIMSGaVVOl NUodk1QWl26XZnlsdBjwQUhwEdbQ9cvTaHl2x3eypRcerwqKHb1PsHNdTbLMvu+ptP qhSAduiC7yhdc59AQsiSUM4Y6T7WcLEdzVbHRQ+7VopDqy48XCVuPQToowosTT1aV5 ttas0gRSzxcYAJ6FzsoqM7MRKWYyLMVzbhDMB/xtxMEHZKsekhK6Q6/pLz7MyM5VJE Tafulc5+iwhig== X-Virus-Scanned: by epochal.quest From: Cody Eksal Date: Wed, 18 Dec 2024 09:01:19 -0400 Subject: [PATCH v2 2/2] arm64: dts: allwinner: a100: Add syscon nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241218-a100-syscon-v2-2-dae60b9ce192@epochal.quest> References: <20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest> In-Reply-To: <20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Parthiban Nallathambi , Andre Przywara , Cody Eksal X-Mailer: b4 0.14.2 The Allwinner A100 has a system configuration block, denoted as SYS_CFG in the user manual's memory map. It is undocumented in the manual, but a glance at the vendor tree shows this block is similar to its predecessors in the A64 and H6. The A100 also has 3 SRAM blocks: A1, A2, and C. Add all of these to the SoC's device tree. Reviewed-by: Parthiban Nallathambi Signed-off-by: Cody Eksal --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 33 ++++++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index 29ac7716c7a5284ccf8af675db9c7d016785f0ff..a24adba201af29a3a117222c67d= a5d269629fa47 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -101,6 +101,39 @@ soc { #size-cells =3D <1>; ranges =3D <0 0 0 0x3fffffff>; =20 + syscon: syscon@3000000 { + compatible =3D "allwinner,sun50i-a100-system-control", + "allwinner,sun50i-a64-system-control"; + reg =3D <0x03000000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + sram_a1: sram@20000 { + compatible =3D "mmio-sram"; + reg =3D <0x00020000 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x00020000 0x4000>; + }; + + sram_c: sram@24000 { + compatible =3D "mmio-sram"; + reg =3D <0x024000 0x21000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x024000 0x21000>; + }; + + sram_a2: sram@100000 { + compatible =3D "mmio-sram"; + reg =3D <0x0100000 0x14000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0100000 0x14000>; + }; + }; + ccu: clock@3001000 { compatible =3D "allwinner,sun50i-a100-ccu"; reg =3D <0x03001000 0x1000>; --=20 2.47.1