From nobody Thu Dec 18 09:44:39 2025 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 883F41FBC8E for ; Tue, 17 Dec 2024 21:21:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734470481; cv=none; b=YSNQAOGc84vRNwaXMO2wzZtKQU51e7NcccR9xcLwN6pol059GnbfJKS8VzTfrXzZ4+RXMmtY7vd/nvofXsbGkbe2rVaJpSkcS19kU0hXPKJTp6F9BhNiqpmzs+f5vIKb+KnnBn/AnknLFhHVIMdrAR2xBKqFhd2ZqIP5vDMSo1w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734470481; c=relaxed/simple; bh=N3CkdBP4BxotD0IFFq7Qq57eqxjC/6uusjnRLSXGc0M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=enjME0UM4lzndnQdh4VtIzE58HTls3v+lCVljZtqOII1O3vgYmTCDL4C0KmItkHaX2Qb21NxTALNo69gs2oVvwvywR9HI/q4Ll4Z/nE1sQBG7mN9ueQ3+KedqZofxRjz1e9NaZ2yP5luD/5iKsjdvFuZ3PqeokFd8+/fsXrkOIQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=VUCz9OE/; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="VUCz9OE/" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1734470476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YE2j3A4NxVRVl2GQB2DLusxN7V/Z1D1qyrpkRyZqAjs=; b=VUCz9OE/AV2KcJ4J/cF5KXrOcr3hPjieyyL33kZUsPDz3yA0S+1ZyfYmkt57QMq55xiumt 2F+dSum7cm/lECcbmlUGO6V3W5MyrylY4OZ19GHhM8/0JzSCzI8rnwAvzElEsh7+UzTBfw U3AvPtw0WbCp9WJejotPzL1AE5lyWyc= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH 06/18] KVM: arm64: Always support SW_INCR PMU event Date: Tue, 17 Dec 2024 13:20:36 -0800 Message-Id: <20241217212048.3709204-7-oliver.upton@linux.dev> In-Reply-To: <20241217212048.3709204-1-oliver.upton@linux.dev> References: <20241217212048.3709204-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Support for SW_INCR is unconditional, as KVM traps accesses to PMSWINC_EL0 and emulates the intended event increment. While it is expected that ~all PMUv3 implementations already advertise this event, non-PMUv3 hardware may not. Signed-off-by: Oliver Upton --- arch/arm64/kvm/pmu-emul.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 809d65b912e8..7f20da32266e 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -875,6 +875,8 @@ static u64 compute_pmceid0(struct arm_pmu *pmu) { u64 val =3D __compute_pmceid(pmu, 0); =20 + /* always support SW_INCR */ + val |=3D BIT(ARMV8_PMUV3_PERFCTR_SW_INCR); /* always support CHAIN */ val |=3D BIT(ARMV8_PMUV3_PERFCTR_CHAIN); return val; --=20 2.39.5