From nobody Thu Dec 18 09:44:37 2025 Received: from out-189.mta1.migadu.com (out-189.mta1.migadu.com [95.215.58.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3831A1FA830 for ; Tue, 17 Dec 2024 21:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734470475; cv=none; b=oBgxpc0pEitOVVWjOs/Y9kgrH/ZTw14p//mQZ67rQVCHUwX3wDkYIZDHP+7Q2HTk86A5wzVuUkXjdg6EtmSCFpA7Exa3rcV6unK+8v3g/oei2kwieYlpD3iP6WUm9rOHCegfkc7BEqahsoHjyy2QMmv3FT+IgzzbO2GV8DFrVU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734470475; c=relaxed/simple; bh=y6VvnHBChQeregBjHDTodO70I2ZylfsaibStu/vkxSQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nL7LuapQXiFYgA4+DYCQtoHBUZSgUlI2VxI+EE4UYPwu3BBn5rQTZuOP0q8yd9xAgg2nBSUBhyMvtLSXM38SwTEaJdcKpSFoGUvgkbb5EZ8i5bHK1GyyMyKMMOlTNvdvvbNGD9gwv90qihqszJxRkACeldU6eUcIqu3qe1Zxcis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=r9cMm4Y4; arc=none smtp.client-ip=95.215.58.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="r9cMm4Y4" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1734470471; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yhHFWrYb/mOQoFZKkVBe+pJEJcbMtsTwCremyuNvSjM=; b=r9cMm4Y4Ct0ojc/NxmhLoRSqbAO4LKLAds+rsjtXuQlN7vdvX/FTcyP2XxGNL1X7DAYnJb ifoyeQkgGNb+Ym0MIQpXaeiOmo/NaUqolOXCkacWeaUesvRfbrAtBDI8R94JCQpJ4dU4P1 QienLMM+/5dvnTM1YvFhOMj174/5Xkw= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH 04/18] drivers/perf: apple_m1: Provide helper for mapping PMUv3 events Date: Tue, 17 Dec 2024 13:20:34 -0800 Message-Id: <20241217212048.3709204-5-oliver.upton@linux.dev> In-Reply-To: <20241217212048.3709204-1-oliver.upton@linux.dev> References: <20241217212048.3709204-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Apple M* parts carry some IMP DEF traps for guest accesses to PMUv3 registers, even though the underlying hardware doesn't implement PMUv3. This means it is possible to virtualize PMUv3 for KVM guests. Add a helper for mapping common PMUv3 event IDs onto hardware event IDs, keeping the implementation-specific crud in the PMU driver rather than KVM proper. Signed-off-by: Oliver Upton --- drivers/perf/apple_m1_cpu_pmu.c | 32 ++++++++++++++++++++++++++++++++ include/linux/perf/arm_pmu.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index d6d4ff6da862..b4fe247543a6 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include =20 #include @@ -174,6 +175,14 @@ static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MA= X] =3D { [PERF_COUNT_HW_BRANCH_MISSES] =3D M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, }; =20 +#define M1_PMUV3_EVENT_MAP(pmuv3_event, m1_event) \ + [ARMV8_PMUV3_PERFCTR_##pmuv3_event] =3D M1_PMU_PERFCTR_##m1_event + +static const unsigned int m1_pmu_pmceid_map[ARMV8_PMUV3_MAX_COMMON_EVENTS]= =3D { + [0 ... ARMV8_PMUV3_MAX_COMMON_EVENTS - 1] =3D HW_OP_UNSUPPORTED, + M1_PMUV3_EVENT_MAP(CPU_CYCLES, CORE_ACTIVE_CYCLE), +}; + /* sysfs definitions */ static ssize_t m1_pmu_events_sysfs_show(struct device *dev, struct device_attribute *attr, @@ -558,6 +567,26 @@ static int m2_pmu_map_event(struct perf_event *event) return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int m1_pmu_map_pmuv3_event(unsigned int eventsel) +{ + int m1_event =3D HW_OP_UNSUPPORTED; + + if (eventsel < ARMV8_PMUV3_MAX_COMMON_EVENTS) + m1_event =3D m1_pmu_pmceid_map[eventsel]; + + return m1_event =3D=3D HW_OP_UNSUPPORTED ? -EOPNOTSUPP : m1_event; +} + +static void m1_pmu_init_pmceid(struct arm_pmu *pmu) +{ + unsigned int event; + + for (event =3D 0; event < ARMV8_PMUV3_MAX_COMMON_EVENTS; event++) { + if (m1_pmu_map_pmuv3_event(event) >=3D 0) + set_bit(event, pmu->pmceid_bitmap); + } +} + static void m1_pmu_reset(void *info) { int i; @@ -618,6 +647,9 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 fla= gs) cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 + cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; + m1_pmu_init_pmceid(cpu_pmu); + bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 4b5b83677e3f..35f3778ae20e 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -100,6 +100,7 @@ struct arm_pmu { void (*stop)(struct arm_pmu *); void (*reset)(void *); int (*map_event)(struct perf_event *event); + int (*map_pmuv3_event)(unsigned int eventsel); DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS); bool secure_access; /* 32-bit ARM only */ #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 --=20 2.39.5