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([145.224.66.247]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436360159aasm114935825e9.6.2024.12.17.03.56.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:56:24 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: James Clark , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH 1/5] perf: arm_spe: Add format option for discard mode Date: Tue, 17 Dec 2024 11:56:04 +0000 Message-Id: <20241217115610.371755-2-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217115610.371755-1-james.clark@linaro.org> References: <20241217115610.371755-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FEAT_SPEv1p2 (optional from Armv8.6) adds a discard mode that allows all SPE data to be discarded rather than written to memory. Add a format bit for this mode. If the mode isn't supported, the format bit isn't published and attempts to use it will result in -EOPNOTSUPP. Allocating an aux buffer is still allowed even though it won't be written to so that old tools continue to work, but updated tools can choose to skip this step. Signed-off-by: James Clark --- drivers/perf/arm_spe_pmu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index fd5b78732603..9aaf3f98e6f5 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -193,6 +193,9 @@ static const struct attribute_group arm_spe_pmu_cap_gro= up =3D { #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */ #define ATTR_CFG_FLD_store_filter_LO 34 #define ATTR_CFG_FLD_store_filter_HI 34 +#define ATTR_CFG_FLD_discard_CFG config /* PMBLIMITR_EL1.FM =3D DISCARD */ +#define ATTR_CFG_FLD_discard_LO 35 +#define ATTR_CFG_FLD_discard_HI 35 =20 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */ #define ATTR_CFG_FLD_event_filter_LO 0 @@ -216,6 +219,7 @@ GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); +GEN_PMU_FORMAT_ATTR(discard); =20 static struct attribute *arm_spe_pmu_formats_attr[] =3D { &format_attr_ts_enable.attr, @@ -228,9 +232,15 @@ static struct attribute *arm_spe_pmu_formats_attr[] = =3D { &format_attr_event_filter.attr, &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, + &format_attr_discard.attr, NULL, }; =20 +static bool discard_unsupported(struct arm_spe_pmu *spe_pmu) +{ + return spe_pmu->pmsver < ID_AA64DFR0_EL1_PMSVer_V1P2; +} + static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, struct attribute *attr, int unused) @@ -238,6 +248,9 @@ static umode_t arm_spe_pmu_format_attr_is_visible(struc= t kobject *kobj, struct device *dev =3D kobj_to_dev(kobj); struct arm_spe_pmu *spe_pmu =3D dev_get_drvdata(dev); =20 + if (attr =3D=3D &format_attr_discard.attr && discard_unsupported(spe_pmu)) + return 0; + if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) return 0; =20 @@ -502,6 +515,12 @@ static void arm_spe_perf_aux_output_begin(struct perf_= output_handle *handle, u64 base, limit; struct arm_spe_pmu_buf *buf; =20 + if (ATTR_CFG_GET_FLD(&event->attr, discard)) { + limit =3D FIELD_PREP(PMBLIMITR_EL1_FM, PMBLIMITR_EL1_FM_DISCARD); + limit |=3D PMBLIMITR_EL1_E; + goto out_write_limit; + } + /* Start a new aux session */ buf =3D perf_aux_output_begin(handle, event); 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([145.224.66.247]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436360159aasm114935825e9.6.2024.12.17.03.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:56:28 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: James Clark , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH 2/5] perf tool: arm-spe: Pull out functions for aux buffer and tracking setup Date: Tue, 17 Dec 2024 11:56:05 +0000 Message-Id: <20241217115610.371755-3-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217115610.371755-1-james.clark@linaro.org> References: <20241217115610.371755-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These won't be used in the next commit in discard mode, so put them in their own functions. No functional changes intended. Signed-off-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 83 +++++++++++++++++----------- 1 file changed, 51 insertions(+), 32 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/u= til/arm-spe.c index 22b19dcc6beb..1b543855f206 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -274,33 +274,9 @@ static void arm_spe_setup_evsel(struct evsel *evsel, s= truct perf_cpu_map *cpus) evsel__set_sample_bit(evsel, PHYS_ADDR); } =20 -static int arm_spe_recording_options(struct auxtrace_record *itr, - struct evlist *evlist, - struct record_opts *opts) +static int arm_spe_setup_aux_buffer(struct record_opts *opts) { - struct arm_spe_recording *sper =3D - container_of(itr, struct arm_spe_recording, itr); - struct evsel *evsel, *tmp; - struct perf_cpu_map *cpus =3D evlist->core.user_requested_cpus; bool privileged =3D perf_event_paranoid_check(-1); - struct evsel *tracking_evsel; - int err; - - sper->evlist =3D evlist; - - evlist__for_each_entry(evlist, evsel) { - if (evsel__is_aux_event(evsel)) { - if (!strstarts(evsel->pmu->name, ARM_SPE_PMU_NAME)) { - pr_err("Found unexpected auxtrace event: %s\n", - evsel->pmu->name); - return -EINVAL; - } - opts->full_auxtrace =3D true; - } - } - - if (!opts->full_auxtrace) - return 0; =20 /* * we are in snapshot mode. @@ -330,6 +306,9 @@ static int arm_spe_recording_options(struct auxtrace_re= cord *itr, pr_err("Failed to calculate default snapshot size and/or AUX area traci= ng mmap pages\n"); return -EINVAL; } + + pr_debug2("%sx snapshot size: %zu\n", ARM_SPE_PMU_NAME, + opts->auxtrace_snapshot_size); } =20 /* We are in full trace mode but '-m,xyz' wasn't specified */ @@ -355,14 +334,15 @@ static int arm_spe_recording_options(struct auxtrace_= record *itr, } } =20 - if (opts->auxtrace_snapshot_mode) - pr_debug2("%sx snapshot size: %zu\n", ARM_SPE_PMU_NAME, - opts->auxtrace_snapshot_size); + return 0; +} =20 - evlist__for_each_entry_safe(evlist, tmp, evsel) { - if (evsel__is_aux_event(evsel)) - arm_spe_setup_evsel(evsel, cpus); - } +static int arm_spe_setup_tracking_event(struct evlist *evlist, + struct record_opts *opts) +{ + int err; + struct evsel *tracking_evsel; + struct perf_cpu_map *cpus =3D evlist->core.user_requested_cpus; =20 /* Add dummy event to keep tracking */ err =3D parse_event(evlist, "dummy:u"); @@ -388,6 +368,45 @@ static int arm_spe_recording_options(struct auxtrace_r= ecord *itr, return 0; } =20 +static int arm_spe_recording_options(struct auxtrace_record *itr, + struct evlist *evlist, + struct record_opts *opts) +{ + struct arm_spe_recording *sper =3D + container_of(itr, struct arm_spe_recording, itr); + struct evsel *evsel, *tmp; + struct perf_cpu_map *cpus =3D evlist->core.user_requested_cpus; + + int err; + + sper->evlist =3D evlist; + + evlist__for_each_entry(evlist, evsel) { + if (evsel__is_aux_event(evsel)) { + if (!strstarts(evsel->pmu->name, ARM_SPE_PMU_NAME)) { + pr_err("Found unexpected auxtrace event: %s\n", + evsel->pmu->name); + return -EINVAL; + } + opts->full_auxtrace =3D true; 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([145.224.66.247]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436360159aasm114935825e9.6.2024.12.17.03.56.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:56:32 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: James Clark , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH 3/5] perf tool: arm-spe: Don't allocate buffer or tracking event in discard mode Date: Tue, 17 Dec 2024 11:56:06 +0000 Message-Id: <20241217115610.371755-4-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217115610.371755-1-james.clark@linaro.org> References: <20241217115610.371755-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The buffer will never be written to so don't bother allocating it. The tracking event is also not required. Signed-off-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/u= til/arm-spe.c index 1b543855f206..4301181b8e45 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -376,7 +376,7 @@ static int arm_spe_recording_options(struct auxtrace_re= cord *itr, container_of(itr, struct arm_spe_recording, itr); struct evsel *evsel, *tmp; struct perf_cpu_map *cpus =3D evlist->core.user_requested_cpus; - + bool discard =3D false; int err; =20 sper->evlist =3D evlist; @@ -396,10 +396,17 @@ static int arm_spe_recording_options(struct auxtrace_= record *itr, return 0; =20 evlist__for_each_entry_safe(evlist, tmp, evsel) { - if (evsel__is_aux_event(evsel)) + if (evsel__is_aux_event(evsel)) { arm_spe_setup_evsel(evsel, cpus); + if (evsel->core.attr.config & + perf_pmu__format_bits(evsel->pmu, "discard")) + discard =3D true; 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([145.224.66.247]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436360159aasm114935825e9.6.2024.12.17.03.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:56:36 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: James Clark , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH 4/5] perf test: arm_spe: Add test for discard mode Date: Tue, 17 Dec 2024 11:56:07 +0000 Message-Id: <20241217115610.371755-5-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217115610.371755-1-james.clark@linaro.org> References: <20241217115610.371755-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test that checks that there were no AUX or AUXTRACE events recorded when discard mode is used. Signed-off-by: James Clark --- tools/perf/tests/shell/test_arm_spe.sh | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/tests/shell/test_arm_spe.sh b/tools/perf/tests/shel= l/test_arm_spe.sh index 3258368634f7..a69aab70dd8a 100755 --- a/tools/perf/tests/shell/test_arm_spe.sh +++ b/tools/perf/tests/shell/test_arm_spe.sh @@ -107,7 +107,37 @@ arm_spe_system_wide_test() { arm_spe_report "SPE system-wide testing" $err } =20 +arm_spe_discard_test() { + echo "SPE discard mode" + + for f in /sys/bus/event_source/devices/arm_spe_*; do + if [ -e "$f/format/discard" ]; then + cpu=3D$(cut -c -1 "$f/cpumask") + break + fi + done + + if [ -z $cpu ]; then + arm_spe_report "SPE discard mode not present" 2 + return + fi + + # Test can use wildcard SPE instance and Perf will only open the event + # on instances that have that format flag. But make sure the target + # runs on an instance with discard mode otherwise we're not testing + # anything. + perf record -o ${perfdata} -e arm_spe/discard/ -N -B --no-bpf-event \ + -- taskset --cpu-list $cpu true + + if perf report -i ${perfdata} --stats | grep 'AUX events\|AUXTRACE events= '; then + arm_spe_report "SPE discard mode found unexpected data" 1 + else + arm_spe_report "SPE discard mode" 0 + fi +} + arm_spe_snapshot_test arm_spe_system_wide_test +arm_spe_discard_test =20 exit $glb_err --=20 2.34.1 From nobody Thu Dec 18 00:09:15 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 911311F426B for ; Tue, 17 Dec 2024 11:56:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734436605; cv=none; b=uT3C6yYEO9UOFuXxq+HySHaW4thatAYEgxB9rSA2NPEVhK8iL06iOKgc8OEJPbUtycg40lZgzEr1j3J1scUgvppZ5PvrUpXI4j68asEFkz0OZyNHpkrWhghrof5DgxRAkgEhSb5bz9SvShu1x0Dtq5OLmXM1SNRevq5/JrsXngQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734436605; c=relaxed/simple; bh=fyI0/dhbkFxqKd8iWh2Jzy9mpwkSrgNFZ+i9alPd06w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=frMiR+vOgpnpLxR2XHv7tAVbwoC7AN9uCva7ZISBDJ0La0GbauAWMfHUdRJQtjshVcH6XvER7nXK7JFK9SRPTgylhC048lSdHKMx7nNRXNzVE9i6eYBELGCAQtmdf/j7h6RX0PoHZ15mBCtMn6gsD2rXY64showWYoynEIX/Ops= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WmrD2b/b; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WmrD2b/b" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-43635796b48so20317625e9.0 for ; Tue, 17 Dec 2024 03:56:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734436601; x=1735041401; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bFM1q7jsB7Su3lAVmgr0rlaLhCHhfoFOEst7jXnFLG4=; b=WmrD2b/ble34C9MwCDKzGxVg0vFLBUyrDuJVfLLw1rqm1qyUXqWiR4eOZbNAk1BNVb w4Jfgt14YAEDSRgePSBFuicKaAgUGvmJ9KwAjmlzoZcAyaMCeTIcWsakq8DZKghJYTTH RdTK+wh+fy0FLBLE1CNgxbjk/MuMoXFuOBFn+mGQMYKWiW1kkYesLDjNUohiIRRv42L3 tEBnBEcZhdBHqtYPB2CqdsAuXKhNiySB36/XPUBHQ89xX+TnS84awpFdq5CEcJlr6M+X jGSfOJdqpWl7+gNYy60d/+FvDsWF+ezjMtjKNRe8YzoCgnw5JWBID5d1O+20jG16Uw+B YZQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734436601; x=1735041401; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bFM1q7jsB7Su3lAVmgr0rlaLhCHhfoFOEst7jXnFLG4=; b=ofzQInw1PzhM/Df+NJLFb/hxeaE83VtfR0g4w8wLXx2u5CjZfXtkYjNkae5IKL+QUs 6sR/peh8Xsrot+bYpYv2BjKy8A/Gb3aJQj5YmFrMYnHePe5QCXhNA2cc42UW0uzaejbH lEcISrurBt+pdPltNblOuO8XXBrCreD6OmYn0V8gS9iMdimOyoV4jaQ8Bb20sflgt6CO 7qx2bVbiZE8oY5+coSqr1g18V2ZCoJWXs7TVrAD4GOxfqDKcgxbnU33ld+/o7DOz7WQS G9hv2QZRVuJma6A7/U6KmPM5v6GVNCSrvrfXAyZIBj9FCAFCNYPp8VBkDmPPgumdM4fv Arlg== X-Forwarded-Encrypted: i=1; AJvYcCVSDNtn+du9B7krGbhWhRE1+Vo6XQQ3k636hyCw5oI0iwIg7JsfyNiJIOWe2/+sF4h8ogejnfco9uOq5ps=@vger.kernel.org X-Gm-Message-State: AOJu0YxnE2/xcAIoot1qG76Z58kJNz26qEoFQlkR9EQ23QxoWXa6Di3a CwSXamjulNd0JLe7Ob4qAWNIxKIX02kz+Y0zrhBID3ydckqrBr/q1nbOujWkztU= X-Gm-Gg: ASbGncu8crfrZAhhlFAkRum0xeX/DducBm3faF8xwr3rVNC+wg09GA9ucy/8mvObEUu oHEiKVEaxV3/8L0+T66qTu7s6dgWKvN5hd7KhVcZHpGpYIt2ctLzznXRKzaCytiwOKRTsVSOOtN oFpiv1bOL22acbC786OrO1i/AkKGqOvbhHEP83nfNV2rOUpL0mZUSqlX0l2jlm4vHWQtKGW9iLy FYpQW4ktfXy08CizukvBP8DCqTjoZ5uxve48LcaFuw3U98tFGj9V1in X-Google-Smtp-Source: AGHT+IGHK04q5y+mpaaNrdicK1T9ozCfgAnXqS1cmz3u3H1E5qAKa1r9yR6aB/fLQM8NPU3JxtkxJw== X-Received: by 2002:a05:600c:3516:b0:436:1b77:b5aa with SMTP id 5b1f17b1804b1-4364815c7d6mr27745645e9.8.1734436601097; Tue, 17 Dec 2024 03:56:41 -0800 (PST) Received: from pop-os.. ([145.224.66.247]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436360159aasm114935825e9.6.2024.12.17.03.56.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:56:40 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: James Clark , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH 5/5] perf docs: arm_spe: Document new discard mode Date: Tue, 17 Dec 2024 11:56:08 +0000 Message-Id: <20241217115610.371755-6-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217115610.371755-1-james.clark@linaro.org> References: <20241217115610.371755-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the flag, hint what it's used for and give an example with other useful options to get minimal output. Signed-off-by: James Clark --- tools/perf/Documentation/perf-arm-spe.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documen= tation/perf-arm-spe.txt index de2b0b479249..588eead438bc 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -150,6 +150,7 @@ arm_spe/load_filter=3D1,min_latency=3D10/' pct_enable=3D1 - collect physical timestamp instead of virtual ti= mestamp (PMSCR.PCT) - requires privilege store_filter=3D1 - collect stores only (PMSFCR.ST) ts_enable=3D1 - enable timestamping with value of generic timer = (PMSCR.TS) + discard=3D1 - enable SPE PMU events but don't collect sample d= ata - see 'Discard mode' (PMBLIMITR.FM =3D DISCARD) =20 +++*+++ Latency is the total latency from the point at which sampling star= ted on that instruction, rather than only the execution latency. @@ -220,6 +221,16 @@ Common errors =20 Increase sampling interval (see above) =20 +Discard mode +~~~~~~~~~~~~ + +SPE PMU events can be used without the overhead of collecting sample data = if +discard mode is supported (optional from Armv8.6). First run a system wide= SPE +session (or on the core of interest) using options to minimize output. The= n run +perf stat: + + perf record -e arm_spe/discard/ -a -N -B --no-bpf-event -o - > /dev/null= & + perf stat -e SAMPLE_FEED_LD =20 SEE ALSO -------- --=20 2.34.1