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(fttx-pool-217.61.150.187.bambit.de [217.61.150.187]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 94C6D10030F; Tue, 17 Dec 2024 09:12:55 +0000 (UTC) From: Frank Wunderlich To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 07/22] arm64: dts: mediatek: mt7988: Add CPU OPP table for clock scaling Date: Tue, 17 Dec 2024 10:12:21 +0100 Message-ID: <20241217091238.16032-8-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241217091238.16032-1-linux@fw-web.de> References: <20241217091238.16032-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: 8150ac17-4322-4ebd-9700-bca82c1fff16 Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add operating points defining frequency/voltages of cpu cores. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- changes: v3: - change commit-title v2: - drop cpu-labels for now --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index 5e53ea47f159..a7954bf5c81e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -21,6 +21,10 @@ cpu@0 { reg =3D <0x0>; device_type =3D "cpu"; enable-method =3D "psci"; + clocks =3D <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu@1 { @@ -28,6 +32,10 @@ cpu@1 { reg =3D <0x1>; device_type =3D "cpu"; enable-method =3D "psci"; + clocks =3D <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu@2 { @@ -35,6 +43,10 @@ cpu@2 { reg =3D <0x2>; device_type =3D "cpu"; enable-method =3D "psci"; + clocks =3D <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu@3 { @@ -42,6 +54,32 @@ cpu@3 { reg =3D <0x3>; device_type =3D "cpu"; enable-method =3D "psci"; + clocks =3D <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + }; + + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <850000>; + }; + opp-1100000000 { + opp-hz =3D /bits/ 64 <1100000000>; + opp-microvolt =3D <850000>; + }; + opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <850000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <900000>; + }; }; }; =20 --=20 2.43.0