From nobody Thu Dec 18 08:11:48 2025 Received: from mxout2.routing.net (mxout2.routing.net [134.0.28.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709FF1DF72D; Tue, 17 Dec 2024 09:18:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734427124; cv=none; b=HLxTm5B2lQwt2wnWhkbg/JseKl2zb1GYJCyZOnncNUEpt6SQhLHNYrRhZIqYvXIAk+ynU4Ffk4AQ2EoyFJrj8j6/tADll17pcIuUQGFPIn9WXMTYhQgn4s3GmqeHHHyol/MQj4MlnQ8pPJhhVizg57+3b2KEg+k3R2yQvG5nW+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734427124; c=relaxed/simple; bh=s/eZo2vqWyErOHJg2Ie7u57IctCoPEgORTcS4Ox4wpI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OvONTeYlKGmsMkCpl2BWDVlZI1J7AB1jQhTn6VLLRE9jPJiyu+r7YfCz/zJ5KyPJ7AR5UCe1e5zl7M4ek4wz8Q8yzG+9ZXTrFkJFwQZl6r0wTXElSeapCjYUVgqtNib1lktjff5iU/t1sj1TRrqIBTTUf+wtYru91Af3d0vtTeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=dOA1B2xf; arc=none smtp.client-ip=134.0.28.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="dOA1B2xf" Received: from mxbox2.masterlogin.de (unknown [192.168.10.89]) by mxout2.routing.net (Postfix) with ESMTP id 9B25F60270; Tue, 17 Dec 2024 09:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1734426775; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bGMVUzg70D55505GQQEnbxpAmhShtyOEYa1yvSmDy/Q=; b=dOA1B2xfYIs3BkwOtNnQy5fyL/WBpd8Cv8Pn6QcVogbAdSW4OsVJJ/Z1yWl3/AZi0uzovi HtOkK3NLJoZ3aHHlT7oXPwFbDGRID/SpOXxbXEX8Leh3JmTz9uEHz9ycAW5VHYQgjvhaA0 qDlmwfjMl3ud6Fm/l8+msDqAYEq0EO8= Received: from frank-u24.. (fttx-pool-217.61.150.187.bambit.de [217.61.150.187]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id E6B56100549; Tue, 17 Dec 2024 09:12:54 +0000 (UTC) From: Frank Wunderlich To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 06/22] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu Date: Tue, 17 Dec 2024 10:12:20 +0100 Message-ID: <20241217091238.16032-7-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241217091238.16032-1-linux@fw-web.de> References: <20241217091238.16032-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: f53882ff-a533-4d87-84ee-c8b7a0182036 Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich In preparation for adding support for CPU DVFS and clock tables for it, add the MCUSYS clock controller node. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index 16b28fcf1e3c..5e53ea47f159 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -192,6 +192,12 @@ pwm@10048000 { status =3D "disabled"; }; =20 + mcusys: mcusys@100e0000 { + compatible =3D "mediatek,mt7988-mcusys", "syscon"; + reg =3D <0 0x100e0000 0 0x1000>; + #clock-cells =3D <1>; + }; + serial@11000000 { compatible =3D "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg =3D <0 0x11000000 0 0x100>; --=20 2.43.0