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(fttx-pool-217.61.150.187.bambit.de [217.61.150.187]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id D539F1004DD; Tue, 17 Dec 2024 09:12:51 +0000 (UTC) From: Frank Wunderlich To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 02/22] arm64: dts: mediatek: mt7988: Add mmc support Date: Tue, 17 Dec 2024 10:12:16 +0100 Message-ID: <20241217091238.16032-3-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241217091238.16032-1-linux@fw-web.de> References: <20241217091238.16032-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: c1cff4fa-b88e-4d2f-9890-b549ef8f6afe Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add devicetree node for MMC controller. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- changes: v3: move clocks in one line v2: squash "add missing label for apmixedsys" --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index d205717ac78b..2e224d0d0168 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -112,7 +112,7 @@ watchdog: watchdog@1001c000 { #reset-cells =3D <1>; }; =20 - clock-controller@1001e000 { + apmixedsys: clock-controller@1001e000 { compatible =3D "mediatek,mt7988-apmixedsys"; reg =3D <0 0x1001e000 0 0x1000>; #clock-cells =3D <1>; @@ -290,6 +290,25 @@ usb@11200000 { clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; }; =20 + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt7988-mmc"; + reg =3D <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks =3D <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names =3D "source", "hclk", "axi_cg", "ahb_cg"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + clock-controller@11f40000 { compatible =3D "mediatek,mt7988-xfi-pll"; reg =3D <0 0x11f40000 0 0x1000>; --=20 2.43.0