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(fttx-pool-217.61.150.187.bambit.de [217.61.150.187]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 9C94A1004DD; Tue, 17 Dec 2024 08:54:48 +0000 (UTC) From: Frank Wunderlich To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: Frank Wunderlich , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v7 5/5] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl subnodes for bpi-r4 Date: Tue, 17 Dec 2024 09:54:30 +0100 Message-ID: <20241217085435.9586-6-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241217085435.9586-1-linux@fw-web.de> References: <20241217085435.9586-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: b0c0f04f-b1bf-42f1-a862-87cedae600e7 Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add board specific pinctrl configurations on Bananapi R4. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- changes in v6: - fix typo - start title uppercase - use bpi-r4 prefix --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arc= h/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index efc4ad0b08b8..aa2dabc041fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -9,3 +9,192 @@ / { model =3D "Banana Pi BPI-R4"; chassis-type =3D "embedded"; }; + +&pio { + mdio0_pins: mdio0-pins { + mux { + function =3D "eth"; + groups =3D "mdc_mdio0"; + }; + + conf { + pins =3D "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength =3D <8>; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function =3D "i2c"; + groups =3D "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-g0-pins { + mux { + function =3D "i2c"; + groups =3D "i2c1_0"; + }; + }; + + i2c1_sfp_pins: i2c1-sfp-g0-pins { + mux { + function =3D "i2c"; + groups =3D "i2c1_sfp"; + }; + }; + + i2c2_0_pins: i2c2-g0-pins { + mux { + function =3D "i2c"; + groups =3D "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-g1-pins { + mux { + function =3D "i2c"; + groups =3D "i2c2_1"; + }; + }; + + gbe0_led0_pins: gbe0-led0-pins { + mux { + function =3D "led"; + groups =3D "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-led0-pins { + mux { + function =3D "led"; + groups =3D "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-led0-pins { + mux { + function =3D "led"; + groups =3D "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-led0-pins { + mux { + function =3D "led"; + groups =3D "gbe3_led0"; + }; + }; + + gbe0_led1_pins: gbe0-led1-pins { + mux { + function =3D "led"; + groups =3D "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function =3D "led"; + groups =3D "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function =3D "led"; + groups =3D "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function =3D "led"; + groups =3D "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function =3D "led"; + groups =3D "2p5gbe_led0"; + }; + }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function =3D "led"; + groups =3D "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-emmc-45-pins { + mux { + function =3D "flash"; + groups =3D "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function =3D "flash"; + groups =3D "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function =3D "flash"; + groups =3D "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function =3D "uart"; + groups =3D "uart0"; + }; + }; + + snfi_pins: snfi-pins { + mux { + function =3D "flash"; + groups =3D "snfi"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function =3D "spi"; + groups =3D "spi0"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; + + spi1_pins: spi1-pins { + mux { + function =3D "spi"; + groups =3D "spi1"; + }; + }; + + spi2_pins: spi2-pins { + mux { + function =3D "spi"; + groups =3D "spi2"; + }; + }; + + spi2_flash_pins: spi2-flash-pins { + mux { + function =3D "spi"; + groups =3D "spi2", "spi2_wp_hold"; + }; + }; +}; --=20 2.43.0