From nobody Wed Dec 17 06:04:06 2025 Received: from mxout3.routing.net (mxout3.routing.net [134.0.28.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E45BB148314; Tue, 17 Dec 2024 08:54:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734425697; cv=none; b=qbKcJHGfJKiNiVeLCRMIYqcVJmCIKVcwQNMQdN5UG3U7DZtyztbziruKPf0fQ85HJbILRPQqkDK+bQ7slSJ3EG+O9HUkg88wRacnDHVW316BBjVj8tnQBuxsnHL2TgTnQK8Jal8w0oxf26NdrinjMf+ALah1XPyQS9syrvH01HI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734425697; c=relaxed/simple; bh=DaHPd6SOKd8MfSu9ZfFUvr3WN62/OMs14KDuAXEquQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B/K00yC+TC8qNP8/Ic+twEvXXOy7Zk2hgFW1cWCMEz0p/wocUuCYGy5nvxcgSL7OrpaPldiNwsWyPaoVl2ncpnWjnkz2bpTgOpbjXdSZZ8iwJcjC6fEh9kbbs9BpKMQRI25+YUNFXIqWZil3H0EHVrI0keIF43JrtRszt6dpXN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=vbPRtcIY; arc=none smtp.client-ip=134.0.28.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="vbPRtcIY" Received: from mxbox2.masterlogin.de (unknown [192.168.10.89]) by mxout3.routing.net (Postfix) with ESMTP id ADD92605EB; Tue, 17 Dec 2024 08:54:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1734425688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VIpsPcGOjRyl5qUhr+7znCLWNsK6P7pZhuPfToLGzCI=; b=vbPRtcIYqD4k7oB3KEslabxqTMsXK+a+Djrmbi2ddcU+4fYhLDm8HoNqg3NLnhzspGYBzy AW7EupL6+TVDmOzfLWXmcpDGZnygfLTlAOVVjmIeUMTCOHMEYS/IZVvuht4O5+KGq39ZjD ZsncLCp/xNL1FxMQwo0Dy3ahSbATAEc= Received: from frank-u24.. (fttx-pool-217.61.150.187.bambit.de [217.61.150.187]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id D6EF51003B7; Tue, 17 Dec 2024 08:54:47 +0000 (UTC) From: Frank Wunderlich To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: Frank Wunderlich , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v7 4/5] arm64: dts: mediatek: mt7988: Add pinctrl support Date: Tue, 17 Dec 2024 09:54:29 +0100 Message-ID: <20241217085435.9586-5-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241217085435.9586-1-linux@fw-web.de> References: <20241217085435.9586-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: d42e49fa-ec72-4dc0-acd8-326356904806 Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add mt7988a pinctrl node. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- v5: - drop pins with second function v2: - fix wrong alignment of reg values --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index c9649b815276..46969577c87a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt7988a"; @@ -105,6 +106,59 @@ clock-controller@1001e000 { #clock-cells =3D <1>; }; =20 + pio: pinctrl@1001f000 { + compatible =3D "mediatek,mt7988-pinctrl"; + reg =3D <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names =3D "gpio", "iocfg_tr", + "iocfg_br", "iocfg_rb", + "iocfg_lb", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 84>; + interrupt-controller; + interrupts =3D ; + interrupt-parent =3D <&gic>; + #interrupt-cells =3D <2>; + + pcie0_pins: pcie0-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; + }; + pwm@10048000 { compatible =3D "mediatek,mt7988-pwm"; reg =3D <0 0x10048000 0 0x1000>; --=20 2.43.0