From nobody Wed Dec 17 19:43:38 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 609061448E4; Mon, 16 Dec 2024 15:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734363659; cv=none; b=N7yN1E/8DolHuGGePCIr2eRgvX0/TWC6V38KW5tOVStUwAgtcNqvyTWFza6QpEJDhPn4N4ov2bJ/KlKBkb5xyrxJC7qYMDrnlN0KsFrsExc3cDT0ehw/2Gf27yQxU7iVdOGy6bQnW8jI3jXdnlsoV6UfRqy7CuQB4YOvI2nIvXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734363659; c=relaxed/simple; bh=9DNIauzaXg1hkOQtTX2G0/c6dVnryyX0aB3vRrCI1ZE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HAsWtzj9NhMyibDnu9N6b88k8ZrCcK6QSJwgj/BPwnfISWW5yYsKVP/Lk/v6cB8y84+uT+7/G8WXR4l8DvPS3bmHcSNaKrKkwSoJ0NJYTHFHw1o1n9/NEZNmP3uuQP3+W0o/I706yW0bZWyUInUFfRyTIwTzw9hRiop9YNvaGLE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=dMH7Iju0; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="dMH7Iju0" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BGEYKiY029957; Mon, 16 Dec 2024 16:40:43 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= s/v1YHGVNRYUeWMmDsWob1hB9FIOwu/mNjAMSlsgc94=; b=dMH7Iju0Z0vXJZaP l27EatwrpqbCT/aUc7furYe28ESR/Tg4UqG8mEhdw1u3wycqD1DMV3W1fszv5zWe Cnw6x18h0w4SFjJ9zYukBkPiLg3QU0N7W1BeVO1xKjaytOAvhFf20RhT8CswiG3+ FoggqotezUZ/nDWkUtPgy5lZDUUDGhPVAJSKq1ZN9UGiNSxK3G+TuGSyEmfucFXO loIpoi07CmnNvUd5po/OVyOgCXBKcS8OnuPUzlJCckCt9ULzK1JHoYGjd72X/Ock mXx8zr2QloSOYZBKcaHbfeldc8VcEfApOqabgrewncHMWVBBhDZXf+mngC0MhOVq U6UdzA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 43jp3987bx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Dec 2024 16:40:42 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8115140046; Mon, 16 Dec 2024 16:39:47 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node4.st.com [10.75.129.133]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4A880277E0C; Mon, 16 Dec 2024 16:39:20 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 16 Dec 2024 16:39:20 +0100 Received: from localhost (10.252.30.129) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 16 Dec 2024 16:39:19 +0100 From: Fabrice Gasnier To: CC: , , , , , , , , Subject: [PATCH 1/5] ARM: dts: stm32: populate all timer counter nodes on stm32mp13 Date: Mon, 16 Dec 2024 16:39:04 +0100 Message-ID: <20241216153908.3069548-2-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216153908.3069548-1-fabrice.gasnier@foss.st.com> References: <20241216153908.3069548-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Counter driver originally had support limited to quadrature interface and simple counter. It has been improved[1], so add the remaining stm32 timer counter nodes. [1] https://lore.kernel.org/linux-arm-kernel/20240307133306.383045-1-fabric= e.gasnier@foss.st.com/ Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/st/stm32mp131.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index e1a764d269d2..0019d12c3d3d 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -261,6 +261,11 @@ timers6: timer@40004000 { dma-names =3D "up"; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + timer@5 { compatible =3D "st,stm32h7-timer-trigger"; reg =3D <5>; @@ -281,6 +286,11 @@ timers7: timer@40005000 { dma-names =3D "up"; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + timer@6 { compatible =3D "st,stm32h7-timer-trigger"; reg =3D <6>; @@ -1196,6 +1206,11 @@ timers12: timer@4c007000 { access-controllers =3D <&etzpc 23>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1221,6 +1236,11 @@ timers13: timer@4c008000 { access-controllers =3D <&etzpc 24>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1246,6 +1266,11 @@ timers14: timer@4c009000 { access-controllers =3D <&etzpc 25>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1276,6 +1301,11 @@ timers15: timer@4c00a000 { access-controllers =3D <&etzpc 26>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1304,6 +1334,11 @@ timers16: timer@4c00b000 { access-controllers =3D <&etzpc 27>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1332,6 +1367,11 @@ timers17: timer@4c00c000 { access-controllers =3D <&etzpc 28>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; --=20 2.25.1 From nobody Wed Dec 17 19:43:38 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6088C139CEF; Mon, 16 Dec 2024 15:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734363658; cv=none; b=NSUbkNMXicfPO0hMMqqWBWrJswd3/EUhnti1asoA2z7gnXgn7F31P4QTP1uRPl5uF7cqQlCV7iyaIZq2YZDiZzeQ2CSvyQA2+PGx6i62MOc0RcYOr3uy44n+UsY4G8SirbdhyCZUkIuzocWbpz/xWhefjPrJMq7FXLUsNKE3Eeo= ARC-Message-Signature: i=1; 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Mon, 16 Dec 2024 16:39:50 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1C49C2843BA; Mon, 16 Dec 2024 16:39:21 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 16 Dec 2024 16:39:20 +0100 Received: from localhost (10.252.30.129) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 16 Dec 2024 16:39:20 +0100 From: Fabrice Gasnier To: CC: , , , , , , , , Subject: [PATCH 2/5] ARM: dts: stm32: populate all timer counter nodes on stm32mp15 Date: Mon, 16 Dec 2024 16:39:05 +0100 Message-ID: <20241216153908.3069548-3-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216153908.3069548-1-fabrice.gasnier@foss.st.com> References: <20241216153908.3069548-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Counter driver originally had support limited to quadrature interface and simple counter. It has been improved[1], so add the remaining stm32 timer counter nodes. [1] https://lore.kernel.org/linux-arm-kernel/20240307133306.383045-1-fabric= e.gasnier@foss.st.com/ Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/st/stm32mp151.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index 4f878ec102c1..13e172371eac 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -576,6 +576,11 @@ timers6: timer@40004000 { access-controllers =3D <&etzpc 20>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + timer@5 { compatible =3D "st,stm32h7-timer-trigger"; reg =3D <5>; @@ -597,6 +602,11 @@ timers7: timer@40005000 { access-controllers =3D <&etzpc 21>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + timer@6 { compatible =3D "st,stm32h7-timer-trigger"; reg =3D <6>; @@ -616,6 +626,11 @@ timers12: timer@40006000 { access-controllers =3D <&etzpc 22>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -641,6 +656,11 @@ timers13: timer@40007000 { access-controllers =3D <&etzpc 23>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -666,6 +686,11 @@ timers14: timer@40008000 { access-controllers =3D <&etzpc 24>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1114,6 +1139,11 @@ timers15: timer@44006000 { access-controllers =3D <&etzpc 54>; status =3D "disabled"; =20 + counter { + compatible =3D "st,stm32-timer-counter"; + status =3D "disabled"; + }; + pwm { compatible =3D "st,stm32-pwm"; #pwm-cells =3D <3>; @@ -1142,11 +1172,17 @@ timers16: timer@44007000 { access-controllers =3D <&etzpc 55>; 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charset="utf-8" Enable the counter nodes without dedicated pins. With such configuration, the counter interface can be used on internal clock to generate events. Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st= /stm32mp135f-dk.dts index 1af335a39993..c6a5bfe89a38 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -396,6 +396,9 @@ &timers3 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4= func */ pinctrl-0 =3D <&pwm3_pins_a>; @@ -412,6 +415,9 @@ &timers4 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_C= H2 func */ pinctrl-0 =3D <&pwm4_pins_a>; @@ -428,6 +434,9 @@ &timers8 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_C= H3 func */ pinctrl-0 =3D <&pwm8_pins_a>; @@ -442,6 +451,9 @@ timer@7 { =20 &timers14 { status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_= CH1 func */ pinctrl-0 =3D <&pwm14_pins_a>; --=20 2.25.1 From nobody Wed Dec 17 19:43:38 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60953148FF0; Mon, 16 Dec 2024 15:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734363657; cv=none; b=bD0aro3ZHsOzkg82p37jkfh1wzfEARpvpxhMF6E0E2oQ1LiUAad5BZEL6tnYMS9229fn2EZIZnpkiGtnzEv+cQk29aVKsItQlU340kmxqRHTMH3gYBs+s0C2shGUAb64OuGKe+T7mRB4Wssf4xRvnJgc3wbpADWPaOtHUHbh50k= ARC-Message-Signature: i=1; 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charset="utf-8" Enable the counter nodes without dedicated pins. With such configuration, the counter interface can be used on internal clock to generate events. Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ev1.dts index 9eb9a1bf4f2c..8f99c30f1af1 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -306,6 +306,9 @@ &timers2 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm2_pins_a>; pinctrl-1 =3D <&pwm2_sleep_pins_a>; @@ -321,6 +324,9 @@ &timers8 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm8_pins_a>; pinctrl-1 =3D <&pwm8_sleep_pins_a>; @@ -336,6 +342,9 @@ &timers12 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm12_pins_a>; pinctrl-1 =3D <&pwm12_sleep_pins_a>; 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charset="utf-8" Enable the counter nodes without dedicated pins. With such configuration, the counter interface can be used on internal clock to generate events. Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/= st/stm32mp15xx-dkx.dtsi index f7634c51efb2..a5511b1f0ce3 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -570,6 +570,9 @@ &timers1 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm1_pins_a>; pinctrl-1 =3D <&pwm1_sleep_pins_a>; @@ -585,6 +588,9 @@ &timers3 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm3_pins_a>; pinctrl-1 =3D <&pwm3_sleep_pins_a>; @@ -600,6 +606,9 @@ &timers4 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm4_pins_a &pwm4_pins_b>; pinctrl-1 =3D <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; @@ -615,6 +624,9 @@ &timers5 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm5_pins_a>; pinctrl-1 =3D <&pwm5_sleep_pins_a>; @@ -630,6 +642,9 @@ &timers6 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; timer@5 { status =3D "okay"; }; @@ -639,6 +654,9 @@ &timers12 { /delete-property/dmas; /delete-property/dma-names; status =3D "disabled"; + counter { + status =3D "okay"; + }; pwm { pinctrl-0 =3D <&pwm12_pins_a>; pinctrl-1 =3D <&pwm12_sleep_pins_a>; --=20 2.25.1