From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6290F1BD9CD for ; Mon, 16 Dec 2024 04:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322129; cv=none; b=ToOVbogMrlakrtikowyzWEpPAFXos/NIKyG0mQGn9OuOElxeVt5gPUZspolSPWaKbKYiQ8kggtRa9nG72Zz2WufdfgVyDxQwoPAhw8Yo2k9UfYPt6dy6QtchOFhJVdGbf38Eew76kjtniaTMyc0uzxHaGkXjTenTNxRJrvqByEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322129; c=relaxed/simple; bh=PalgsxfP3ZDRiS+0o+J+LTsic4o/XxB0AEksOrPdf4U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hUdJG/uaccF7JN4ICanDFE9RJdn3sCvFngMN2DcNL6Z05dT32nHESLFKtXT7vP7HGfYwToAND0SzQfq4IFKsIjzKE3xRPsnGNQfG5sZDAHlQwPR383ZBY+93OtTngXM+XYN2fScmtJikwzXSgCi/GUo4HLxe4B5jF8gOXlBm6ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA8071424; Sun, 15 Dec 2024 20:09:13 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C7FE03F58B; Sun, 15 Dec 2024 20:08:41 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev Subject: [PATCH V3 1/7] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 Date: Mon, 16 Dec 2024 09:38:25 +0530 Message-Id: <20241216040831.2448257-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR0_EL1 register fields as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b081b54d6d22..a6cbe0dcd63b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1591,6 +1591,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1652,6 +1653,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg =20 --=20 2.25.1 From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AE2AB1C3F0E for ; Mon, 16 Dec 2024 04:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322132; cv=none; b=JuO3Z0fyL7Xq8X85K1zNDAiixid6Spoyu4JjHQcdeZahts4D3VbDSID4dC+V2slbf7np973BInuQPCeL7UV+ouwb3Vmte+Kpz1fgBtWip5ajRO12vA95KkMirCD5bNz3wJOa64LEnSop4VeFeNN8+aRFkOo4TX1y6n/bfD+5DJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322132; c=relaxed/simple; bh=IUJZIYdttaUlv6hbhzryrA4QhshdOKnDcCZXtcCN+J8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PshwB9DB4iJbLm2/Jsw8rJqGV1mXvO4ibtREPGWwFiRsTT+898qGQyEfmCEiYyVtliftDTP1HJb1sR++pR8WJDOFu2L9aZstOi7fntQxJDKrJ2LEGFEJDrtUDQqJc05bkFo7c90wuanAWBp4c0N3mdq9yIkLqPS3g6U88Vmv4Wg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E5741AC1; Sun, 15 Dec 2024 20:09:18 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4D71E3F58B; Sun, 15 Dec 2024 20:08:46 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev Subject: [PATCH V3 2/7] arm64/sysreg: Add register fields for MDSELR_EL1 Date: Mon, 16 Dec 2024 09:38:26 +0530 Message-Id: <20241216040831.2448257-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSELR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a6cbe0dcd63b..fe878eb194a0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -93,6 +93,17 @@ Res0 63:32 Field 31:0 DTRTX EndSysreg =20 +Sysreg MDSELR_EL1 2 0 0 4 2 +Res0 63:6 +Enum 5:4 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +Res0 3:0 +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 06BB91C54B6 for ; Mon, 16 Dec 2024 04:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322136; cv=none; b=qLlXjxgCy7r+ArKZuRD2QvGj8dHSfgQCSyhZYVH7WeL64I22UKxzSLiGIyEn6Lg73TtSRxUbxnpd3cVga2Y/Zr079B8eMOV8cCwlwVf5HEtr7A5zo6Ne/Femm8pA8vj4pajJGj5fkWW5GcfkKiSt/vVbnkJV6ntYn0f/9IoZchA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322136; c=relaxed/simple; bh=A4SjgjMpKlFAhfY1vhzbQhRrcBbBYAAsd+vvtK6hDGI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EqLcXMBpa8ZBDKEiThStRgNVRUZSeTSyT4hedYxbnEK/65ig+Dwo4ES+ocPNgmk7oI2Ny3tWr4xu/qGL6/wZLNXpWY43xR7Td7Co16i9fjEQgcqAq1gAuibIl4GND6XXt/PG/fjlBG7QGSlJhNL/3Dbstjy6EwzKI8pkOKH/XGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB1AB1AED; Sun, 15 Dec 2024 20:09:22 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C0D4D3F58B; Sun, 15 Dec 2024 20:08:50 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev Subject: [PATCH V3 3/7] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Date: Mon, 16 Dec 2024 09:38:27 +0530 Message-Id: <20241216040831.2448257-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index fe878eb194a0..a9dc5e4f9d97 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2557,6 +2557,35 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A280C185B62 for ; Mon, 16 Dec 2024 04:08:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322141; cv=none; b=CloOZj3tRCa71AAO6OxAhNbdueXof5OPyeKmru6YBI2HwysaLvv6RH0r/NEcESKkWuOzqnKD53GAKbwNMCdw27mTbqoPlHRjg8tuSaWhO6DDC/oL+pEdReKrVyN3ZoHuUGlNAZ0JoBrPWwnklCIOoiUdZYrmkkHhMg5gvmlivjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322141; c=relaxed/simple; bh=sm1+8wKPa8Px/JwDiO3hfRddBEYurSFy1/JjUHjmVlE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=D00ebptwDmw5Eais52D26VjlMQdN4SVEktMdWVNTqgQ3IACEOY8+RijPeVJVEE6QhImF/Vd8W2pbMSPni96dw0XzTRuDN7t8HJoe8AnrSjur8BdX5OYRJve1N27/kWilc9wqzQJgXoNl04GlkZuN0g5cA9URIotWf1rY4pPTGVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 303CE1BA8; Sun, 15 Dec 2024 20:09:27 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 37E3C3F58B; Sun, 15 Dec 2024 20:08:54 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev Subject: [PATCH V3 4/7] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Date: Mon, 16 Dec 2024 09:38:28 +0530 Message-Id: <20241216040831.2448257-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a9dc5e4f9d97..8bf22f3904bd 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2586,6 +2586,34 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1E65E1CBEAA for ; Mon, 16 Dec 2024 04:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322145; cv=none; b=nr6jGaEVVgC0Hc9mg3S7zNslNc4qYiTQ3ZM9/E6FrxhAgTkjFizpOsTzA3D0N0fA6ZGLwJtOL9gcTm32in5291tHj/lN5Gpd3wN+JfhBWd5FYnOmHoVN0rbF0CvtLK6MZK/2a3FCl92mxA4fwMrVU0kK/OtHeI0g36Eu5bi0N1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734322145; c=relaxed/simple; bh=IeUs7k0HB31r6gPF9UlyWyc85kOFsHKd/2r0oJxY2LI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q6AjyLbAKwR80tsh2aNn48uFo02Nd/cYjQd6ike992nVYPt0oOa1LyAXrSoXcKvIKlw9JZTxgRNXMsEPPwRFNAx17dskvSyKFXCov5GH8IYV4+IWFWqlleOHynOcBAGrz8agnv0jp1Qw+1xl4GScG6Nol19e1yofudcUS02WoQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B43A1AED; Sun, 15 Dec 2024 20:09:31 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A2C263F58B; Sun, 15 Dec 2024 20:08:59 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev Subject: [PATCH V3 5/7] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Date: Mon, 16 Dec 2024 09:38:29 +0530 Message-Id: <20241216040831.2448257-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds required field details for ID_AA64DFR1_EL1, and also drops dummy ftr_raz[] array which is now redundant. These register fields will be used to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 later. The register fields have been marked as FTR_STRICT, unless there is a known variation in practice. Cc: Catalin Marinas Cc: Will Deacon cc: Mark Brown Cc: Mark Rutland Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- Changes in V3: - Updated the commit message - Marked ID_AA64DFR1_EL1.ABLE as FTR_NONSTRICT in ftr_id_aa64dfr1[] arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6ce71f444ed8..0dc22fde104e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -534,6 +534,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] =3D { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _ABL_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _DPFZS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EB= EP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_IT= E_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _ABLE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _PMICNTR_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SP= MU_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _CTX_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _WRPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1= _BRPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SY= SPMUID_SHIFT, 8, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_mvfr0[] =3D { ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_= SHIFT, 4, 0), @@ -720,10 +735,6 @@ static const struct arm64_ftr_bits ftr_single32[] =3D { ARM64_FTR_END, }; =20 -static const struct arm64_ftr_bits ftr_raz[] =3D { - ARM64_FTR_END, -}; - #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ .sys_id =3D id, \ .reg =3D &(struct arm64_ftr_reg){ \ @@ -796,7 +807,7 @@ static const struct __ftr_reg_entry { =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1), =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 6 */ ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), --=20 2.25.1 From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CE1CC1CEAD6; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52D011AED; Sun, 15 Dec 2024 20:09:36 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1A3A13F58B; Sun, 15 Dec 2024 20:09:03 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org Subject: [PATCH V3 6/7] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Date: Mon, 16 Dec 2024 09:38:30 +0530 Message-Id: <20241216040831.2448257-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. This adds a new helper __init_el2_fgt2() initializing this new FEAT_FGT2 based fine grained registers. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. This updates __init_el2_debug() as required for FEAT_Debugv8p9. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: Marc Zyngier Cc: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual --- Changes in V3: - Dropped MDCR_EL3.TDA boot requirement from documentation (separate series) - Dropped MDCR_EL2_EBWE definition as MDCR_EL2 is now defined in tools sysr= eg https://lore.kernel.org/all/20241211065425.1106683-1-anshuman.khandual@arm.= com/ Documentation/arch/arm64/booting.rst | 18 ++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 26 ++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index 3278fb4bf219..054cfe1cad18 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -288,6 +288,12 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. =20 + For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: =20 - If EL3 is present and the kernel is entered at EL2: @@ -322,6 +328,18 @@ Before jumping into the kernel, the following conditio= ns must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. =20 + For CPUs with FEAT_Debugv8p9 extension present: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): =20 - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 4ef52d7245bb..2fbfe27d38b5 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -105,6 +105,13 @@ // to own it. =20 .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + orr x2, x2, #MDCR_EL2_EBWE +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm =20 @@ -244,6 +251,24 @@ .Lskip_gcs_\@: .endm =20 +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HDFGRTR2_EL2, x0 +.Lskip_dbg_v8p9_\@: +.Lskip_fgt2_\@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -283,6 +308,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 __init_el2_gcs .endm =20 --=20 2.25.1 From nobody Thu Dec 18 05:07:16 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3A2061CEAD6 for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE48B1AED; Sun, 15 Dec 2024 20:09:40 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C641A3F58B; Sun, 15 Dec 2024 20:09:08 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev Subject: [PATCH V3 7/7] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Date: Mon, 16 Dec 2024 09:38:31 +0530 Message-Id: <20241216040831.2448257-8-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241216040831.2448257-1-anshuman.khandual@arm.com> References: <20241216040831.2448257-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently there can be maximum 16 breakpoints, and 16 watchpoints available on a given platform - as detected from ID_AA64DFR0_EL1.[BRPs|WRPs] register fields. But these breakpoint, and watchpoints can be extended further up to 64 via a new arch feature FEAT_Debugv8p9. This first enables banked access for the breakpoint and watchpoint register set via MDSELR_EL1, extended exceptions via MDSCR_EL1.EMBWE and determining available breakpoints and watchpoints in the platform from ID_AA64DFR1_EL1, when FEAT_Debugv8p9 is enabled. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- Changes in V3: - Used SYS_FIELD_PREP() in read_wb_reg() and write_wb_reg() - Added MAX_PER_BANK based BUILD_BUG_ON() tests in arch_hw_breakpoint_init() - Dropped local variables i.e mdsel_bank and index - Derived bank and index from MAX_PER_BANK as required arch/arm64/include/asm/debug-monitors.h | 1 + arch/arm64/include/asm/hw_breakpoint.h | 47 ++++++++++++++++++------ arch/arm64/kernel/debug-monitors.c | 15 +++++--- arch/arm64/kernel/hw_breakpoint.c | 48 +++++++++++++++++++++++-- 4 files changed, 95 insertions(+), 16 deletions(-) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/a= sm/debug-monitors.h index 8f6ba31b8658..56b89a582a0d 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -20,6 +20,7 @@ #define DBG_MDSCR_KDE (1 << 13) #define DBG_MDSCR_MDE (1 << 15) #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) +#define DBG_MDSCR_EMBWE (1UL << 32) =20 #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) =20 diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/as= m/hw_breakpoint.h index bd81cf17744a..e48273b64109 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -79,8 +79,9 @@ static inline void decode_ctrl_reg(u32 reg, * Limits. * Changing these will require modifications to the register accessors. */ -#define ARM_MAX_BRP 16 -#define ARM_MAX_WRP 16 +#define ARM_MAX_BRP 64 +#define ARM_MAX_WRP 64 +#define MAX_PER_BANK 16 =20 /* Virtual debug register bases. */ #define AARCH64_DBG_REG_BVR 0 @@ -94,6 +95,14 @@ static inline void decode_ctrl_reg(u32 reg, #define AARCH64_DBG_REG_NAME_WVR wvr #define AARCH64_DBG_REG_NAME_WCR wcr =20 +static inline bool is_debug_v8p9_enabled(void) +{ + u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + int dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_D= ebugVer_SHIFT); + + return dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9; +} + /* Accessor macros for the debug registers. */ #define AARCH64_DBG_READ(N, REG, VAL) do {\ VAL =3D read_sysreg(dbg##REG##N##_el1);\ @@ -138,19 +147,37 @@ static inline void ptrace_hw_copy_thread(struct task_= struct *task) /* Determine number of BRP registers available. */ static inline int get_num_brps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_BRPs_SHIFT); + u64 dfr0, dfr1; + int dver, brps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_Debug= Ver_SHIFT); + if (dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + brps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_BRPs_SHIFT, 8); + } else { + brps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_BRPs= _SHIFT); + } + return 1 + brps; } =20 /* Determine number of WRP registers available. */ static inline int get_num_wrps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_WRPs_SHIFT); + u64 dfr0, dfr1; + int dver, wrps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_Debug= Ver_SHIFT); + if (dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + wrps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_WRPs_SHIFT, 8); + } else { + wrps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_WRPs= _SHIFT); + } + return 1 + wrps; } =20 #ifdef CONFIG_CPU_PM diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-m= onitors.c index 58f047de3e1c..50779c68f11e 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include =20 @@ -34,7 +35,7 @@ u8 debug_monitors_arch(void) /* * MDSCR access routines. */ -static void mdscr_write(u32 mdscr) +static void mdscr_write(u64 mdscr) { unsigned long flags; flags =3D local_daif_save(); @@ -43,7 +44,7 @@ static void mdscr_write(u32 mdscr) } NOKPROBE_SYMBOL(mdscr_write); =20 -static u32 mdscr_read(void) +static u64 mdscr_read(void) { return read_sysreg(mdscr_el1); } @@ -79,7 +80,7 @@ static DEFINE_PER_CPU(int, kde_ref_count); =20 void enable_debug_monitors(enum dbg_active_el el) { - u32 mdscr, enable =3D 0; + u64 mdscr, enable =3D 0; =20 WARN_ON(preemptible()); =20 @@ -90,6 +91,9 @@ void enable_debug_monitors(enum dbg_active_el el) this_cpu_inc_return(kde_ref_count) =3D=3D 1) enable |=3D DBG_MDSCR_KDE; =20 + if (is_debug_v8p9_enabled()) + enable |=3D DBG_MDSCR_EMBWE; + if (enable && debug_enabled) { mdscr =3D mdscr_read(); mdscr |=3D enable; @@ -100,7 +104,7 @@ NOKPROBE_SYMBOL(enable_debug_monitors); =20 void disable_debug_monitors(enum dbg_active_el el) { - u32 mdscr, disable =3D 0; + u64 mdscr, disable =3D 0; =20 WARN_ON(preemptible()); =20 @@ -111,6 +115,9 @@ void disable_debug_monitors(enum dbg_active_el el) this_cpu_dec_return(kde_ref_count) =3D=3D 0) disable &=3D ~DBG_MDSCR_KDE; =20 + if (is_debug_v8p9_enabled()) + disable &=3D ~DBG_MDSCR_EMBWE; + if (disable) { mdscr =3D mdscr_read(); mdscr &=3D disable; diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index 722ac45f9f7b..e9c87fb0e772 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -103,7 +103,7 @@ int hw_breakpoint_slots(int type) WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ WRITE_WB_REG_CASE(OFF, 15, REG, VAL) =20 -static u64 read_wb_reg(int reg, int n) +static u64 __read_wb_reg(int reg, int n) { u64 val =3D 0; =20 @@ -118,9 +118,31 @@ static u64 read_wb_reg(int reg, int n) =20 return val; } + +static u64 read_wb_reg(int reg, int n) +{ + unsigned long flags; + u64 val; + + if (!is_debug_v8p9_enabled()) + return __read_wb_reg(reg, n); + + /* + * Bank selection in MDSELR_EL1, followed by an indexed read from + * breakpoint (or watchpoint) registers cannot be interrupted, as + * that might cause misread from the wrong targets instead. Hence + * this requires mutual exclusion. + */ + local_irq_save(flags); + write_sysreg_s(SYS_FIELD_PREP(MDSELR_EL1, BANK, n / MAX_PER_BANK), SYS_MD= SELR_EL1); + isb(); + val =3D __read_wb_reg(reg, n % MAX_PER_BANK); + local_irq_restore(flags); + return val; +} NOKPROBE_SYMBOL(read_wb_reg); =20 -static void write_wb_reg(int reg, int n, u64 val) +static void __write_wb_reg(int reg, int n, u64 val) { switch (reg + n) { GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val= ); @@ -132,6 +154,26 @@ static void write_wb_reg(int reg, int n, u64 val) } isb(); } + +static void write_wb_reg(int reg, int n, u64 val) +{ + unsigned long flags; + + if (!is_debug_v8p9_enabled()) + return __write_wb_reg(reg, n, val); + + /* + * Bank selection in MDSELR_EL1, followed by an indexed read from + * breakpoint (or watchpoint) registers cannot be interrupted, as + * that might cause misread from the wrong targets instead. Hence + * this requires mutual exclusion. + */ + local_irq_save(flags); + write_sysreg_s(SYS_FIELD_PREP(MDSELR_EL1, BANK, n / MAX_PER_BANK), SYS_MD= SELR_EL1); + isb(); + __write_wb_reg(reg, n % MAX_PER_BANK, val); + local_irq_restore(flags); +} NOKPROBE_SYMBOL(write_wb_reg); =20 /* @@ -1005,6 +1047,8 @@ static int __init arch_hw_breakpoint_init(void) =20 /* Register cpu_suspend hw breakpoint restore hook */ cpu_suspend_set_dbg_restorer(hw_breakpoint_reset); + BUILD_BUG_ON((ARM_MAX_BRP % MAX_PER_BANK) !=3D 0); + BUILD_BUG_ON((ARM_MAX_WRP % MAX_PER_BANK) !=3D 0); =20 return ret; } --=20 2.25.1