From nobody Wed Dec 17 19:39:24 2025 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98A191547E4 for ; Mon, 16 Dec 2024 03:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318836; cv=none; b=gyU4y8XugfGspkN0UfLcbsr7727UIG0/W2GvK3X6dGUXqqHkaRWBpkJyYoUZCUgI2GtM7xwNiCXn3pjSS+IIwdQbrjq9kxVRBQ8wGPweHxaWubFYenqgLgKraITwe7U6ym2AMJpHjbIwLPqfBjPBU3qIutJlZHCO9gAb8bulpjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318836; c=relaxed/simple; bh=dTxUYroMkkS6yYemGfRDl3QZZF8yWEGI0ldNnuZpgB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DPjRvmmYZnomh6GnX2+uShPycCUdxeuz3rByEr+uwIW0j4rwojkswyMDjZMUo/nHKFCOT2J2/CLBXpxSItFhpvdMbCY3Zi1hCWqFBVPLLAK3x9+arJ3S9jzn29zeBxBCo+JVxMZMJtAB3ZJCrF9BycNhIYyw12JIWpZyuMdpABI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=ot8+dGVh; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="ot8+dGVh" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6253B2C04EA; Mon, 16 Dec 2024 16:13:49 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1734318829; bh=dAFqooAZLwvN37SBMg+rsgoIlHkI6A6yh+3k1eVyeJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ot8+dGVhy2xDkIe6Wz4Fn0nI6GztPKBq7X5Hn+pZVSSKgyR7IrV+QXvKH3zsyUgT4 25WuR//1ggXmv+MCdfH/IKjwN+X7WYFx1Ft+bl4a5jYAf2GIFejJr06Ca7TzJHF+T+ Ml5zHWHqJNOnPzZHo8sPFcd0XC28XBEJeZoo0fjqBrEH/wJ3CH0W3TxWbVR3eN2YlF wU3Iq8tcAjJjW83xWRCnIQDaZr3mczp3BHS2VVBXWHdLE7HOYGBQnUvaQ9TncYDEX6 /Pp+plJdS0D5TEGjm/t4/GQxb5QGMAJlzcinsnM1T8+XwtaZzLDisfyQjXEXoxiek7 Yv+uo+6AxEP/Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 16 Dec 2024 16:13:49 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id EEC3013EE9C; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id EBA452803EA; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v2 4/4] net: mdio: Add RTL9300 MDIO driver Date: Mon, 16 Dec 2024 16:13:46 +1300 Message-ID: <20241216031346.2626805-5-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> References: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.4 cv=BNQQr0QG c=1 sm=1 tr=0 ts=675f9aed a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=RZcAm9yDv7YA:10 a=PLFZzS6RjvMAOK3DgDUA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Content-Type: text/plain; charset="utf-8" Add a driver for the MDIO controller on the RTL9300 family of Ethernet switches with integrated SoC. There are 4 physical SMI interfaces on the RTL9300 but access is done using the switch ports so a single MDIO bus is presented to the rest of the system. Signed-off-by: Chris Packham --- Notes: Changes in v2: - Add clause 22 support - Remove commented out code - Formatting cleanup - Set MAX_PORTS correctly for MDIO interface - Fix off-by-one error in pn check drivers/net/mdio/Kconfig | 7 + drivers/net/mdio/Makefile | 1 + drivers/net/mdio/mdio-realtek-rtl.c | 341 ++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/net/mdio/mdio-realtek-rtl.c diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig index 4a7a303be2f7..0c6240c4a7e9 100644 --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig @@ -185,6 +185,13 @@ config MDIO_IPQ8064 This driver supports the MDIO interface found in the network interface units of the IPQ8064 SoC =20 +config MDIO_REALTEK_RTL + tristate "Realtek RTL9300 MDIO interface support" + depends on MACH_REALTEK_RTL || COMPILE_TEST + help + This driver supports the MDIO interface found in the Realtek + RTL9300 family of Ethernet switches with integrated SoC. + config MDIO_REGMAP tristate help diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile index 1015f0db4531..2cd8b491f301 100644 --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MDIO_MOXART) +=3D mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) +=3D mdio-mscc-miim.o obj-$(CONFIG_MDIO_MVUSB) +=3D mdio-mvusb.o obj-$(CONFIG_MDIO_OCTEON) +=3D mdio-octeon.o +obj-$(CONFIG_MDIO_REALTEK_RTL) +=3D mdio-realtek-rtl.o obj-$(CONFIG_MDIO_REGMAP) +=3D mdio-regmap.o obj-$(CONFIG_MDIO_SUN4I) +=3D mdio-sun4i.o obj-$(CONFIG_MDIO_THUNDER) +=3D mdio-thunder.o diff --git a/drivers/net/mdio/mdio-realtek-rtl.c b/drivers/net/mdio/mdio-re= altek-rtl.c new file mode 100644 index 000000000000..a13b84279138 --- /dev/null +++ b/drivers/net/mdio/mdio-realtek-rtl.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MDIO controller for RTL9300 switches with integrated SoC. + * + * The MDIO communication is abstracted by the switch. At the software lev= el + * communication uses the switch port to address the PHY with the actual M= DIO + * bus and address having been setup via the realtek,smi-address property. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMI_GLB_CTRL 0x000 +#define GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf)) +#define SMI_PORT0_15_POLLING_SEL 0x008 +#define SMI_ACCESS_PHY_CTRL_0 0x170 +#define SMI_ACCESS_PHY_CTRL_1 0x174 +#define PHY_CTRL_RWOP BIT(2) +#define PHY_CTRL_TYPE BIT(1) +#define PHY_CTRL_CMD BIT(0) +#define PHY_CTRL_FAIL BIT(25) +#define SMI_ACCESS_PHY_CTRL_2 0x178 +#define SMI_ACCESS_PHY_CTRL_3 0x17c +#define SMI_PORT0_5_ADDR_CTRL 0x180 + +#define MAX_PORTS 28 +#define MAX_SMI_BUSSES 4 +#define MAX_SMI_ADDR 0x1f + +struct realtek_mdio_priv { + struct regmap *regmap; + u8 smi_bus[MAX_PORTS]; + u8 smi_addr[MAX_PORTS]; + bool smi_bus_isc45[MAX_SMI_BUSSES]; + u32 reg_base; +}; + +static int realtek_mdio_wait_ready(struct realtek_mdio_priv *priv) +{ + struct regmap *regmap =3D priv->regmap; + u32 reg_base =3D priv->reg_base; + u32 val; + + return regmap_read_poll_timeout(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 500); +} + +static int realtek_mdio_read_c22(struct mii_bus *bus, int phy_id, int regn= um) +{ + struct realtek_mdio_priv *priv =3D bus->priv; + struct regmap *regmap =3D priv->regmap; + u32 reg_base =3D priv->reg_base; + u32 val; + int err; + + err =3D realtek_mdio_wait_ready(priv); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, phy_id << = 16); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + regnum << 20 | 0x1f << 15 | 0xfff << 3 | PHY_CTRL_CMD); + if (err) + return err; + + err =3D realtek_mdio_wait_ready(priv); + if (err) + return err; + + err =3D regmap_read(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return val & 0xffff; +} + +static int realtek_mdio_write_c22(struct mii_bus *bus, int phy_id, int reg= num, u16 value) +{ + struct realtek_mdio_priv *priv =3D bus->priv; + struct regmap *regmap =3D priv->regmap; + u32 reg_base =3D priv->reg_base; + u32 val; + int err; + + err =3D realtek_mdio_wait_ready(priv); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_0, BIT(phy_id= )); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, value << 1= 6); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + regnum << 20 | 0x1f << 15 | 0xfff << 3 | PHY_CTRL_RWOP | PHY_CTRL_C= MD); + if (err) + return err; + + err =3D regmap_read_poll_timeout(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int realtek_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_= addr, int regnum) +{ + struct realtek_mdio_priv *priv =3D bus->priv; + struct regmap *regmap =3D priv->regmap; + u32 reg_base =3D priv->reg_base; + u32 val; + int err; + + err =3D realtek_mdio_wait_ready(priv); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, phy_id << = 16); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_3, + dev_addr << 16 | (regnum & 0xffff)); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_TYPE | PHY_CTRL_CMD); + if (err) + return err; + + err =3D realtek_mdio_wait_ready(priv); + if (err) + return err; + + err =3D regmap_read(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return val & 0xffff; +} + +static int realtek_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev= _addr, + int regnum, u16 value) +{ + struct realtek_mdio_priv *priv =3D bus->priv; + struct regmap *regmap =3D priv->regmap; + u32 reg_base =3D priv->reg_base; + u32 val; + int err; + + err =3D realtek_mdio_wait_ready(priv); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_0, BIT(phy_id= )); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, value << 1= 6); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_3, + dev_addr << 16 | (regnum & 0xffff)); + if (err) + return err; + + err =3D regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_RWOP | PHY_CTRL_TYPE | PHY_CTRL_CMD); + if (err) + return err; + + err =3D regmap_read_poll_timeout(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int realtek_mdiobus_init(struct realtek_mdio_priv *priv) +{ + u32 glb_ctrl_mask =3D 0, glb_ctrl_val =3D 0; + struct regmap *regmap =3D priv->regmap; + u32 reg_base =3D priv->reg_base; + u32 port_addr[5] =3D { 0 }; + u32 poll_sel[2] =3D { 0 }; + int i, err; + + /* Associate the port with the SMI interface and PHY */ + for (i =3D 0; i < MAX_PORTS; i++) { + int pos; + + if (priv->smi_bus[i] > 3) + continue; + + pos =3D (i % 6) * 5; + port_addr[i / 6] |=3D priv->smi_addr[i] << pos; + + pos =3D (i % 16) * 2; + poll_sel[i / 16] |=3D priv->smi_bus[i] << pos; + } + + /* Put the interfaces into C45 mode if required */ + for (i =3D 0; i < MAX_SMI_BUSSES; i++) { + if (priv->smi_bus_isc45[i]) { + glb_ctrl_mask |=3D GLB_CTRL_INTF_SEL(i); + glb_ctrl_val |=3D GLB_CTRL_INTF_SEL(i); + } + } + + err =3D regmap_bulk_write(regmap, reg_base + SMI_PORT0_5_ADDR_CTRL, + port_addr, 5); + if (err) + return err; + + err =3D regmap_bulk_write(regmap, reg_base + SMI_PORT0_15_POLLING_SEL, + poll_sel, 2); + if (err) + return err; + + err =3D regmap_update_bits(regmap, reg_base + SMI_GLB_CTRL, + glb_ctrl_mask, glb_ctrl_val); + if (err) + return err; + + return 0; +} + +static int realtek_mdiobus_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct realtek_mdio_priv *priv; + struct fwnode_handle *child; + struct mii_bus *bus; + int err; + + bus =3D devm_mdiobus_alloc_size(dev, sizeof(*priv)); + if (!bus) + return -ENOMEM; + + bus->name =3D "Reaktek Switch MDIO Bus"; + bus->read =3D realtek_mdio_read_c22; + bus->write =3D realtek_mdio_write_c22; + bus->read_c45 =3D realtek_mdio_read_c45; + bus->write_c45 =3D realtek_mdio_write_c45; + bus->parent =3D dev; + priv =3D bus->priv; + + priv->regmap =3D syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + err =3D device_property_read_u32(dev, "reg", &priv->reg_base); + if (err) + return err; + + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + + device_for_each_child_node(dev, child) { + u32 pn, smi_addr[2]; + + err =3D fwnode_property_read_u32(child, "reg", &pn); + if (err) + return err; + + if (pn >=3D MAX_PORTS) + return dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn); + + err =3D fwnode_property_read_u32_array(child, "realtek,smi-address", smi= _addr, 2); + if (err) { + smi_addr[0] =3D 0; + smi_addr[1] =3D pn; + } + + if (smi_addr[0] > MAX_SMI_BUSSES) + return dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", + smi_addr[0]); + + if (smi_addr[1] > MAX_SMI_ADDR) + return dev_err_probe(dev, -EINVAL, "illegal smi addr %d\n", smi_addr[1]= ); + + if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45")) + priv->smi_bus_isc45[smi_addr[0]] =3D true; + + priv->smi_bus[pn] =3D smi_addr[0]; + priv->smi_addr[pn] =3D smi_addr[1]; + } + + err =3D realtek_mdiobus_init(priv); + if (err) + return dev_err_probe(dev, err, "failed to initialise MDIO bus controller= \n"); + + err =3D devm_of_mdiobus_register(dev, bus, dev->of_node); + if (err) + return dev_err_probe(dev, err, "cannot register MDIO bus\n"); + + return 0; +} + +static const struct of_device_id realtek_mdio_ids[] =3D { + { .compatible =3D "realtek,rtl9301-mdio" }, + { .compatible =3D "realtek,rtl9302b-mdio" }, + { .compatible =3D "realtek,rtl9302c-mdio" }, + { .compatible =3D "realtek,rtl9303-mdio" }, + {} +}; +MODULE_DEVICE_TABLE(of, realtek_mdio_ids); + +static struct platform_driver rtl9300_mdio_driver =3D { + .probe =3D realtek_mdiobus_probe, + .driver =3D { + .name =3D "mdio-rtl9300", + .of_match_table =3D realtek_mdio_ids, + }, +}; + +module_platform_driver(rtl9300_mdio_driver); + +MODULE_DESCRIPTION("RTL9300 MDIO driver"); +MODULE_LICENSE("GPL"); --=20 2.47.1