From nobody Wed Dec 17 19:55:22 2025 Received: from mail-m83156.xmail.ntesmail.com (mail-m83156.xmail.ntesmail.com [156.224.83.156]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58BD9653; Mon, 16 Dec 2024 03:48:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.224.83.156 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734320913; cv=none; b=dDyVTJi2OmoLS9bsseKKoK5NSs7ToOBcuWFtz9M3eCW9Zc2EzmFGPrdYqGswQAerthDPAk0f+pBXU+b+x9TOVlG0QK6vrgd1CKanWjCTQNEVn92ud02kdOzQQCZETa0+AVYUrlBuGXP/bvsHzHRey2rV4PqG0s/Mu/rWnHgkPBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734320913; c=relaxed/simple; bh=SAeeRt9nfXT4+x4Ry4uhieP25OfvOFVy/Z38zGydqWg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Bxd9hVr7EwH+12M1KXk1y3kugyCv/v0WaQTzaNVnrFZKp581/Vco21K93+xAbH5ZJQAwJxlKmZql+RR4A05EbjrPyQogSy5ncVB5JZGXRk9ZkTRAORFYtZzWrC9/4B0rz7LNlCwiXUgGnkYQ1cflTmajg574d5YAP+D3CxYi5zo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=WUPrHAs2; arc=none smtp.client-ip=156.224.83.156 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="WUPrHAs2" Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 5cf79914; Mon, 16 Dec 2024 11:13:00 +0800 (GMT+08:00) From: Damon Ding To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rfoss@kernel.org, vkoul@kernel.org, sebastian.reichel@collabora.com, cristian.ciocaltea@collabora.com, l.stach@pengutronix.de, andy.yan@rock-chips.com, hjc@rock-chips.com, algea.cao@rock-chips.com, kever.yang@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Damon Ding Subject: [PATCH v2 06/11] drm/bridge: analogix_dp: Add support for phy configuration. Date: Mon, 16 Dec 2024 11:12:20 +0800 Message-Id: <20241216031225.3746-7-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241216031225.3746-1-damon.ding@rock-chips.com> References: <20241216031225.3746-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkhDGFZKHh8fTxpLS0xKGB9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a93cd746ea603a3kunm5cf79914 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OS46LSo*CzIcMiFLSUlPQgkK MypPFBpVSlVKTEhPSEpDTENKQ0tCVTMWGhIXVR8aFhQVVR8SFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPT0hPNwY+ DKIM-Signature: a=rsa-sha256; b=WUPrHAs2JjsO2ORWmSawb4Zhj7h3Wtn/TENNjgJTjNlfOMxUVLYm+ppsA0UuKWze+Am4nBNHEUxD2ccpE1yXm40b15/WsZFxPZDBeCnBzxesTgNn/T71Vw2/RZtN3OINd7oXe5jz/cN70Lzej/ZBTmXHF//nwQfI/Ghe5emftis=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=fLnJTP9Scjrv+H234l17f44byuYhFDRw9PdboVjk7gw=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add support to configurate link rate, lane count, voltage swing and pre-emphasis with phy_configure(). It is helpful in application scenarios where analogix controller is mixed with the phy of other vendors. Signed-off-by: Damon Ding --- Changes in v2: - remove needless assignments for phy_configure() - remove unnecessary changes for phy_power_on()/phy_power_off() --- .../drm/bridge/analogix/analogix_dp_core.c | 1 + .../gpu/drm/bridge/analogix/analogix_dp_reg.c | 56 +++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/g= pu/drm/bridge/analogix/analogix_dp_core.c index 6f10d88a34c5..9429c50cc1bc 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1696,6 +1696,7 @@ int analogix_dp_resume(struct analogix_dp_device *dp) if (dp->plat_data->power_on) dp->plat_data->power_on(dp->plat_data); =20 + phy_set_mode(dp->phy, PHY_MODE_DP); phy_power_on(dp->phy); =20 analogix_dp_init_dp(dp); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gp= u/drm/bridge/analogix/analogix_dp_reg.c index 3afc73c858c4..613ce504bea6 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include =20 @@ -513,10 +514,25 @@ void analogix_dp_enable_sw_function(struct analogix_d= p_device *dp) void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwt= ype) { u32 reg; + int ret; =20 reg =3D bwtype; if ((bwtype =3D=3D DP_LINK_BW_2_7) || (bwtype =3D=3D DP_LINK_BW_1_62)) writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); + + if (dp->phy) { + union phy_configure_opts phy_cfg =3D {0}; + + phy_cfg.dp.lanes =3D dp->link_train.lane_count; + phy_cfg.dp.link_rate =3D + drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; + phy_cfg.dp.set_rate =3D true; + ret =3D phy_configure(dp->phy, &phy_cfg); + if (ret && ret !=3D -EOPNOTSUPP) { + dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret); + return; + } + } } =20 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bw= type) @@ -530,9 +546,22 @@ void analogix_dp_get_link_bandwidth(struct analogix_dp= _device *dp, u32 *bwtype) void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) { u32 reg; + int ret; =20 reg =3D count; writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); + + if (dp->phy) { + union phy_configure_opts phy_cfg =3D {0}; + + phy_cfg.dp.lanes =3D dp->link_train.lane_count; + phy_cfg.dp.set_lanes =3D true; + ret =3D phy_configure(dp->phy, &phy_cfg); + if (ret && ret !=3D -EOPNOTSUPP) { + dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret); + return; + } + } } =20 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) @@ -546,10 +575,37 @@ void analogix_dp_get_lane_count(struct analogix_dp_de= vice *dp, u32 *count) void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) { u8 lane; + int ret; =20 for (lane =3D 0; lane < dp->link_train.lane_count; lane++) writel(dp->link_train.training_lane[lane], dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); + + if (dp->phy) { + union phy_configure_opts phy_cfg =3D {0}; + + for (lane =3D 0; lane < dp->link_train.lane_count; lane++) { + u8 training_lane =3D dp->link_train.training_lane[lane]; + u8 vs, pe; + + vs =3D (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> + DP_TRAIN_VOLTAGE_SWING_SHIFT; + pe =3D (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT; + phy_cfg.dp.voltage[lane] =3D vs; + phy_cfg.dp.pre[lane] =3D pe; + } + + phy_cfg.dp.lanes =3D dp->link_train.lane_count; + phy_cfg.dp.link_rate =3D + drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; + phy_cfg.dp.set_voltages =3D true; + ret =3D phy_configure(dp->phy, &phy_cfg); + if (ret && ret !=3D -EOPNOTSUPP) { + dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret); + return; + } + } } =20 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 l= ane) --=20 2.34.1