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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 5cf798ef; Mon, 16 Dec 2024 11:12:50 +0800 (GMT+08:00) From: Damon Ding To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rfoss@kernel.org, vkoul@kernel.org, sebastian.reichel@collabora.com, cristian.ciocaltea@collabora.com, l.stach@pengutronix.de, andy.yan@rock-chips.com, hjc@rock-chips.com, algea.cao@rock-chips.com, kever.yang@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Damon Ding Subject: [PATCH v2 01/11] drm/rockchip: analogix_dp: Use formalized struct definition for grf field Date: Mon, 16 Dec 2024 11:12:15 +0800 Message-Id: <20241216031225.3746-2-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241216031225.3746-1-damon.ding@rock-chips.com> References: <20241216031225.3746-1-damon.ding@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh4dS1YeTBhPSU5MT0pJTR5WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0 NVSktLVUpCWQY+ X-HM-Tid: 0a93cd744b6503a3kunm5cf798ef X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NlE6Kjo5HjIVNiE3MkktOgwN QiMwCx5VSlVKTEhPSEpDTExJTkxMVTMWGhIXVR8aFhQVVR8SFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPTktDNwY+ DKIM-Signature: a=rsa-sha256; b=kLV6XObCAsNGJ4m9IVkDoSBHP3yxMWacf8JXsce4607myMKo40vfrqZxMZYCXTNZ0ugbluSpHLbPiwPp3scjMHdUOsZEU9c0tLXClXYsK4xE4CiW3SHi8VGXJ/0J5efSt0NCcx30NHVEqpBzyKw/kvw0TRh296nIOgToJ+T//bI=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=jSiNxVdDNc2EjHmkzB8d0czfEXAFHpn+E0ApTupnCwA=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" The formalized struct definition will makes grf field operations more concise and easier to extend. Signed-off-by: Damon Ding --- Changes in v2: - Initialize struct rockchip_dp_chip_data rk3399_edp/rk3288_dp in order of its members --- .../gpu/drm/rockchip/analogix_dp-rockchip.c | 77 +++++++++++-------- 1 file changed, 45 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/= drm/rockchip/analogix_dp-rockchip.c index d3341edfe4f4..871606a31ef1 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -32,26 +32,29 @@ =20 #include "rockchip_drm_drv.h" =20 -#define RK3288_GRF_SOC_CON6 0x25c -#define RK3288_EDP_LCDC_SEL BIT(5) -#define RK3399_GRF_SOC_CON20 0x6250 -#define RK3399_EDP_LCDC_SEL BIT(5) - -#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 =20 +#define GRF_REG_FIELD(_reg, _lsb, _msb) { \ + .reg =3D _reg, \ + .lsb =3D _lsb, \ + .msb =3D _msb, \ + .valid =3D true, \ + } + +struct rockchip_grf_reg_field { + u32 reg; + u32 lsb; + u32 msb; + bool valid; +}; + /** * struct rockchip_dp_chip_data - splite the grf setting of kind of chips - * @lcdsel_grf_reg: grf register offset of lcdc select - * @lcdsel_big: reg value of selecting vop big for eDP - * @lcdsel_lit: reg value of selecting vop little for eDP + * @lcdc_sel: grf register field of lcdc_sel * @chip_type: specific chip type */ struct rockchip_dp_chip_data { - u32 lcdsel_grf_reg; - u32 lcdsel_big; - u32 lcdsel_lit; + const struct rockchip_grf_reg_field lcdc_sel; u32 chip_type; }; =20 @@ -84,6 +87,26 @@ static struct rockchip_dp_device *pdata_encoder_to_dp(st= ruct analogix_dp_plat_da return container_of(plat_data, struct rockchip_dp_device, plat_data); } =20 +static int rockchip_grf_write(struct regmap *grf, u32 reg, u32 mask, u32 v= al) +{ + return regmap_write(grf, reg, (mask << 16) | (val & mask)); +} + +static int rockchip_grf_field_write(struct regmap *grf, + const struct rockchip_grf_reg_field *field, + u32 val) +{ + u32 mask; + + if (!field->valid) + return 0; + + mask =3D GENMASK(field->msb, field->lsb); + val <<=3D field->lsb; + + return rockchip_grf_write(grf, field->reg, mask, val); +} + static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) { reset_control_assert(dp->rst); @@ -181,7 +204,6 @@ static void rockchip_dp_drm_encoder_enable(struct drm_e= ncoder *encoder, struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; int ret; - u32 val; =20 crtc =3D rockchip_dp_drm_get_new_crtc(encoder, state); if (!crtc) @@ -192,24 +214,19 @@ static void rockchip_dp_drm_encoder_enable(struct drm= _encoder *encoder, if (old_crtc_state && old_crtc_state->self_refresh_active) return; =20 - ret =3D drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); - if (ret < 0) - return; - - if (ret) - val =3D dp->data->lcdsel_lit; - else - val =3D dp->data->lcdsel_big; - - DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); - ret =3D clk_prepare_enable(dp->grfclk); if (ret < 0) { DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret); return; } =20 - ret =3D regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); + ret =3D drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); + if (ret < 0) + return; + + DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); + + ret =3D rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, ret); if (ret !=3D 0) DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); =20 @@ -448,16 +465,12 @@ static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, = rockchip_dp_suspend, rockchip_dp_resume, NULL); =20 static const struct rockchip_dp_chip_data rk3399_edp =3D { - .lcdsel_grf_reg =3D RK3399_GRF_SOC_CON20, - .lcdsel_big =3D HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL), - .lcdsel_lit =3D HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL), + .lcdc_sel =3D GRF_REG_FIELD(0x6250, 5, 5), .chip_type =3D RK3399_EDP, }; =20 static const struct rockchip_dp_chip_data rk3288_dp =3D { - .lcdsel_grf_reg =3D RK3288_GRF_SOC_CON6, - .lcdsel_big =3D HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL), - .lcdsel_lit =3D HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL), + .lcdc_sel =3D GRF_REG_FIELD(0x025c, 5, 5), .chip_type =3D RK3288_DP, }; =20 --=20 2.34.1