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[79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:47 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:21 +0100 Subject: [PATCH 1/8] iio: dac: ad3552r-common: fix ad3541/2r ranges Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-1-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Fix ad3541/2r voltage ranges to be as per ad3542r datasheet, rev. C, table 38 (page 57). Fixes: 8f2b54824b28 ("drivers:iio:dac: Add AD3552R driver support") Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-common.c | 5 ++--- drivers/iio/dac/ad3552r.h | 8 +++----- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/iio/dac/ad3552r-common.c b/drivers/iio/dac/ad3552r-com= mon.c index 0f495df2e5ce..03e0864f5084 100644 --- a/drivers/iio/dac/ad3552r-common.c +++ b/drivers/iio/dac/ad3552r-common.c @@ -22,11 +22,10 @@ EXPORT_SYMBOL_NS_GPL(ad3552r_ch_ranges, "IIO_AD3552R"); =20 const s32 ad3542r_ch_ranges[AD3542R_MAX_RANGES][2] =3D { [AD3542R_CH_OUTPUT_RANGE_0__2P5V] =3D { 0, 2500 }, - [AD3542R_CH_OUTPUT_RANGE_0__3V] =3D { 0, 3000 }, [AD3542R_CH_OUTPUT_RANGE_0__5V] =3D { 0, 5000 }, [AD3542R_CH_OUTPUT_RANGE_0__10V] =3D { 0, 10000 }, - [AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V] =3D { -2500, 7500 }, - [AD3542R_CH_OUTPUT_RANGE_NEG_5__5V] =3D { -5000, 5000 } + [AD3542R_CH_OUTPUT_RANGE_NEG_5__5V] =3D { -5000, 5000 }, + [AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V] =3D { -2500, 7500 } }; EXPORT_SYMBOL_NS_GPL(ad3542r_ch_ranges, "IIO_AD3552R"); =20 diff --git a/drivers/iio/dac/ad3552r.h b/drivers/iio/dac/ad3552r.h index fd5a3dfd1d1c..4b5581039ae9 100644 --- a/drivers/iio/dac/ad3552r.h +++ b/drivers/iio/dac/ad3552r.h @@ -131,7 +131,7 @@ #define AD3552R_CH1_ACTIVE BIT(1) =20 #define AD3552R_MAX_RANGES 5 -#define AD3542R_MAX_RANGES 6 +#define AD3542R_MAX_RANGES 5 #define AD3552R_QUAD_SPI 2 =20 extern const s32 ad3552r_ch_ranges[AD3552R_MAX_RANGES][2]; @@ -189,16 +189,14 @@ enum ad3552r_ch_vref_select { enum ad3542r_ch_output_range { /* Range from 0 V to 2.5 V. Requires Rfb1x connection */ AD3542R_CH_OUTPUT_RANGE_0__2P5V, - /* Range from 0 V to 3 V. Requires Rfb1x connection */ - AD3542R_CH_OUTPUT_RANGE_0__3V, /* Range from 0 V to 5 V. Requires Rfb1x connection */ AD3542R_CH_OUTPUT_RANGE_0__5V, /* Range from 0 V to 10 V. Requires Rfb2x connection */ AD3542R_CH_OUTPUT_RANGE_0__10V, - /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */ - AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V, /* Range from -5 V to 5 V. Requires Rfb2x connection */ AD3542R_CH_OUTPUT_RANGE_NEG_5__5V, + /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */ + AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V, }; =20 enum ad3552r_ch_output_range { --=20 2.47.0 From nobody Wed Dec 17 21:29:50 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38A8C1D4342 for ; Mon, 16 Dec 2024 20:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734381474; cv=none; b=ZyaLdsd2To8h7oIZMgIqFLOqVXsv2zboSb36QNXoXeEYZLtRUcxZbsSNIEcmYoLqSt2l46bWAx1SnKk464DXVsrnkEGREnqc+PeLyQN+IQyy3d+cQ/b/rvUQg/PlBMd+DWklwhPPzEnaflvhTj+o0/MGot5ADLk+vTXxPlO1X1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734381474; c=relaxed/simple; bh=EHy5byuG6WbwH/WIoV7ON1vbDnc/Cuw0X71BpLN71pk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZcdNsn0uIAAtXsBRgRQCGwO/7zG9PBNSdkf/JmspVYkecoQEJzM83pt1Nl1WVHxWGHp2vwT1peQJ1qplu8n359cpSEpS9NfVEOtxhOBg5KONm8ipKNrVq9Y+Tf+MliURUHq3huuaafhwtKOrcfWmT+/SX+sYfMdl1h1B/zK0aYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=UnMC+KMd; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="UnMC+KMd" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso31421845e9.0 for ; Mon, 16 Dec 2024 12:37:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1734381470; x=1734986270; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/uTGbHwpheP7ZTAGPT3M61/wOimoSAI/DIQJehz+WSk=; b=UnMC+KMdsaOANflEqx+9YBwxWI6Q6M4V6CwRaPkbZZrJIDjEYuUVl8YZcgSSByG41p hNNkDFdWoyedjiLVtJk+4bQw53xLm8zH8OiezEqxdpogKw9X5PURHkRz2kkhVCn1PKjK NJ21VDjP4p7ECTjto3PWRLe0zY4Hdpv3W+Eo3If12+3ARArQ8N6MVrrnvPxn6o7daRQb A4xStepoMfteVSokDz7V+j2I/tDzRgUHE4jhbd80+Hx86ADagfO/kLXSNILW3l5Al7UD vLPrI9vMMhb1IHBP/J1IzFBx1nVVt/pnjGsgmPEtp3HMC/VWz7Kg9W9Yxz7dgx8crLjo yU/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734381470; x=1734986270; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/uTGbHwpheP7ZTAGPT3M61/wOimoSAI/DIQJehz+WSk=; b=xC3NYWNgJgDmEqaT5Q8BagJzXAxLA2JZ0WJmrz297x9Rnu1qE5TMKAESjlUVd3X1LY SjURFuqcq6PAEIMuD7xss+HpoefVB4En1el9EuJFAqjFeYSPiayg8GyRCkeujbhT4R5h g1pTNN1LnRNkoEZy3KaGdnIfEbZ9pT3JP6HeDF1jtlDZ6VvZ6L+4we1QITDK6Fip7swp 9IAqleGA4qjKSQsOQR6xgNKdkMVj1uhv/OCgmDIa5N5Lckp6CCRfEDN7jvwLtl1Dccyw kNJ3ERtYzB3rPydt6xc/hdiVJSEBBXLJY/CugTPFHtIsW7RMQGIauK+Yp4YdWiOz+Gn7 2p0g== X-Forwarded-Encrypted: i=1; AJvYcCW0MYcwSO9ZffPrnUvZpdpToBPDiNdzy3pyQW/L3aJ4IYVHaJO7dabJeCUNVg9EY/Hfhyc5K0SQiUmDOTQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxbU8iiZjpQIE14U8qRT9E9GuFfoCf6lEckhKfm/WcZNmKX2wjP csp/Ws0uI4tDl4SsB70zXOkIsbbckbGsDtMAJxyiTw646MgrVyJUlnEJjf1DjlA= X-Gm-Gg: ASbGncv7DmCAQAU19bXiX5hYmECqmp8vCMMtBa6Lspngn+CB/tUbeQYEGWZeaQyGYHC UfI2PPHpgROU1CrfQTl9EHAJ1LzpuvAbEeF5BSjpqGUyXBX5N1c4Q96FaZW2y+tAxK6nU/+HtLr cLb1tBBXI4/HodxLr53oKR3uNV2v1OIbnG66AfIFperojjF+8oHtkARJNVLrbem0h0AREj2nmhm 4Q0xZbSeVHbJjplPiSiQxMkLxntzEdrOeBIPPC4jRKquP1e+XQvHAHgFb7vJfn0AIZj2p3jCNof 6su/xwJDaAZvucsVxd//KNNhv2QyWCNbcg== X-Google-Smtp-Source: AGHT+IFNCWVvRQ7+f8hFiG7JbS7X72/g8umDwwWJ5AyRvkEjalQbahlAC2N4g/Q6vqIgCI1W5i1cmw== X-Received: by 2002:a05:600c:214a:b0:434:f7e3:bfbd with SMTP id 5b1f17b1804b1-4362aa947admr126088855e9.23.1734381469651; Mon, 16 Dec 2024 12:37:49 -0800 (PST) Received: from [127.0.1.1] (host-79-17-239-245.retail.telecomitalia.it. [79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:49 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:22 +0100 Subject: [PATCH 2/8] iio: dac: ad3552r-hs: clear reset status flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-2-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Clear reset status flag, to keep error status register clean after reset (ad3552r manual, rev B table 38). Fixes: 0b4d9fe58be8 ("iio: dac: ad3552r: add high-speed platform driver") Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-hs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c index 216c634f3eaf..8974df625670 100644 --- a/drivers/iio/dac/ad3552r-hs.c +++ b/drivers/iio/dac/ad3552r-hs.c @@ -329,6 +329,12 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *s= t) dev_info(st->dev, "Chip ID error. Expected 0x%x, Read 0x%x\n", AD3552R_ID, id); =20 + /* Clear reset error flag, see ad3552r manual, rev B table 38. */ + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, + AD3552R_MASK_RESET_STATUS, 1); + if (ret) + return ret; + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 0, 1); --=20 2.47.0 From nobody Wed Dec 17 21:29:50 2025 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24DFF1D5147 for ; Mon, 16 Dec 2024 20:37:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734381474; cv=none; b=LQTimGDDQDAobtr3P8yZmsPuRN32HLB+7CQNhma8Jmnd4HJezBLqbZZoCy8k4+MPoiF6RQSdam9YCflvo50gnFqc8cBiG6sB2jxsmve0gohUbaBFLZjMCI6y99zFDH0xxICj+1LAWeRuWg2BBPwC3I6GXnZLW+XaW/onmZStSPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734381474; c=relaxed/simple; bh=+lZHZ4OM8rTY/dhezSlahZGVnk6ol0FvguLhf0YmUqs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vh6RFSgPyXWwaUzGyeihh2Phy2V1OFxfdvOIW9Y2DQMzc8yiSHmWy+7PYRpMacIoHoVP8FI5gM2oiWGj914iXYhnuckqTFVwFtkJFK3TMCjnMeOi3bx5AtX8rz3ivbSLeYZapqQxvUZ6WRdSK84AMSmKJvNqZt6gImSWYQyW+m4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=cJBRdOaw; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="cJBRdOaw" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-38634c35129so3568228f8f.3 for ; Mon, 16 Dec 2024 12:37:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1734381471; x=1734986271; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xfrMkIY9tbM1sPwHCNYu/jKLHOMpHgwU9OMNQ7g5My0=; b=cJBRdOawEkOW40eACpx42wbMrSVUoqbwIGoTmQkGn5wEPVc5K1P1BdsyIbURYgQRvS hh/rB6IA9YGN7ouwRmQO+s2M9ifO3Cd8S7+vm0SygSqz+MPqIGQOj0YXqB+UPVpLTpab r5UWjw9x3eOHpiQ3pyvOaIQjNNb1QleehpbQKxv1msu57g/sEXe5lya/qmPXfrzTPxVO S1vuAW9hcx1qhNsnzNud0oMeUmmluX3/kWrtGooJnCN6cZK//yq2pLq2WJvqg0tK2fUF zq0WsUzBAnUcpC+mc8JkqaA2UgpoxhSHNk+ku2Aao24rqHLde9sn7SpVimOdLsGNIPtb wfyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734381471; x=1734986271; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xfrMkIY9tbM1sPwHCNYu/jKLHOMpHgwU9OMNQ7g5My0=; b=PxYmg49pzevb8annZ2yyApfLcktEJ0aUj29WUKmQgVtTehX0k+M3hrqskPn5CTRaMk 8XOrS+DurwgAi1Huc3uZfw8M1fQtjZuG0MXWmlv2o8Pi1QhODilfTUiYubikbLNt0y4j DhuIRi9w3LCmt07XoItXPUc3f2hQp+/vnAPve6FlC+E/rSARYdE+1n+n3rLGVKwVZY4S YXGAidONptdv3wec063CuJXHm+iMevp40CRZrIV52QZtu3rS3c0wQeoCq+lSH+3OIshC JJrCZqnLKW2PAi42BogXcg6rFsCqpynr1vfoJxQ8pTGpMZQpjBJFcnL+jqtcVZu1CVKV 1+6A== X-Forwarded-Encrypted: i=1; AJvYcCUBu1D6V32MoN+AC1rVGpRtXpfPYKIMsyUYq3758wGBdCW6MAdEk+vJcgreGHv6g9nGfcZUEbt951UhdzM=@vger.kernel.org X-Gm-Message-State: AOJu0Yw72As6f0zFkdeLCkzl2E2zQwWz6qwTnK35GtymFD0F48zajBzB o37rg0J0UCVmvvJYXvvfAq89tIUChglrHK8EyIpPnBq7IfuZ6IQ1iF4zHK+gelk= X-Gm-Gg: ASbGncs63+78qegAnyhy9g/6YJ4P6rl+qWkqDpwM6fQbjNoNUtkpNXHce+Hk3VoVcR7 VHZlC+/9zxlJphI1gA/gKiX1XVUhl4DVpjOk7ZhP0dWI5ezTHVXRZfmafLv/iEfMecySVweMate 07YaY8YBHUq1FOLf/u43TKuhO+9j1Im/HabL1/QuxTPimxE+ZyOr2RONSXbYJwdt/n+xjytf9sV 9LuMMVI7WGVWNHXtE5f2lgBxbs3WcRsY+UAz/6qCh5Hb/puPiPZnRkhyIlgZAdbjhpLqisWKhPc PKXr3MBXEwsv6bLtqtPftYvkE2bim0sTOg== X-Google-Smtp-Source: AGHT+IEoJVL8cN2aUSGgeveVOviRfZY6zn17RiTNDc/doqRdW4vCiAiD453Ku2lgjqBBhDniZ5kaaw== X-Received: by 2002:a05:6000:1acf:b0:385:f0dc:c9f4 with SMTP id ffacd0b85a97d-38880acd9dfmr12653328f8f.20.1734381470841; Mon, 16 Dec 2024 12:37:50 -0800 (PST) Received: from [127.0.1.1] (host-79-17-239-245.retail.telecomitalia.it. [79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:50 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:23 +0100 Subject: [PATCH 3/8] iio: dac: adi-axi-dac: modify stream enable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-3-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Change suggested from the AXI HDL team, modify the function axi_dac_data_stream_enable() to check for interface busy, to avoid possible issues when starting the stream. Fixes: e61d7178429a ("iio: dac: adi-axi-dac: extend features") Signed-off-by: Angelo Dureghello --- drivers/iio/dac/adi-axi-dac.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index b143f7ed6847..d02eb535b648 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -585,6 +585,17 @@ static int axi_dac_ddr_disable(struct iio_backend *bac= k) static int axi_dac_data_stream_enable(struct iio_backend *back) { struct axi_dac_state *st =3D iio_backend_get_priv(back); + int ret, val; + + ret =3D regmap_read_poll_timeout(st->regmap, + AXI_DAC_UI_STATUS_REG, val, + FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) =3D=3D 0, + 10, 100 * KILO); + if (ret) { + if (ret =3D=3D -ETIMEDOUT) + dev_err(st->dev, "AXI read timeout\n"); + return ret; + } =20 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE); --=20 2.47.0 From nobody Wed Dec 17 21:29:50 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A2C51D5176 for ; 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[79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:51 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:24 +0100 Subject: [PATCH 4/8] iio: backend: add API for interface configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-4-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello , Antoniu Miclaus X-Mailer: b4 0.14.1 From: Antoniu Miclaus Add backend support for setting and getting the interface type in use. Link: https://lore.kernel.org/linux-iio/20241129153546.63584-1-antoniu.micl= aus@analog.com/T/#m6d86939078d780512824f1540145aade38b0990b Signed-off-by: Antoniu Miclaus Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello --- This patch has been picked up from the Antoniu patchset still not accepted, and extended with the interface setter, fixing also namespace names to be between quotation marks. --- drivers/iio/industrialio-backend.c | 42 ++++++++++++++++++++++++++++++++++= ++++ include/linux/iio/backend.h | 19 +++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index 363281272035..6edc3e685f6a 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -636,6 +636,48 @@ ssize_t iio_backend_ext_info_set(struct iio_dev *indio= _dev, uintptr_t private, } EXPORT_SYMBOL_NS_GPL(iio_backend_ext_info_set, "IIO_BACKEND"); =20 +/** + * iio_backend_interface_type_get - get the interface type used. + * @back: Backend device + * @type: Interface type + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_interface_type_get(struct iio_backend *back, + enum iio_backend_interface_type *type) +{ + int ret; + + ret =3D iio_backend_op_call(back, interface_type_get, type); + if (ret) + return ret; + + if (*type >=3D IIO_BACKEND_INTERFACE_MAX) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(iio_backend_interface_type_get, "IIO_BACKEND"); + +/** + * iio_backend_interface_type_set - set the interface type used. + * @back: Backend device + * @type: Interface type + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_interface_type_set(struct iio_backend *back, + enum iio_backend_interface_type type) +{ + if (type >=3D IIO_BACKEND_INTERFACE_MAX) + return -EINVAL; + + return iio_backend_op_call(back, interface_type_set, type); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_interface_type_set, "IIO_BACKEND"); + /** * iio_backend_extend_chan_spec - Extend an IIO channel * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 10be00f3b120..2b7221099d8c 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -70,6 +70,15 @@ enum iio_backend_sample_trigger { IIO_BACKEND_SAMPLE_TRIGGER_MAX }; =20 +enum iio_backend_interface_type { + IIO_BACKEND_INTERFACE_SERIAL_LVDS, + IIO_BACKEND_INTERFACE_SERIAL_CMOS, + IIO_BACKEND_INTERFACE_SERIAL_SPI, + IIO_BACKEND_INTERFACE_SERIAL_DSPI, + IIO_BACKEND_INTERFACE_SERIAL_QSPI, + IIO_BACKEND_INTERFACE_MAX +}; + /** * struct iio_backend_ops - operations structure for an iio_backend * @enable: Enable backend. @@ -88,6 +97,8 @@ enum iio_backend_sample_trigger { * @extend_chan_spec: Extend an IIO channel. * @ext_info_set: Extended info setter. * @ext_info_get: Extended info getter. + * @interface_type_get: Interface type. + * @interface_type_set: Interface type setter. * @read_raw: Read a channel attribute from a backend device * @debugfs_print_chan_status: Print channel status into a buffer. * @debugfs_reg_access: Read or write register value of backend. @@ -128,6 +139,10 @@ struct iio_backend_ops { const char *buf, size_t len); int (*ext_info_get)(struct iio_backend *back, uintptr_t private, const struct iio_chan_spec *chan, char *buf); + int (*interface_type_get)(struct iio_backend *back, + enum iio_backend_interface_type *type); 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[79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:53 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:25 +0100 Subject: [PATCH 5/8] iio: dac: adi-axi-dac: add bus mode setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-5-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello The ad354xr requires DSPI mode to work in buffering mode, so backend needs to allow a mode selection between: SPI (entire ad35xxr family), DSPI (ad354xr), QSPI (ad355xr). Signed-off-by: Angelo Dureghello --- drivers/iio/dac/adi-axi-dac.c | 46 +++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index d02eb535b648..f7d22409e9b3 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -64,7 +64,7 @@ #define AXI_DAC_UI_STATUS_IF_BUSY BIT(4) #define AXI_DAC_CUSTOM_CTRL_REG 0x008C #define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24) -#define AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER BIT(2) +#define AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2) #define AXI_DAC_CUSTOM_CTRL_STREAM BIT(1) #define AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0) =20 @@ -95,6 +95,12 @@ enum { AXI_DAC_DATA_INTERNAL_RAMP_16BIT =3D 11, }; =20 +enum multi_io_mode { + AXI_DAC_MULTI_IO_MODE_SPI, + AXI_DAC_MULTI_IO_MODE_DSPI, + AXI_DAC_MULTI_IO_MODE_QSPI, +}; + struct axi_dac_info { unsigned int version; const struct iio_backend_info *backend_info; @@ -725,6 +731,43 @@ static int axi_dac_bus_reg_read(struct iio_backend *ba= ck, u32 reg, u32 *val, return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); } =20 +static int axi_dac_interface_type_set(struct iio_backend *back, + enum iio_backend_interface_type type) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + int mode, ival, ret; + + switch (type) { + case IIO_BACKEND_INTERFACE_SERIAL_SPI: + mode =3D AXI_DAC_MULTI_IO_MODE_SPI; + break; + case IIO_BACKEND_INTERFACE_SERIAL_DSPI: + mode =3D AXI_DAC_MULTI_IO_MODE_DSPI; + break; + case IIO_BACKEND_INTERFACE_SERIAL_QSPI: + mode =3D AXI_DAC_MULTI_IO_MODE_QSPI; + break; + default: + return -EINVAL; + } + + ret =3D regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, + AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, + FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode)); + if (ret) + return ret; + + ret =3D regmap_read_poll_timeout(st->regmap, + AXI_DAC_UI_STATUS_REG, ival, + FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) =3D=3D 0, + 10, 100 * KILO); + + if (ret =3D=3D -ETIMEDOUT) + dev_err(st->dev, "AXI read timeout\n"); + + return ret; +} + static void axi_dac_child_remove(void *data) { platform_device_unregister(data); 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[79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:55 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:26 +0100 Subject: [PATCH 6/8] iio: dac: ad3552r-hs: exit for error on wrong chip id Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-6-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Exit for error on wrong chip id, otherwise driver continues with wrong assumptions. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-hs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c index 8974df625670..e613eee7fc11 100644 --- a/drivers/iio/dac/ad3552r-hs.c +++ b/drivers/iio/dac/ad3552r-hs.c @@ -326,8 +326,9 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *st) =20 id |=3D val << 8; if (id !=3D st->model_data->chip_id) - dev_info(st->dev, "Chip ID error. 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[79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:57 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:27 +0100 Subject: [PATCH 7/8] iio: dac: ad3552r-hs: add ad3541/2r support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-7-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello A new fpga HDL has been developed from ADI to support ad354xr devices. Add support for ad3541r and ad3542r with following additions: - use common device_info structures for hs and non hs drivers, - DMA buffering, use DSPI mode for ad354xr and QSPI for ad355xr, - use DAC "instruction mode" when backend is not buffering, suggested from the ADI HDL team as more proper configuration mode to be used for all ad35xxr devices, - change samplerate to respect number of lanes. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-common.c | 44 +++++++ drivers/iio/dac/ad3552r-hs.c | 262 ++++++++++++++++++++++++++++++++---= ---- drivers/iio/dac/ad3552r.c | 36 ------ drivers/iio/dac/ad3552r.h | 8 ++ 4 files changed, 270 insertions(+), 80 deletions(-) diff --git a/drivers/iio/dac/ad3552r-common.c b/drivers/iio/dac/ad3552r-com= mon.c index 03e0864f5084..2a0dd18ca906 100644 --- a/drivers/iio/dac/ad3552r-common.c +++ b/drivers/iio/dac/ad3552r-common.c @@ -47,6 +47,50 @@ u16 ad3552r_calc_custom_gain(u8 p, u8 n, s16 goffs) } EXPORT_SYMBOL_NS_GPL(ad3552r_calc_custom_gain, "IIO_AD3552R"); =20 +const struct ad3552r_model_data ad3541r_model_data =3D { + .model_name =3D "ad3541r", + .chip_id =3D AD3541R_ID, + .num_hw_channels =3D 1, + .ranges_table =3D ad3542r_ch_ranges, + .num_ranges =3D ARRAY_SIZE(ad3542r_ch_ranges), + .requires_output_range =3D true, + .num_spi_data_lanes =3D 2, +}; +EXPORT_SYMBOL_NS_GPL(ad3541r_model_data, "IIO_AD3552R"); + +const struct ad3552r_model_data ad3542r_model_data =3D { + .model_name =3D "ad3542r", + .chip_id =3D AD3542R_ID, + .num_hw_channels =3D 2, + .ranges_table =3D ad3542r_ch_ranges, + .num_ranges =3D ARRAY_SIZE(ad3542r_ch_ranges), + .requires_output_range =3D true, + .num_spi_data_lanes =3D 2, +}; +EXPORT_SYMBOL_NS_GPL(ad3542r_model_data, "IIO_AD3552R"); + +const struct ad3552r_model_data ad3551r_model_data =3D { + .model_name =3D "ad3551r", + .chip_id =3D AD3551R_ID, + .num_hw_channels =3D 1, + .ranges_table =3D ad3552r_ch_ranges, + .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), + .requires_output_range =3D false, + .num_spi_data_lanes =3D 4, +}; +EXPORT_SYMBOL_NS_GPL(ad3551r_model_data, "IIO_AD3552R"); + +const struct ad3552r_model_data ad3552r_model_data =3D { + .model_name =3D "ad3552r", + .chip_id =3D AD3552R_ID, + .num_hw_channels =3D 2, + .ranges_table =3D ad3552r_ch_ranges, + .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), + .requires_output_range =3D false, + .num_spi_data_lanes =3D 4, +}; +EXPORT_SYMBOL_NS_GPL(ad3552r_model_data, "IIO_AD3552R"); + static void ad3552r_get_custom_range(struct ad3552r_ch_data *ch_data, s32 *v_min, s32 *v_max) { diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c index e613eee7fc11..58c8661f483b 100644 --- a/drivers/iio/dac/ad3552r-hs.c +++ b/drivers/iio/dac/ad3552r-hs.c @@ -19,6 +19,31 @@ #include "ad3552r.h" #include "ad3552r-hs.h" =20 +/* + * Important notes for register map access: + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * Register address space is divided in 2 regions, primary (config) and + * secondary (DAC). Primary region can only be accessed in simple SPI mode, + * with exception for ad355x models where setting QSPI pin high allows QSPI + * access to both the regions. + * + * Due to the fact that ad3541/2r do not implement QSPI, for proper device + * detection, HDL keeps "QSPI" pin level low at boot (see ad3552r manual, = rev B + * table 7, pin 31, digital input). For this reason, actually the working = mode + * between SPI, DSPI and QSPI must be set via software, configuring the ta= rget + * DAC appropriately, together with the backend api to configure the bus m= ode + * accordingly. + * + * Also, important to note that none of the three modes allow to read in D= DR. + * + * In non-buffering operations, mode is set to simple SPI SDR for all prim= ary + * and secondary region r/w accesses, to avoid to switch the mode each tim= e DAC + * register is accessed (raw accesses, r/w), and to be able to dump regist= ers + * content (possible as non DDR only). + * In buffering mode, driver sets best possible mode, D/QSPI and DDR. + */ + struct ad3552r_hs_state { const struct ad3552r_model_data *model_data; struct gpio_desc *reset_gpio; @@ -27,6 +52,8 @@ struct ad3552r_hs_state { bool single_channel; struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; struct ad3552r_hs_platform_data *data; + /* INTERFACE_CONFIG_D register cache, in DDR we cannot read values. */ + u32 config_d; }; =20 static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st, @@ -56,15 +83,19 @@ static int ad3552r_hs_read_raw(struct iio_dev *indio_de= v, switch (mask) { case IIO_CHAN_INFO_SAMP_FREQ: /* - * Using 4 lanes (QSPI), then using 2 as DDR mode is - * considered always on (considering buffering mode always). + * Using a "num_spi_data_lanes" variable since ad3541/2 have + * only DSPI interface, while ad355x is QSPI. Then using 2 as + * DDR mode is considered always on (considering buffering + * mode always). */ *val =3D DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * - 4 * 2, chan->scan_type.realbits); + st->model_data->num_spi_data_lanes * 2, + chan->scan_type.realbits); =20 return IIO_VAL_INT; =20 case IIO_CHAN_INFO_RAW: + /* For RAW accesses, stay always in simple-spi. */ ret =3D st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), val, 2); @@ -93,6 +124,7 @@ static int ad3552r_hs_write_raw(struct iio_dev *indio_de= v, =20 switch (mask) { case IIO_CHAN_INFO_RAW: + /* For RAW accesses, stay always in simple-spi. */ iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), @@ -104,6 +136,42 @@ static int ad3552r_hs_write_raw(struct iio_dev *indio_= dev, } } =20 +static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st) +{ + int bus_mode; + + if (st->model_data->num_spi_data_lanes =3D=3D 4) + bus_mode =3D IIO_BACKEND_INTERFACE_SERIAL_QSPI; + else + bus_mode =3D IIO_BACKEND_INTERFACE_SERIAL_DSPI; + + return iio_backend_interface_type_set(st->back, bus_mode); +} + +static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st) +{ + int mode_target; + + /* + * Best access for secondary reg area, QSPI where possible, + * else as DSPI. + */ + if (st->model_data->num_spi_data_lanes =3D=3D 4) + mode_target =3D AD3552R_QUAD_SPI; + else + mode_target =3D AD3552R_DUAL_SPI; + + /* + * Better to not use update here, since generally it is already + * set as DDR mode, and it's not possible to read in DDR mode. + */ + return st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_TRANSFER_REGISTER, + FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, + mode_target) | + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); +} + static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev) { struct ad3552r_hs_state *st =3D iio_priv(indio_dev); @@ -132,48 +200,127 @@ static int ad3552r_hs_buffer_postenable(struct iio_d= ev *indio_dev) return -EINVAL; } =20 - ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_STREAM_MODE, - loop_len, 1); + /* + * With ad3541/2r supoport, QSPI pin is held low at reset from HDL, + * streaming start sequence must respect strictly the order below. + */ + + /* Primary region access, set streaming mode (now in SPI + SDR). */ + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_B, + AD3552R_MASK_SINGLE_INST, 0, 1); if (ret) return ret; =20 - /* Inform DAC chip to switch into DDR mode */ + /* + * Set target loop len, 0x2c 0r 0x2a, descending loop, + * and keeping loop len value so it's not cleared hereafter when + * enabling streaming mode (cleared by CS_ up). + */ ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_D, - AD3552R_MASK_SPI_CONFIG_DDR, - AD3552R_MASK_SPI_CONFIG_DDR, 1); + AD3552R_REG_ADDR_TRANSFER_REGISTER, + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); if (ret) - return ret; + goto exit_err_streaming; + + ret =3D st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_STREAM_MODE, + loop_len, 1); + if (ret) + goto exit_err_streaming; + + /* + * Registers dump for debug purposes is only possible until here, + * read in primary region must be SPI SDR (DDR read is never possible, + * D/QSPI SDR read in primary region is also not possible). + */ + + /* Setting DDR now, caching current config_d. */ + ret =3D st->data->bus_reg_read(st->back, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + &st->config_d, 1); + if (ret) + goto exit_err_streaming; + + st->config_d |=3D AD3552R_MASK_SPI_CONFIG_DDR; + ret =3D st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + st->config_d, 1); + + if (ret) + goto exit_err_streaming; =20 - /* Inform DAC IP to go for DDR mode from now on */ ret =3D iio_backend_ddr_enable(st->back); - if (ret) { - dev_err(st->dev, "could not set DDR mode, not streaming"); - goto exit_err; - } + if (ret) + goto exit_err_ddr_mode_target; + + /* + * From here onward mode is DDR, so reading any register is not + * possible anymore, including calling "ad3552r_qspi_update_reg_bits" + * function. + */ + + /* Set target to best high speed mode (D or QSPI). */ + ret =3D ad3552r_hs_set_target_io_mode_hs(st); + if (ret) + goto exit_err_ddr_mode; + + /* Set bus to best high speed mode (D or QSPI). */ + ret =3D ad3552r_hs_set_bus_io_mode_hs(st); + if (ret) + goto exit_err_bus_mode_target; =20 + /* + * Backend setup must be done now only, or related register values + * will be disrupted by previous bus accesses. + */ ret =3D iio_backend_data_transfer_addr(st->back, val); if (ret) - goto exit_err; + goto exit_err_bus_mode_target; =20 ret =3D iio_backend_data_format_set(st->back, 0, &fmt); if (ret) - goto exit_err; + goto exit_err_bus_mode_target; =20 ret =3D iio_backend_data_stream_enable(st->back); if (ret) - goto exit_err; + goto exit_err_bus_mode_target; =20 return 0; =20 -exit_err: - ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_D, - AD3552R_MASK_SPI_CONFIG_DDR, - 0, 1); +exit_err_bus_mode_target: + /* Back to simple SPI, not using update to avoid read. */ + st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER, + FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, + AD3552R_SPI) | + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); + + /* + * Back bus to simple SPI, this must be executed together with above + * target mode unwind, and can be done only after it. + */ + iio_backend_interface_type_set(st->back, + IIO_BACKEND_INTERFACE_SERIAL_SPI); =20 +exit_err_ddr_mode: iio_backend_ddr_disable(st->back); =20 +exit_err_ddr_mode_target: + /* + * Back to SDR. + * In DDR we cannot read, whatever the mode is, so not using update. + */ + st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, 1), + 1); + +exit_err_streaming: + /* Back to single instruction mode, disabling loop. */ + st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, + AD3552R_MASK_SINGLE_INST | + AD3552R_MASK_SHORT_INSTRUCTION, 1); + return ret; } =20 @@ -186,11 +333,23 @@ static int ad3552r_hs_buffer_predisable(struct iio_de= v *indio_dev) if (ret) return ret; =20 - /* Inform DAC to set in SDR mode */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_D, - AD3552R_MASK_SPI_CONFIG_DDR, - 0, 1); + /* + * Set us to simple SPI, even if still in ddr, so to be able + * to write in primary region. + */ + ret =3D iio_backend_interface_type_set(st->back, + IIO_BACKEND_INTERFACE_SERIAL_SPI); + if (ret) + return ret; + + /* + * Back to SDR + * (in DDR we cannot read, whatever the mode is, so not using update). + */ + st->config_d &=3D ~AD3552R_MASK_SPI_CONFIG_DDR; + ret =3D st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + st->config_d, 1); if (ret) return ret; =20 @@ -198,6 +357,24 @@ static int ad3552r_hs_buffer_predisable(struct iio_dev= *indio_dev) if (ret) return ret; =20 + /* + * Back to simple SPI for secondary region too now, + * so to be able to dump/read registers there too if needed. + */ + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_TRANSFER_REGISTER, + AD3552R_MASK_MULTI_IO_MODE, + AD3552R_SPI, 1); + if (ret) + return ret; + + /* Back to single instruction mode, disabling loop. */ + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, + AD3552R_MASK_SINGLE_INST, + AD3552R_MASK_SINGLE_INST, 1); + if (ret) + return ret; + return 0; } =20 @@ -304,10 +481,18 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *= st) if (ret) return ret; =20 + /* HDL starts with DDR enabled, disabling it. */ ret =3D iio_backend_ddr_disable(st->back); if (ret) return ret; =20 + ret =3D st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_INTERFACE_CONFIG_B, + AD3552R_MASK_SINGLE_INST | + AD3552R_MASK_SHORT_INSTRUCTION, 1); + if (ret) + return ret; + ret =3D ad3552r_hs_scratch_pad_test(st); if (ret) return ret; @@ -330,6 +515,8 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *st) "chip id error, expected 0x%x, got 0x%x\n", st->model_data->chip_id, id); =20 + dev_info(st->dev, "chip id %s detected", st->model_data->model_name); + /* Clear reset error flag, see ad3552r manual, rev B table 38. */ ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, AD3552R_MASK_RESET_STATUS, 1); @@ -342,14 +529,6 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *s= t) if (ret) return ret; =20 - ret =3D st->data->bus_reg_write(st->back, - AD3552R_REG_ADDR_TRANSFER_REGISTER, - FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, - AD3552R_QUAD_SPI) | - AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); - if (ret) - return ret; - ret =3D iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL); if (ret) return ret; @@ -505,15 +684,10 @@ static int ad3552r_hs_probe(struct platform_device *p= dev) return devm_iio_device_register(&pdev->dev, indio_dev); } =20 -static const struct ad3552r_model_data ad3552r_model_data =3D { - .model_name =3D "ad3552r", - .chip_id =3D AD3552R_ID, - .num_hw_channels =3D 2, - .ranges_table =3D ad3552r_ch_ranges, - .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), -}; - static const struct of_device_id ad3552r_hs_of_id[] =3D { + { .compatible =3D "adi,ad3541r", .data =3D &ad3541r_model_data }, + { .compatible =3D "adi,ad3542r", .data =3D &ad3542r_model_data }, + { .compatible =3D "adi,ad3551r", .data =3D &ad3551r_model_data }, { .compatible =3D "adi,ad3552r", .data =3D &ad3552r_model_data }, { } }; diff --git a/drivers/iio/dac/ad3552r.c b/drivers/iio/dac/ad3552r.c index e7206af53af6..9d28e06b80c0 100644 --- a/drivers/iio/dac/ad3552r.c +++ b/drivers/iio/dac/ad3552r.c @@ -649,42 +649,6 @@ static int ad3552r_probe(struct spi_device *spi) return devm_iio_device_register(&spi->dev, indio_dev); } =20 -static const struct ad3552r_model_data ad3541r_model_data =3D { - .model_name =3D "ad3541r", - .chip_id =3D AD3541R_ID, - .num_hw_channels =3D 1, - .ranges_table =3D ad3542r_ch_ranges, - .num_ranges =3D ARRAY_SIZE(ad3542r_ch_ranges), - .requires_output_range =3D true, -}; - -static const struct ad3552r_model_data ad3542r_model_data =3D { - .model_name =3D "ad3542r", - .chip_id =3D AD3542R_ID, - .num_hw_channels =3D 2, - .ranges_table =3D ad3542r_ch_ranges, - .num_ranges =3D ARRAY_SIZE(ad3542r_ch_ranges), - .requires_output_range =3D true, -}; - -static const struct ad3552r_model_data ad3551r_model_data =3D { - .model_name =3D "ad3551r", - .chip_id =3D AD3551R_ID, - .num_hw_channels =3D 1, - .ranges_table =3D ad3552r_ch_ranges, - .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), - .requires_output_range =3D false, -}; - -static const struct ad3552r_model_data ad3552r_model_data =3D { - .model_name =3D "ad3552r", - .chip_id =3D AD3552R_ID, - .num_hw_channels =3D 2, - .ranges_table =3D ad3552r_ch_ranges, - .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), - .requires_output_range =3D false, -}; - static const struct spi_device_id ad3552r_id[] =3D { { .name =3D "ad3541r", diff --git a/drivers/iio/dac/ad3552r.h b/drivers/iio/dac/ad3552r.h index 4b5581039ae9..9d450019ece9 100644 --- a/drivers/iio/dac/ad3552r.h +++ b/drivers/iio/dac/ad3552r.h @@ -132,11 +132,18 @@ =20 #define AD3552R_MAX_RANGES 5 #define AD3542R_MAX_RANGES 5 +#define AD3552R_SPI 0 +#define AD3552R_DUAL_SPI 1 #define AD3552R_QUAD_SPI 2 =20 extern const s32 ad3552r_ch_ranges[AD3552R_MAX_RANGES][2]; extern const s32 ad3542r_ch_ranges[AD3542R_MAX_RANGES][2]; =20 +extern const struct ad3552r_model_data ad3541r_model_data; +extern const struct ad3552r_model_data ad3542r_model_data; +extern const struct ad3552r_model_data ad3551r_model_data; +extern const struct ad3552r_model_data ad3552r_model_data; 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[79.17.239.245]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4363602b468sm95514245e9.11.2024.12.16.12.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 12:37:59 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 16 Dec 2024 21:36:28 +0100 Subject: [PATCH 8/8] iio: dac: ad3552r-hs: update function name (non functional) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-8-856ff71fc930@baylibre.com> References: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> In-Reply-To: <20241216-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v1-0-856ff71fc930@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner , Olivier Moysan Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Update ad3552r_qspi_update_reg_bits function name to a more generic name, since used mode can be SIMPLE/DUAL/QUAD SPI. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-hs.c | 58 ++++++++++++++++++++--------------------= ---- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c index 58c8661f483b..931e6036da36 100644 --- a/drivers/iio/dac/ad3552r-hs.c +++ b/drivers/iio/dac/ad3552r-hs.c @@ -56,9 +56,9 @@ struct ad3552r_hs_state { u32 config_d; }; =20 -static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st, - u32 reg, u32 mask, u32 val, - size_t xfer_size) +static int ad3552r_update_reg_bits(struct ad3552r_hs_state *st, + u32 reg, u32 mask, u32 val, + size_t xfer_size) { u32 rval; int ret; @@ -206,9 +206,8 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev = *indio_dev) */ =20 /* Primary region access, set streaming mode (now in SPI + SDR). */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_B, - AD3552R_MASK_SINGLE_INST, 0, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, + AD3552R_MASK_SINGLE_INST, 0, 1); if (ret) return ret; =20 @@ -217,10 +216,9 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev= *indio_dev) * and keeping loop len value so it's not cleared hereafter when * enabling streaming mode (cleared by CS_ up). */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_TRANSFER_REGISTER, - AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, - AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); if (ret) goto exit_err_streaming; =20 @@ -247,7 +245,6 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev = *indio_dev) ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, st->config_d, 1); - if (ret) goto exit_err_streaming; =20 @@ -257,7 +254,7 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev = *indio_dev) =20 /* * From here onward mode is DDR, so reading any register is not - * possible anymore, including calling "ad3552r_qspi_update_reg_bits" + * possible anymore, including calling "ad3552r_update_reg_bits" * function. */ =20 @@ -361,10 +358,9 @@ static int ad3552r_hs_buffer_predisable(struct iio_dev= *indio_dev) * Back to simple SPI for secondary region too now, * so to be able to dump/read registers there too if needed. */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_TRANSFER_REGISTER, - AD3552R_MASK_MULTI_IO_MODE, - AD3552R_SPI, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, + AD3552R_MASK_MULTI_IO_MODE, + AD3552R_SPI, 1); if (ret) return ret; =20 @@ -388,10 +384,10 @@ static inline int ad3552r_hs_set_output_range(struct = ad3552r_hs_state *st, else val =3D FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode); =20 - return ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, - AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), - val, 1); + return ad3552r_update_reg_bits(st, + AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, + AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), + val, 1); } =20 static int ad3552r_hs_reset(struct ad3552r_hs_state *st) @@ -407,10 +403,10 @@ static int ad3552r_hs_reset(struct ad3552r_hs_state *= st) fsleep(10); gpiod_set_value_cansleep(st->reset_gpio, 0); } else { - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_A, - AD3552R_MASK_SOFTWARE_RESET, - AD3552R_MASK_SOFTWARE_RESET, 1); + ret =3D ad3552r_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_A, + AD3552R_MASK_SOFTWARE_RESET, + AD3552R_MASK_SOFTWARE_RESET, 1); if (ret) return ret; } @@ -543,19 +539,17 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *= st) =20 val =3D ret; =20 - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, - AD3552R_MASK_REFERENCE_VOLTAGE_SEL, - val, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, + AD3552R_MASK_REFERENCE_VOLTAGE_SEL, + val, 1); if (ret) return ret; =20 ret =3D ad3552r_get_drive_strength(st->dev, &val); if (!ret) { - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_D, - AD3552R_MASK_SDO_DRIVE_STRENGTH, - val, 1); + ret =3D ad3552r_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SDO_DRIVE_STRENGTH, val, 1); if (ret) return ret; } --=20 2.47.0