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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-fd-dp-audio-fixup-v4-7-f8d1961cf22f@linaro.org> References: <20241216-fd-dp-audio-fixup-v4-0-f8d1961cf22f@linaro.org> In-Reply-To: <20241216-fd-dp-audio-fixup-v4-0-f8d1961cf22f@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=53798; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=rDpX0q4A84dKhxfFPsB2ir+EHrJuMllf2jHjSn2Nt7U=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnX1u5NnxZDVDs0+Z8KwP3QMVQs6ccQ+h5xSLkO t4a7L3rn3GJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ19buQAKCRCLPIo+Aiko 1f4kCACpruk/SekhoFrb8EwiQkUWFqouJPVSXv9XnQ0SMcE+vNiLJIYXNaZyV2rzER+ewMQUo4H sjCm47dbdb2o4FP5F7b2hMr5CJ+a4xcFa97sMjSTLrseVYjckSgQ9zqegQ8lr/JIcQ1eU7JBnsM R77n+zbl/o+hBAlO2MBn6V889f8nZLj74CnbBz3cyF59UCo5EpiYclyaGhOZnDC4TDhL9WWp7R1 vLoQGyCC/f5vPW+W0IjizfK2vW+8/cMIdbo4EEpDuGIaSlpnhUJJ7IicvE48z5bbBoybrpb9Amg xdlkJD9v9Ffmv77lPVSaPS7yRmR8qXZbh9eXLWkg3AqGVpnK X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Having I/O regions inside a msm_dp_catalog_private() results in extra layers of one-line wrappers for accessing the data. Move I/O region base and size to the globally visible struct msm_dp_catalog. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 542 +++++++++++++++-----------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 12 + 2 files changed, 232 insertions(+), 322 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 354ec834f9357c4797fc08a4532e69acc67b4317..399bd11312d33268faee7699461= 96d344546e63d 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -63,154 +63,127 @@ #define DP_DEFAULT_P0_OFFSET 0x1000 #define DP_DEFAULT_P0_SIZE 0x0400 =20 -struct dss_io_region { - size_t len; - void __iomem *base; -}; - -struct dss_io_data { - struct dss_io_region ahb; - struct dss_io_region aux; - struct dss_io_region link; - struct dss_io_region p0; -}; - struct msm_dp_catalog_private { struct device *dev; struct drm_device *drm_dev; - struct dss_io_data io; struct msm_dp_catalog msm_dp_catalog; }; =20 void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - struct dss_io_data *dss =3D &catalog->io; - - msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_= ahb"); - msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_= aux"); - msm_disp_snapshot_add_block(disp_state, dss->link.len, dss->link.base, "d= p_link"); - msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base, "dp_p0= "); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->ahb_len, msm_dp_catalog->ahb_base, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->aux_len, msm_dp_catalog->aux_base, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->link_len, msm_dp_catalog->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->p0_len, msm_dp_catalog->p0_base, "dp_p0"); } =20 -static inline u32 msm_dp_read_aux(struct msm_dp_catalog_private *catalog, = u32 offset) +static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) { - return readl_relaxed(catalog->io.aux.base + offset); + return readl_relaxed(msm_dp_catalog->aux_base + offset); } =20 -static inline void msm_dp_write_aux(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.aux.base + offset); + writel(data, msm_dp_catalog->aux_base + offset); } =20 -static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog_private *cat= alog, u32 offset) +static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) { - return readl_relaxed(catalog->io.ahb.base + offset); + return readl_relaxed(msm_dp_catalog->ahb_base + offset); } =20 -static inline void msm_dp_write_ahb(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.ahb.base + offset); + writel(data, msm_dp_catalog->ahb_base + offset); } =20 -static inline void msm_dp_write_p0(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.p0.base + offset); + writel(data, msm_dp_catalog->p0_base + offset); } =20 -static inline u32 msm_dp_read_p0(struct msm_dp_catalog_private *catalog, +static inline u32 msm_dp_read_p0(struct msm_dp_catalog *msm_dp_catalog, u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io.p0.base + offset); + return readl_relaxed(msm_dp_catalog->p0_base + offset); } =20 -static inline u32 msm_dp_read_link(struct msm_dp_catalog_private *catalog,= u32 offset) +static inline u32 msm_dp_read_link(struct msm_dp_catalog *msm_dp_catalog, = u32 offset) { - return readl_relaxed(catalog->io.link.base + offset); + return readl_relaxed(msm_dp_catalog->link_base + offset); } =20 -static inline void msm_dp_write_link(struct msm_dp_catalog_private *catalo= g, +static inline void msm_dp_write_link(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.link.base + offset); + writel(data, msm_dp_catalog->link_base + offset); } =20 /* aux related catalog functions */ u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_aux(catalog, REG_DP_AUX_DATA); + return msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_DATA); } =20 int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_aux(catalog, REG_DP_AUX_DATA, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_DATA, data); return 0; } =20 int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); return 0; } =20 int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read) { u32 data; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 if (read) { - data =3D msm_dp_read_aux(catalog, REG_DP_AUX_TRANS_CTRL); + data =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL); data &=3D ~DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); } else { - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, 0); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, 0); } return 0; } =20 int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_read_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); + msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); return 0; } =20 @@ -229,47 +202,41 @@ int msm_dp_catalog_aux_clear_hw_interrupts(struct msm= _dp_catalog *msm_dp_catalog void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog) { u32 aux_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - aux_ctrl =3D msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); =20 aux_ctrl |=3D DP_AUX_CTRL_RESET; - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); usleep_range(1000, 1100); /* h/w recommended delay */ =20 aux_ctrl &=3D ~DP_AUX_CTRL_RESET; - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); } =20 void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool= enable) { u32 aux_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - aux_ctrl =3D msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); =20 if (enable) { - msm_dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff); - msm_dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); aux_ctrl |=3D DP_AUX_CTRL_ENABLE; } else { aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; } =20 - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); } =20 int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *m= sm_dp_catalog, unsigned long wait_us) { u32 state; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 /* poll for hpd connected status every 2ms and timeout after wait_us */ - return readl_poll_timeout(catalog->io.aux.base + + return readl_poll_timeout(msm_dp_catalog->aux_base + REG_DP_DP_HPD_INT_STATUS, state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, min(wait_us, 2000), wait_us); @@ -277,15 +244,13 @@ int msm_dp_catalog_aux_wait_for_hpd_connect_state(str= uct msm_dp_catalog *msm_dp_ =20 u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack | + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; @@ -297,20 +262,14 @@ void msm_dp_catalog_ctrl_update_transfer_unit(struct = msm_dp_catalog *msm_dp_cata u32 msm_dp_tu, u32 valid_boundary, u32 valid_boundary2) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(catalog, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(msm_dp_catalog, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary= 2); } =20 void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, state); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, state); } =20 void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 cfg) @@ -320,13 +279,11 @@ void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_ca= talog *msm_dp_catalog, u32 =20 drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", cfg); =20 - msm_dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg); + msm_dp_write_link(msm_dp_catalog, REG_DP_CONFIGURATION_CTRL, cfg); } =20 void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ u32 ln_mapping; =20 @@ -335,7 +292,7 @@ void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_cat= alog *msm_dp_catalog) ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; =20 - msm_dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); } =20 @@ -343,17 +300,15 @@ void msm_dp_catalog_ctrl_psr_mainlink_enable(struct m= sm_dp_catalog *msm_dp_catal bool enable) { u32 val; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - val =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 if (enable) val |=3D DP_MAINLINK_CTRL_ENABLE; else val &=3D ~DP_MAINLINK_CTRL_ENABLE; =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); } =20 void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, @@ -369,25 +324,25 @@ void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_= catalog *msm_dp_catalog, * To make sure link reg writes happens before other operation, * msm_dp_write_link() function uses writel() */ - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } else { - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } } =20 @@ -399,7 +354,7 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_cata= log *msm_dp_catalog, struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - misc_val =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + misc_val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -409,16 +364,14 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_ca= talog *msm_dp_catalog, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(catalog->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc_val); } =20 void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog) { u32 mainlink_ctrl, hw_revision; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); if (hw_revision >=3D DP_HW_VERSION_1_2) @@ -426,7 +379,7 @@ void msm_dp_catalog_setup_peripheral_flush(struct msm_d= p_catalog *msm_dp_catalog else mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, @@ -484,9 +437,9 @@ void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catal= og *msm_dp_catalog, nvid *=3D 3; =20 drm_dbg_dp(catalog->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); - msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); } =20 int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, @@ -504,7 +457,7 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct ms= m_dp_catalog *msm_dp_cata bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; =20 /* Poll for mainlink ready status */ - ret =3D readx_poll_timeout(readl, catalog->io.link.base + + ret =3D readx_poll_timeout(readl, msm_dp_catalog->link_base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -525,10 +478,7 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct m= sm_dp_catalog *msm_dp_cata */ u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog) { - const struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_cata= log, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_ahb(catalog, REG_DP_HW_VERSION); + return msm_dp_read_ahb(msm_dp_catalog, REG_DP_HW_VERSION); } =20 /** @@ -546,28 +496,24 @@ u32 msm_dp_catalog_hw_revision(const struct msm_dp_ca= talog *msm_dp_catalog) void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) { u32 sw_reset; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - sw_reset =3D msm_dp_read_ahb(catalog, REG_DP_SW_RESET); + sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); =20 sw_reset |=3D DP_SW_RESET; - msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); usleep_range(1000, 1100); /* h/w recommended delay */ =20 sw_reset &=3D ~DP_SW_RESET; - msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); } =20 bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log) { u32 data; int ret; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 /* Poll for mainlink ready status */ - ret =3D readl_poll_timeout(catalog->io.link.base + + ret =3D readl_poll_timeout(msm_dp_catalog->link_base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -582,17 +528,14 @@ bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp= _catalog *msm_dp_catalog) void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - if (enable) { - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, DP_INTERRUPT_STATUS1_MASK); - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); } else { - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00); - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); } } =20 @@ -602,73 +545,63 @@ void msm_dp_catalog_hpd_config_intr(struct msm_dp_cat= alog *msm_dp_catalog, struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - u32 config =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + u32 config =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); =20 config =3D (en ? config | intr_mask : config & ~intr_mask); =20 drm_dbg_dp(catalog->drm_dev, "intr_mask=3D%#x config=3D%#x\n", intr_mask, config); - msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, config & DP_DP_HPD_INT_MASK); } =20 void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 reftimer =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); =20 /* Configure REFTIMER and enable it */ reftimer |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); =20 /* Enable HPD */ - msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); } =20 void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 reftimer =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); =20 reftimer &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); =20 - msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); } =20 -static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog_private *catal= og) +static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog *msm_dp_catalo= g) { /* trigger sdp */ - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); } =20 void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 config; =20 /* enable PSR1 function */ - config =3D msm_dp_read_link(catalog, REG_PSR_CONFIG); + config =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); config |=3D PSR1_SUPPORTED; - msm_dp_write_link(catalog, REG_PSR_CONFIG, config); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, config); =20 - msm_dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); - msm_dp_catalog_enable_sdp(catalog); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); + msm_dp_catalog_enable_sdp(msm_dp_catalog); } =20 void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 cmd; =20 - cmd =3D msm_dp_read_link(catalog, REG_PSR_CMD); + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); =20 @@ -677,8 +610,8 @@ void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog = *msm_dp_catalog, bool ent else cmd |=3D PSR_EXIT; =20 - msm_dp_catalog_enable_sdp(catalog); - msm_dp_write_link(catalog, REG_PSR_CMD, cmd); + msm_dp_catalog_enable_sdp(msm_dp_catalog); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); } =20 u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) @@ -687,7 +620,7 @@ u32 msm_dp_catalog_link_is_connected(struct msm_dp_cata= log *msm_dp_catalog) struct msm_dp_catalog_private, msm_dp_catalog); u32 status; =20 - status =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); + status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; @@ -697,14 +630,12 @@ u32 msm_dp_catalog_link_is_connected(struct msm_dp_ca= talog *msm_dp_catalog) =20 u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); int isr, mask; =20 - isr =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, + isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); =20 /* * We only want to return interrupts that are unmasked to the caller. @@ -718,29 +649,25 @@ u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_= catalog *msm_dp_catalog) =20 u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS4); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); intr_ack =3D (intr & DP_INTERRUPT_STATUS4) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); =20 return intr; } =20 int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS2); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); intr &=3D ~DP_INTERRUPT_STATUS2_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS2) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, intr_ack | DP_INTERRUPT_STATUS2_MASK); =20 return intr; @@ -748,13 +675,10 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_c= atalog *msm_dp_catalog) =20 void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); usleep_range(1000, 1100); /* h/w recommended delay */ - msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, 0x0); } =20 void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, @@ -765,66 +689,66 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_= dp_catalog *msm_dp_catalog, u32 value =3D 0x0; =20 /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); =20 drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &=3D ~(1 << 16); - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E); break; case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); =20 value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); break; case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: @@ -836,26 +760,21 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_= dp_catalog *msm_dp_catalog, =20 u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_link(catalog, REG_DP_MAINLINK_READY); + return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY); } =20 /* panel related catalog functions */ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, u32 sync_start, u32 width_blanking, u32 msm_dp_active) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 reg; =20 - msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); - msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_st= art); + msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, widt= h_blanking); + msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); + reg =3D msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG); =20 if (msm_dp_catalog->wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; @@ -865,42 +784,36 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_cat= alog *msm_dp_catalog, u32 t =20 DRM_DEBUG_DP("wide_bus_en=3D%d reg=3D%#x\n", msm_dp_catalog->wide_bus_en,= reg); =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg); return 0; } =20 static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_d= p_catalog, struct dp_sdp *vsc_sdp) { - struct msm_dp_catalog_private *catalog; u32 header[2]; u32 val; int i; =20 - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); } } =20 static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_= catalog) { - struct msm_dp_catalog_private *catalog; u32 hw_revision; =20 - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=3D DP_HW_VERSION_1_0= ) { - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00); } } =20 @@ -911,15 +824,15 @@ void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_d= p_catalog *msm_dp_catalog, =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); =20 - cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); =20 cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); =20 msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); =20 @@ -929,7 +842,7 @@ void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_= catalog *msm_dp_catalog, drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); =20 msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } @@ -941,15 +854,15 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_= dp_catalog *msm_dp_catalog) =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); =20 - cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); =20 cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -957,7 +870,7 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp= _catalog *msm_dp_catalog) drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); =20 msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } @@ -998,53 +911,47 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_ca= talog *msm_dp_catalog, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_perio= d * hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync= _width * hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_s= tart); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_= end); + msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_VIDEO_CONFIG, DP_TPG_VIDEO_CONFIG_BPP_8BIT | DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__); } =20 void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); } =20 static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) @@ -1061,15 +968,15 @@ static void __iomem *msm_dp_ioremap(struct platform_= device *pdev, int idx, size_ =20 static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog) { + struct msm_dp_catalog *msm_dp_catalog =3D &catalog->msm_dp_catalog; struct platform_device *pdev =3D to_platform_device(catalog->dev); - struct dss_io_data *dss =3D &catalog->io; =20 - dss->ahb.base =3D msm_dp_ioremap(pdev, 0, &dss->ahb.len); - if (IS_ERR(dss->ahb.base)) - return PTR_ERR(dss->ahb.base); + msm_dp_catalog->ahb_base =3D msm_dp_ioremap(pdev, 0, &msm_dp_catalog->ahb= _len); + if (IS_ERR(msm_dp_catalog->ahb_base)) + return PTR_ERR(msm_dp_catalog->ahb_base); =20 - dss->aux.base =3D msm_dp_ioremap(pdev, 1, &dss->aux.len); - if (IS_ERR(dss->aux.base)) { + msm_dp_catalog->aux_base =3D msm_dp_ioremap(pdev, 1, &msm_dp_catalog->aux= _len); + if (IS_ERR(msm_dp_catalog->aux_base)) { /* * The initial binding had a single reg, but in order to * support variation in the sub-region sizes this was split. @@ -1077,34 +984,35 @@ static int msm_dp_catalog_get_io(struct msm_dp_catal= og_private *catalog) * reg is specified, so fill in the sub-region offsets and * lengths based on this single region. */ - if (PTR_ERR(dss->aux.base) =3D=3D -EINVAL) { - if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + if (PTR_ERR(msm_dp_catalog->aux_base) =3D=3D -EINVAL) { + if (msm_dp_catalog->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE= ) { DRM_ERROR("legacy memory region not large enough\n"); return -EINVAL; } =20 - dss->ahb.len =3D DP_DEFAULT_AHB_SIZE; - dss->aux.base =3D dss->ahb.base + DP_DEFAULT_AUX_OFFSET; - dss->aux.len =3D DP_DEFAULT_AUX_SIZE; - dss->link.base =3D dss->ahb.base + DP_DEFAULT_LINK_OFFSET; - dss->link.len =3D DP_DEFAULT_LINK_SIZE; - dss->p0.base =3D dss->ahb.base + DP_DEFAULT_P0_OFFSET; - dss->p0.len =3D DP_DEFAULT_P0_SIZE; + msm_dp_catalog->ahb_len =3D DP_DEFAULT_AHB_SIZE; + msm_dp_catalog->aux_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_AUX_= OFFSET; + msm_dp_catalog->aux_len =3D DP_DEFAULT_AUX_SIZE; + msm_dp_catalog->link_base =3D msm_dp_catalog->ahb_base + + DP_DEFAULT_LINK_OFFSET; + msm_dp_catalog->link_len =3D DP_DEFAULT_LINK_SIZE; + msm_dp_catalog->p0_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_P0_OF= FSET; + msm_dp_catalog->p0_len =3D DP_DEFAULT_P0_SIZE; } else { - DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); - return PTR_ERR(dss->aux.base); + DRM_ERROR("unable to remap aux region: %pe\n", msm_dp_catalog->aux_base= ); + return PTR_ERR(msm_dp_catalog->aux_base); } } else { - dss->link.base =3D msm_dp_ioremap(pdev, 2, &dss->link.len); - if (IS_ERR(dss->link.base)) { - DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); - return PTR_ERR(dss->link.base); + msm_dp_catalog->link_base =3D msm_dp_ioremap(pdev, 2, &msm_dp_catalog->l= ink_len); + if (IS_ERR(msm_dp_catalog->link_base)) { + DRM_ERROR("unable to remap link region: %pe\n", msm_dp_catalog->link_ba= se); + return PTR_ERR(msm_dp_catalog->link_base); } =20 - dss->p0.base =3D msm_dp_ioremap(pdev, 3, &dss->p0.len); - if (IS_ERR(dss->p0.base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); - return PTR_ERR(dss->p0.base); + msm_dp_catalog->p0_base =3D msm_dp_ioremap(pdev, 3, &msm_dp_catalog->p0_= len); + if (IS_ERR(msm_dp_catalog->p0_base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", msm_dp_catalog->p0_base); + return PTR_ERR(msm_dp_catalog->p0_base); } } =20 @@ -1132,72 +1040,62 @@ struct msm_dp_catalog *msm_dp_catalog_get(struct de= vice *dev) void msm_dp_catalog_write_audio_stream(struct msm_dp_catalog *msm_dp_catal= og, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); } =20 void msm_dp_catalog_write_audio_timestamp(struct msm_dp_catalog *msm_dp_ca= talog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); } =20 void msm_dp_catalog_write_audio_infoframe(struct msm_dp_catalog *msm_dp_ca= talog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); } =20 void msm_dp_catalog_write_audio_copy_mgmt(struct msm_dp_catalog *msm_dp_ca= talog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[= 0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[= 1]); } =20 void msm_dp_catalog_write_audio_isrc(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); struct dp_sdp_header tmp =3D *sdp_hdr; u32 header[2]; u32 reg; =20 /* XXX: is it necessary to preserve this field? */ - reg =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_ISRC_1); + reg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_1); tmp.HB3 =3D FIELD_GET(HEADER_3_MASK, reg); =20 msm_dp_utils_pack_sdp_header(&tmp, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); } =20 void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog= , u32 select) @@ -1216,7 +1114,7 @@ void msm_dp_catalog_audio_config_acr(struct msm_dp_ca= talog *msm_dp_catalog, u32 drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n", select, acr_ctrl); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } =20 void msm_dp_catalog_audio_enable(struct msm_dp_catalog *msm_dp_catalog, bo= ol enable) @@ -1230,7 +1128,7 @@ void msm_dp_catalog_audio_enable(struct msm_dp_catalo= g *msm_dp_catalog, bool ena catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - audio_ctrl =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_CFG); + audio_ctrl =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG); =20 if (enable) audio_ctrl |=3D BIT(0); @@ -1239,7 +1137,7 @@ void msm_dp_catalog_audio_enable(struct msm_dp_catalo= g *msm_dp_catalog, bool ena =20 drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); /* make sure audio engine is disabled */ wmb(); } @@ -1256,7 +1154,7 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - sdp_cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); + sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); /* AUDIO_TIMESTAMP_SDP_EN */ sdp_cfg |=3D BIT(1); /* AUDIO_STREAM_SDP_EN */ @@ -1270,9 +1168,9 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) =20 drm_dbg_dp(catalog->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); =20 - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, sdp_cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); =20 - sdp_cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); + sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); /* IFRM_REGSRC -> Do not use reg values */ sdp_cfg2 &=3D ~BIT(0); /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ @@ -1280,7 +1178,7 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) =20 drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); =20 - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); } =20 void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *msm_dp_catalog,= u32 safe_to_exit_level) @@ -1294,7 +1192,7 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_cat= alog *msm_dp_catalog, u32 s catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - mainlink_levels =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); + mainlink_levels =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_LEVE= LS); mainlink_levels &=3D 0xFE0; mainlink_levels |=3D safe_to_exit_level; =20 @@ -1302,5 +1200,5 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_cat= alog *msm_dp_catalog, u32 s "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", mainlink_levels, safe_to_exit_level); =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 08bb42e91b779633875dbeb4130bc55a6571cfb1..9aadaf1627a5813ab2d87e6e02d= c0a967affdd79 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -33,6 +33,18 @@ =20 struct msm_dp_catalog { bool wide_bus_en; + + void __iomem *ahb_base; + size_t ahb_len; + + void __iomem *aux_base; + size_t aux_len; + + void __iomem *link_base; + size_t link_len; + + void __iomem *p0_base; + size_t p0_len; }; =20 /* Debug module */ --=20 2.39.5