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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241216-fd-dp-audio-fixup-v4-11-f8d1961cf22f@linaro.org> References: <20241216-fd-dp-audio-fixup-v4-0-f8d1961cf22f@linaro.org> In-Reply-To: <20241216-fd-dp-audio-fixup-v4-0-f8d1961cf22f@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=22465; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=x99tycZ9mS36didAo3PXzDXTL5cVyZnK2r4ktmML9j8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnX1u6T7DfOHkZCXD+GvEIYPbkV9MF9uJbRqPew W/6pMsIsbiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ19bugAKCRCLPIo+Aiko 1X/KB/9u95nyLxvlqsZ1Mu9JHBZu020CXq73qnD81fWI9H1iCNYrm2FDqjIW/1i1uOlL3nwLUni Lx8bmF5Lm5M0My/wG6XmVYAvXqjkPTd0WXRb5BQ24m5t/CAtkfa5vR59CzoR8GJnl+DGpzpJpFr ULGs1s78M9cYYFtqPw+qPYjzSRpZrwUxO+DOo3BqKhReCwKxYhaH7NE+/y2pOVyV1t5F3LIO9wI QPF1js4Nvrk+z99rioUyChA7aR9BK+Cw6KTqMyvN9K9wGubvec0WGCRbMfBbrtsuGbN5/wHo+Wc LhGJk0yrz2wQi0IeJE9oCDYhwOREQhl9Ky5NlT+nKvyVbieB X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move panel-related functions to dp_panel.c, following up the cleanup done by the rest of the submodules. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 193 --------------------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 11 -- drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 +- drivers/gpu/drm/msm/dp/dp_panel.c | 210 ++++++++++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/dp/dp_panel.h | 5 + 5 files changed, 207 insertions(+), 218 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 8101d34a62639149686383d3b6b3acab0441c89a..b323fb3341280963012b605483d= 4f3c7190fd7d5 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -21,8 +21,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 =20 -#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_XFER_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -223,197 +221,6 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_c= atalog *msm_dp_catalog) return intr; } =20 -/* panel related catalog functions */ -int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, - u32 sync_start, u32 width_blanking, u32 msm_dp_active) -{ - u32 reg; - - msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_st= art); - msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, widt= h_blanking); - msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); - - reg =3D msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG); - - if (msm_dp_catalog->wide_bus_en) - reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; - else - reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; - - - DRM_DEBUG_DP("wide_bus_en=3D%d reg=3D%#x\n", msm_dp_catalog->wide_bus_en,= reg); - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg); - return 0; -} - -static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_d= p_catalog, struct dp_sdp *vsc_sdp) -{ - u32 header[2]; - u32 val; - int i; - - msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); - - for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { - val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | - (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); - } -} - -static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_= catalog) -{ - u32 hw_revision; - - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=3D DP_HW_VERSION_1_0= ) { - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00); - } -} - -void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp) -{ - struct msm_dp_catalog_private *catalog; - u32 cfg, cfg2, misc; - - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); - - cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); - - msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); - - /* indicates presence of VSC (BIT(6) of MISC1) */ - misc |=3D DP_MISC1_VSC_SDP; - - drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D1\n"); - - pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); - - msm_dp_catalog_panel_update_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog) -{ - struct msm_dp_catalog_private *catalog; - u32 cfg, cfg2, misc; - - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); - - cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); - - /* switch back to MSA */ - misc &=3D ~DP_MISC1_VSC_SDP; - - drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D0\n"); - - pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); - - msm_dp_catalog_panel_update_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, - struct drm_display_mode *drm_mode) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 hsync_period, vsync_period; - u32 display_v_start, display_v_end; - u32 hsync_start_x, hsync_end_x; - u32 v_sync_width; - u32 hsync_ctl; - u32 display_hctl; - - /* TPG config parameters*/ - hsync_period =3D drm_mode->htotal; - vsync_period =3D drm_mode->vtotal; - - display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * - hsync_period); - display_v_end =3D ((vsync_period - (drm_mode->vsync_start - - drm_mode->vdisplay)) - * hsync_period) - 1; - - display_v_start +=3D drm_mode->htotal - drm_mode->hsync_start; - display_v_end -=3D (drm_mode->hsync_start - drm_mode->hdisplay); - - hsync_start_x =3D drm_mode->htotal - drm_mode->hsync_start; - hsync_end_x =3D hsync_period - (drm_mode->hsync_start - - drm_mode->hdisplay) - 1; - - v_sync_width =3D drm_mode->vsync_end - drm_mode->vsync_start; - - hsync_ctl =3D (hsync_period << 16) | - (drm_mode->hsync_end - drm_mode->hsync_start); - display_hctl =3D (hsync_end_x << 16) | hsync_start_x; - - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_perio= d * - hsync_period); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync= _width * - hsync_period); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_s= tart); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_= end); - msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); - drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__); -} - -void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g) -{ - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); -} - -void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log) -{ - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index d2c9f8c693f6cac4b33094e124c7f80f6d89b580..f652745ae3fd5fe322b7a59b784= 46ec5b71c044d 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -128,17 +128,6 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_ca= talog *msm_dp_catalog); void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); =20 -/* DP Panel APIs */ -int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, - u32 sync_start, u32 width_blanking, u32 msm_dp_active); -void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp); -void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog); -void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, - struct drm_display_mode *drm_mode); -void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g); - -void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log); - struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 /* DP Audio APIs */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index e6b103798f8d94b54afebdb9c65ccb6ae965a2c8..519bf64cc9a25c80eb92bfe5b40= d1d921e120494 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2369,7 +2369,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, bool force_link_train pixel_rate_orig, ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); =20 - msm_dp_catalog_panel_clear_dsc_dto(ctrl->catalog); + msm_dp_panel_clear_dsc_dto(ctrl->panel); =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 @@ -2395,7 +2395,7 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *= msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); + msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); @@ -2450,7 +2450,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); + msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 92415bf8aa16655a6cf4f7d6f8a5896275edf001..aee45f9afe461a73ff51ed0ded1= a1815a5b0330e 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -4,6 +4,7 @@ */ =20 #include "dp_panel.h" +#include "dp_reg.h" #include "dp_utils.h" =20 #include @@ -11,6 +12,8 @@ #include #include =20 +#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) + #define DP_MAX_NUM_DP_LANES 4 #define DP_LINK_RATE_HBR2 540000 /* kbytes */ =20 @@ -242,9 +245,87 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pa= nel *msm_dp_panel) } } =20 +static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, + struct drm_display_mode *drm_mode) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *catalog =3D panel->catalog; + u32 hsync_period, vsync_period; + u32 display_v_start, display_v_end; + u32 hsync_start_x, hsync_end_x; + u32 v_sync_width; + u32 hsync_ctl; + u32 display_hctl; + + /* TPG config parameters*/ + hsync_period =3D drm_mode->htotal; + vsync_period =3D drm_mode->vtotal; + + display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * + hsync_period); + display_v_end =3D ((vsync_period - (drm_mode->vsync_start - + drm_mode->vdisplay)) + * hsync_period) - 1; + + display_v_start +=3D drm_mode->htotal - drm_mode->hsync_start; + display_v_end -=3D (drm_mode->hsync_start - drm_mode->hdisplay); + + hsync_start_x =3D drm_mode->htotal - drm_mode->hsync_start; + hsync_end_x =3D hsync_period - (drm_mode->hsync_start - + drm_mode->hdisplay) - 1; + + v_sync_width =3D drm_mode->vsync_end - drm_mode->vsync_start; + + hsync_ctl =3D (hsync_period << 16) | + (drm_mode->hsync_end - drm_mode->hsync_start); + display_hctl =3D (hsync_end_x << 16) | hsync_start_x; + + + msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + hsync_period); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + hsync_period); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); + drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); +} + +static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *catalog =3D panel->catalog; + + msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); +} + void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) { - struct msm_dp_catalog *catalog; struct msm_dp_panel_private *panel; =20 if (!msm_dp_panel) { @@ -253,7 +334,6 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_d= p_panel, bool enable) } =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; =20 if (!panel->panel_on) { drm_dbg_dp(panel->drm_dev, @@ -262,18 +342,114 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel *ms= m_dp_panel, bool enable) } =20 if (!enable) { - msm_dp_catalog_panel_tpg_disable(catalog); + msm_dp_panel_tpg_disable(msm_dp_panel); return; } =20 - drm_dbg_dp(panel->drm_dev, "calling catalog tpg_enable\n"); - msm_dp_catalog_panel_tpg_enable(catalog, &panel->msm_dp_panel.msm_dp_mode= .drm_mode); + drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n"); + msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.dr= m_mode); +} + +void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *catalog =3D panel->catalog; + + msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); +} + +static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) +{ + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 header[2]; + u32 val; + int i; + + msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); + + for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { + val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | + (vsc_sdp->db[i + 3] << 24)); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); + } +} + +static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) +{ + u32 hw_revision; + + hw_revision =3D msm_dp_catalog_hw_revision(panel->catalog); + if (hw_revision >=3D DP_HW_VERSION_1_0 && + hw_revision < DP_HW_VERSION_1_2) { + msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, 0x0); + } +} + +void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 cfg, cfg2, misc; + + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + + cfg |=3D GEN0_SDP_EN; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 |=3D GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + + msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); + + /* indicates presence of VSC (BIT(6) of MISC1) */ + misc |=3D DP_MISC1_VSC_SDP; + + drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); + + pr_debug("misc settings =3D 0x%x\n", misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + + msm_dp_panel_update_sdp(panel); +} + +void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 cfg, cfg2, misc; + + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + + cfg &=3D ~GEN0_SDP_EN; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + + /* switch back to MSA */ + misc &=3D ~DP_MISC1_VSC_SDP; + + drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); + + pr_debug("misc settings =3D 0x%x\n", misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + + msm_dp_panel_update_sdp(panel); } =20 static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_= panel) { - struct msm_dp_catalog *catalog; - struct msm_dp_panel_private *panel; struct msm_dp_display_mode *msm_dp_mode; struct drm_dp_vsc_sdp vsc_sdp_data; struct dp_sdp vsc_sdp; @@ -284,8 +460,6 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) return -EINVAL; } =20 - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; msm_dp_mode =3D &msm_dp_panel->msm_dp_mode; =20 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); @@ -312,7 +486,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) return len; } =20 - msm_dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp); + msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp); =20 return 0; } @@ -327,6 +501,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel) u32 sync_start; u32 msm_dp_active; u32 total; + u32 reg; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); catalog =3D panel->catalog; @@ -372,7 +547,20 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_d= p_panel) =20 msm_dp_active =3D data; =20 - msm_dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blankin= g, msm_dp_active); + msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); + msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); + msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + + reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); + if (catalog->wide_bus_en) + reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; + else + reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; + + drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", catalog->wide_= bus_en, reg); + + msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 4906f4f09f2451cfed3c1007f38b4db7dfdb1d90..8dde55b3a5ab64c0c12d69cb2dd= 5b5c733c83432 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -57,6 +57,11 @@ int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_p= anel, void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e); =20 +void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); + +void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp); +void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); + /** * is_link_rate_valid() - validates the link rate * @lane_rate: link rate requested by the sink --=20 2.39.5