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Sun, 15 Dec 2024 04:29:00 -0800 (PST) Received: from localhost.localdomain ([83.168.79.145]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d652ad187dsm2055327a12.28.2024.12.15.04.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2024 04:28:59 -0800 (PST) From: Karol Przybylski To: alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, simona@ffwll.ch, srinivasan.shanmugam@amd.com, Hawking.Zhang@amd.com, Jack.Xiao@amd.com, lijo.lazar@amd.com, Jesse.zhang@amd.com, tao.zhou1@amd.com Cc: Karol Przybylski , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amdgpu: Fix potential integer overflow in scheduler mask calculations Date: Sun, 15 Dec 2024 13:28:57 +0100 Message-Id: <20241215122857.927606-1-karprzy7@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The use of 1 << i in scheduler mask calculations can result in an unintentional integer overflow due to the expression being evaluated as a 32-bit signed integer. This patch replaces 1 << i with 1ULL << i to ensure the operation is performed as a 64-bit unsigned integer, preventing overflow Discovered in coverity scan, CID 1636393, 1636175, 1636007, 1635853 Fixes: c5c63d9cb5d3b drm/amdgpu: add amdgpu_gfx_sched_mask and amdgpu_compu= te_sched_mask debugfs Signed-off-by: Karol Przybylski --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gfx.c index 69a6b6dba0a5..8fb6c5f6a060 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2050,7 +2050,7 @@ static int amdgpu_debugfs_gfx_sched_mask_set(void *da= ta, u64 val) if (!adev) return -ENODEV; =20 - mask =3D (1 << adev->gfx.num_gfx_rings) - 1; + mask =3D (1ULL << adev->gfx.num_gfx_rings) - 1; if ((val & mask) =3D=3D 0) return -EINVAL; =20 @@ -2078,7 +2078,7 @@ static int amdgpu_debugfs_gfx_sched_mask_get(void *da= ta, u64 *val) for (i =3D 0; i < adev->gfx.num_gfx_rings; ++i) { ring =3D &adev->gfx.gfx_ring[i]; if (ring->sched.ready) - mask |=3D 1 << i; + mask |=3D 1ULL << i; } =20 *val =3D mask; @@ -2120,7 +2120,7 @@ static int amdgpu_debugfs_compute_sched_mask_set(void= *data, u64 val) if (!adev) return -ENODEV; =20 - mask =3D (1 << adev->gfx.num_compute_rings) - 1; + mask =3D (1ULL << adev->gfx.num_compute_rings) - 1; if ((val & mask) =3D=3D 0) return -EINVAL; =20 @@ -2149,7 +2149,7 @@ static int amdgpu_debugfs_compute_sched_mask_get(void= *data, u64 *val) for (i =3D 0; i < adev->gfx.num_compute_rings; ++i) { ring =3D &adev->gfx.compute_ring[i]; if (ring->sched.ready) - mask |=3D 1 << i; + mask |=3D 1ULL << i; } =20 *val =3D mask; --=20 2.34.1