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Sun, 15 Dec 2024 04:40:23 -0800 (PST) From: Dmitry Baryshkov Date: Sun, 15 Dec 2024 14:40:16 +0200 Subject: [PATCH v8 1/3] drm/msm/dpu: add support for virtual planes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241215-dpu-virtual-wide-v8-1-65221f213ce1@linaro.org> References: <20241215-dpu-virtual-wide-v8-0-65221f213ce1@linaro.org> In-Reply-To: <20241215-dpu-virtual-wide-v8-0-65221f213ce1@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=22519; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ezbqaOrF2y7Ca75CspR9J44P8kcSu10rCHb5ToxdUl0=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ3rcOWNDO70Al48zeY6ERp46xsZU0+Yc8KrkarWo9/o1J 5NWHI/vZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBEWNTZ/8qJ7VTWkT1lO2Nb /fEX3395/Vg3OUri+faZR//2rT0o/0UgxOmI3Lec/ZuOOtgFHPZxVmKXn33Fpuawz4rPSXebtju 5nRLv1eSSrP3GtO2uafGvZiOfw15GfRvS7sjddC71ssw//exl9y+O1PbdGpaLM6wPtN53FWsxiu q5lX1GtXBthS6jkdMJNbETC9J7vwrsSP79wlRng+Ksyn7ZmN3sp77M2lvI25XL1nmxPI/lTqLE4 +bDmQtOiMT937j9dmBHZ+2b2kz+H0e2P+xjtK6Oc17m+M6gYPWDvQdY7ZjZa58diW2uZqlxm731 pQdr3+bFP7sqbD6a+j+RdTc2Epihyym776tqoDfT7ve2AA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Only several SSPP blocks support such features as YUV output or scaling, thus different DRM planes have different features. Properly utilizing all planes requires the attention of the compositor, who should prefer simpler planes to YUV-supporting ones. Otherwise it is very easy to end up in a situation when all featureful planes are already allocated for simple windows, leaving no spare plane for YUV playback. To solve this problem make all planes virtual. Each plane is registered as if it supports all possible features, but then at the runtime during the atomic_check phase the driver selects backing SSPP block for each plane. As the planes are attached to the CRTC and not the encoder, the SSPP blocks are also allocated per CRTC ID (all other resources are currently allocated per encoder ID). This also matches the hardware requirement, where both rectangles of a single SSPP can only be used with the LM pair. Note, this does not provide support for using two different SSPP blocks for a single plane or using two rectangles of an SSPP to drive two planes. Each plane still gets its own SSPP and can utilize either a solo rectangle or both multirect rectangles depending on the resolution. Note #2: By default support for virtual planes is turned off and the driver still uses old code path with preallocated SSPP block for each plane. To enable virtual planes, pass 'msm.dpu_use_virtual_planes=3D1' kernel parameter. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 50 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 264 ++++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 13 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 82 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 14 ++ 7 files changed, 399 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 9f6ffd344693ecfb633095772a31ada5613345dc..fcbcac00c8500cfff8546279524= 638e1f5ae3f18 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1182,6 +1182,49 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_s= tate *cstate) return false; } =20 +static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc= _state *crtc_state) +{ + int total_planes =3D crtc->dev->mode_config.num_total_plane; + struct drm_atomic_state *state =3D crtc_state->state; + struct dpu_global_state *global_state; + struct drm_plane_state **states; + struct drm_plane *plane; + int ret; + + global_state =3D dpu_kms_get_global_state(crtc_state->state); + if (IS_ERR(global_state)) + return PTR_ERR(global_state); + + dpu_rm_release_all_sspp(global_state, crtc); + + if (!crtc_state->enable) + return 0; + + states =3D kcalloc(total_planes, sizeof(*states), GFP_KERNEL); + if (!states) + return -ENOMEM; + + drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { + struct drm_plane_state *plane_state =3D + drm_atomic_get_plane_state(state, plane); + + if (IS_ERR(plane_state)) { + ret =3D PTR_ERR(plane_state); + goto done; + } + + states[plane_state->normalized_zpos] =3D plane_state; + } + + ret =3D dpu_assign_plane_resources(global_state, state, crtc, states, tot= al_planes); + +done: + kfree(states); + return ret; + + return 0; +} + static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -1197,6 +1240,13 @@ static int dpu_crtc_atomic_check(struct drm_crtc *cr= tc, =20 bool needs_dirtyfb =3D dpu_crtc_needs_dirtyfb(crtc_state); =20 + if (dpu_use_virtual_planes && + (crtc_state->planes_changed || crtc_state->zpos_changed)) { + rc =3D dpu_crtc_reassign_planes(crtc, crtc_state); + if (rc < 0) + return rc; + } + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state= )) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index ca4847b2b73876c59dedff1e3ec4188ea70860a7..afb2ee309772b1aa7b93eddde96= 0028bdb612a1e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -51,6 +51,9 @@ #define DPU_DEBUGFS_DIR "msm_dpu" #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" =20 +bool dpu_use_virtual_planes; +module_param(dpu_use_virtual_planes, bool, 0); + static int dpu_kms_hw_init(struct msm_kms *kms); static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); =20 @@ -829,8 +832,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_k= ms) type, catalog->sspp[i].features, catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); =20 - plane =3D dpu_plane_init(dev, catalog->sspp[i].id, type, - (1UL << max_crtc_count) - 1); + if (dpu_use_virtual_planes) + plane =3D dpu_plane_init_virtual(dev, type, (1UL << max_crtc_count) - 1= ); + else + plane =3D dpu_plane_init(dev, catalog->sspp[i].id, type, + (1UL << max_crtc_count) - 1); if (IS_ERR(plane)) { DPU_ERROR("dpu_plane_init failed\n"); ret =3D PTR_ERR(plane); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index 88d64d43ea1a8226b414f04bf76551f7dda94ef6..547cdb2c0c788a031685e397e2c= 8ef73ca6290d7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -54,6 +54,8 @@ #define ktime_compare_safe(A, B) \ ktime_compare(ktime_sub((A), (B)), ktime_set(0, 0)) =20 +extern bool dpu_use_virtual_planes; + struct dpu_kms { struct msm_kms base; struct drm_device *dev; @@ -128,6 +130,8 @@ struct dpu_global_state { uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; uint32_t cdm_to_enc_id; + + uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; =20 struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 3ffac24333a2a5b01135d4ece418432d4a74dc04..309a8cdaafcf3dacd1c7ba4e0cd= db7f3f56423c0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -878,7 +878,7 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, drm_rect_rotate_inv(&pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); - if (r_pipe_cfg->src_rect.x1 !=3D 0) + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) drm_rect_rotate_inv(&r_pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); @@ -1001,8 +1001,13 @@ static int dpu_plane_atomic_check(struct drm_plane *= plane, crtc_state =3D drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); =20 - pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp =3D NULL; + if (pdpu->pipe !=3D SSPP_NONE) { + pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp =3D NULL; + } + + if (!pipe->sspp) + return -EINVAL; =20 ret =3D dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); if (ret) @@ -1019,6 +1024,112 @@ static int dpu_plane_atomic_check(struct drm_plane = *plane, return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } =20 +static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *plane_state =3D + drm_atomic_get_plane_state(state, plane); + struct drm_plane_state *old_plane_state =3D + drm_atomic_get_old_plane_state(state, plane); + struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); + struct drm_crtc_state *crtc_state; + int ret; + + if (plane_state->crtc) + crtc_state =3D drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + ret =3D dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state); + if (ret) + return ret; + + if (!plane_state->visible) { + /* + * resources are freed by dpu_crtc_assign_plane_resources(), + * but clean them here. + */ + pstate->pipe.sspp =3D NULL; + pstate->r_pipe.sspp =3D NULL; + + return 0; + } + + /* force resource reallocation if the format of FB has changed */ + if (!old_plane_state || !old_plane_state->fb || + msm_framebuffer_format(old_plane_state->fb) !=3D + msm_framebuffer_format(plane_state->fb)) + crtc_state->planes_changed =3D true; + + return 0; +} + +static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, + struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_plane_state *plane_state) +{ + const struct drm_crtc_state *crtc_state =3D NULL; + struct drm_plane *plane =3D plane_state->plane; + struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + struct dpu_rm_sspp_requirements reqs; + struct dpu_plane_state *pstate; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe *r_pipe; + const struct msm_format *fmt; + + if (plane_state->crtc) + crtc_state =3D drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + pstate =3D to_dpu_plane_state(plane_state); + pipe =3D &pstate->pipe; + r_pipe =3D &pstate->r_pipe; + + pipe->sspp =3D NULL; + r_pipe->sspp =3D NULL; + + if (!plane_state->fb) + return -EINVAL; + + fmt =3D msm_framebuffer_format(plane_state->fb); + reqs.yuv =3D MSM_FORMAT_IS_YUV(fmt); + reqs.scale =3D (plane_state->src_w >> 16 !=3D plane_state->crtc_w) || + (plane_state->src_h >> 16 !=3D plane_state->crtc_h); + + reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); + + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); + if (!pipe->sspp) + return -ENODEV; + + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); +} + +int dpu_assign_plane_resources(struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_plane_state **states, + unsigned int num_planes) +{ + unsigned int i; + int ret; + + for (i =3D 0; i < num_planes; i++) { + struct drm_plane_state *plane_state =3D states[i]; + + if (!plane_state || + !plane_state->visible) + continue; + + ret =3D dpu_plane_virtual_assign_resources(crtc, global_state, + state, plane_state); + if (ret) + break; + } + + return ret; +} + static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe= *pipe) { const struct msm_format *format =3D @@ -1335,12 +1446,15 @@ static void dpu_plane_atomic_print_state(struct drm= _printer *p, =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - drm_printf(p, "\tsspp[0]=3D%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=3D%s\n", dpu_get_multirect_mode(pipe->= multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=3D%s\n", - dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->sr= c_rect)); - drm_printf(p, "\tdst[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->ds= t_rect)); + if (pipe->sspp) { + drm_printf(p, "\tsspp[0]=3D%s\n", pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[0]=3D%s\n", + dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[0]=3D%s\n", + dpu_get_multirect_index(pipe->multirect_index)); + drm_printf(p, "\tsrc[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->s= rc_rect)); + drm_printf(p, "\tdst[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->d= st_rect)); + } =20 if (r_pipe->sspp) { drm_printf(p, "\tsspp[1]=3D%s\n", r_pipe->sspp->cap->name); @@ -1433,39 +1547,29 @@ static const struct drm_plane_helper_funcs dpu_plan= e_helper_funcs =3D { .atomic_update =3D dpu_plane_atomic_update, }; =20 -/** - * dpu_plane_init - create new dpu plane for the given pipe - * @dev: Pointer to DRM device - * @pipe: dpu hardware pipe identifier - * @type: Plane type - PRIMARY/OVERLAY/CURSOR - * @possible_crtcs: bitmask of crtc that can be attached to the given pipe - * - * Initialize the plane. - */ -struct drm_plane *dpu_plane_init(struct drm_device *dev, - uint32_t pipe, enum drm_plane_type type, - unsigned long possible_crtcs) +static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = =3D { + .prepare_fb =3D dpu_plane_prepare_fb, + .cleanup_fb =3D dpu_plane_cleanup_fb, + .atomic_check =3D dpu_plane_virtual_atomic_check, + .atomic_update =3D dpu_plane_atomic_update, +}; + +/* initialize plane */ +static struct drm_plane *dpu_plane_init_common(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs, + bool inline_rotation, + const uint32_t *format_list, + uint32_t num_formats, + enum dpu_sspp pipe) { struct drm_plane *plane =3D NULL; - const uint32_t *format_list; struct dpu_plane *pdpu; struct msm_drm_private *priv =3D dev->dev_private; struct dpu_kms *kms =3D to_dpu_kms(priv->kms); - struct dpu_hw_sspp *pipe_hw; - uint32_t num_formats; uint32_t supported_rotations; int ret; =20 - /* initialize underlying h/w driver */ - pipe_hw =3D dpu_rm_get_sspp(&kms->rm, pipe); - if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { - DPU_ERROR("[%u]SSPP is invalid\n", pipe); - return ERR_PTR(-EINVAL); - } - - format_list =3D pipe_hw->cap->sblk->format_list; - num_formats =3D pipe_hw->cap->sblk->num_formats; - pdpu =3D drmm_universal_plane_alloc(dev, struct dpu_plane, base, 0xff, &dpu_plane_funcs, format_list, num_formats, @@ -1491,7 +1595,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *d= ev, =20 supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_M= ODE_ROTATE_180; =20 - if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + if (inline_rotation) supported_rotations |=3D DRM_MODE_ROTATE_MASK; =20 drm_plane_create_rotation_property(plane, @@ -1499,10 +1603,98 @@ struct drm_plane *dpu_plane_init(struct drm_device = *dev, =20 drm_plane_enable_fb_damage_clips(plane); =20 - /* success! finalize initialization */ + DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, + pipe, plane->base.id); + return plane; +} + +/** + * dpu_plane_init - create new dpu plane for the given pipe + * @dev: Pointer to DRM device + * @pipe: dpu hardware pipe identifier + * @type: Plane type - PRIMARY/OVERLAY/CURSOR + * @possible_crtcs: bitmask of crtc that can be attached to the given pipe + * + * Initialize the plane. + */ +struct drm_plane *dpu_plane_init(struct drm_device *dev, + uint32_t pipe, enum drm_plane_type type, + unsigned long possible_crtcs) +{ + struct drm_plane *plane =3D NULL; + struct msm_drm_private *priv =3D dev->dev_private; + struct dpu_kms *kms =3D to_dpu_kms(priv->kms); + struct dpu_hw_sspp *pipe_hw; + + /* initialize underlying h/w driver */ + pipe_hw =3D dpu_rm_get_sspp(&kms->rm, pipe); + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { + DPU_ERROR("[%u]SSPP is invalid\n", pipe); + return ERR_PTR(-EINVAL); + } + + + plane =3D dpu_plane_init_common(dev, type, possible_crtcs, + pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION), + pipe_hw->cap->sblk->format_list, + pipe_hw->cap->sblk->num_formats, + pipe); + if (IS_ERR(plane)) + return plane; + drm_plane_helper_add(plane, &dpu_plane_helper_funcs); =20 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, pipe, plane->base.id); + + return plane; +} + +/** + * dpu_plane_init_virtual - create new virtualized DPU plane + * @dev: Pointer to DRM device + * @type: Plane type - PRIMARY/OVERLAY/CURSOR + * @possible_crtcs: bitmask of crtc that can be attached to the given pipe + * + * Initialize the virtual plane with no backing SSPP / pipe. + */ +struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs) +{ + struct drm_plane *plane =3D NULL; + struct msm_drm_private *priv =3D dev->dev_private; + struct dpu_kms *kms =3D to_dpu_kms(priv->kms); + bool has_inline_rotation =3D false; + const u32 *format_list =3D NULL; + u32 num_formats =3D 0; + int i; + + /* Determine the largest configuration that we can implement */ + for (i =3D 0; i < kms->catalog->sspp_count; i++) { + const struct dpu_sspp_cfg *cfg =3D &kms->catalog->sspp[i]; + + if (test_bit(DPU_SSPP_INLINE_ROTATION, &cfg->features)) + has_inline_rotation =3D true; + + if (!format_list || + cfg->sblk->csc_blk.len) { + format_list =3D cfg->sblk->format_list; + num_formats =3D cfg->sblk->num_formats; + } + } + + plane =3D dpu_plane_init_common(dev, type, possible_crtcs, + has_inline_rotation, + format_list, + num_formats, + SSPP_NONE); + if (IS_ERR(plane)) + return plane; + + drm_plane_helper_add(plane, &dpu_plane_virtual_helper_funcs); + + DPU_DEBUG("%s created virtual id:%u\n", plane->name, plane->base.id); + return plane; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index 97090ca7842b41c697090665d89194a87c02cba1..acd5725175cdde4fcf7a9f71bb4= 46251c5a14d22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -62,10 +62,23 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, unsigned long possible_crtcs); =20 +struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs); + +int dpu_plane_color_fill(struct drm_plane *plane, + uint32_t color, uint32_t alpha); + #ifdef CONFIG_DEBUG_FS void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable); #else static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, b= ool enable) {} #endif =20 +int dpu_assign_plane_resources(struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_plane_state **states, + unsigned int num_planes); + #endif /* _DPU_PLANE_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index c247af03dc8ef7174eedf3d5cc267d64f17a8656..2c325bcd328aa475cba9b9a2146= ee3e009816551 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -725,6 +725,88 @@ int dpu_rm_reserve( return ret; } =20 +static struct dpu_hw_sspp *dpu_rm_try_sspp(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs, + unsigned int type) +{ + uint32_t crtc_id =3D crtc->base.id; + struct dpu_hw_sspp *hw_sspp; + int i; + + for (i =3D 0; i < ARRAY_SIZE(rm->hw_sspp); i++) { + if (!rm->hw_sspp[i]) + continue; + + if (global_state->sspp_to_crtc_id[i]) + continue; + + hw_sspp =3D rm->hw_sspp[i]; + + if (hw_sspp->cap->type !=3D type) + continue; + + if (reqs->scale && !hw_sspp->cap->sblk->scaler_blk.len) + continue; + + // TODO: QSEED2 and RGB scalers are not yet supported + if (reqs->scale && !hw_sspp->ops.setup_scaler) + continue; + + if (reqs->yuv && !hw_sspp->cap->sblk->csc_blk.len) + continue; + + if (reqs->rot90 && !(hw_sspp->cap->features & DPU_SSPP_INLINE_ROTATION)) + continue; + + global_state->sspp_to_crtc_id[i] =3D crtc_id; + + return rm->hw_sspp[i]; + } + + return NULL; +} + +/** + * dpu_rm_reserve_sspp - Reserve the required SSPP for the provided CRTC + * @rm: DPU Resource Manager handle + * @global_state: private global state + * @crtc: DRM CRTC handle + * @reqs: SSPP required features + */ +struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs) +{ + struct dpu_hw_sspp *hw_sspp =3D NULL; + + if (!reqs->scale && !reqs->yuv) + hw_sspp =3D dpu_rm_try_sspp(rm, global_state, crtc, reqs, SSPP_TYPE_DMA); + if (!hw_sspp && reqs->scale) + hw_sspp =3D dpu_rm_try_sspp(rm, global_state, crtc, reqs, SSPP_TYPE_RGB); + if (!hw_sspp) + hw_sspp =3D dpu_rm_try_sspp(rm, global_state, crtc, reqs, SSPP_TYPE_VIG); + + return hw_sspp; +} + +/** + * dpu_rm_release_all_sspp - Given the CRTC, release all SSPP + * blocks previously reserved for that use case. + * @global_state: resources shared across multiple kms objects + * @crtc: DRM CRTC handle + */ +void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, + struct drm_crtc *crtc) +{ + uint32_t crtc_id =3D crtc->base.id; + + _dpu_rm_clear_mapping(global_state->sspp_to_crtc_id, + ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); +} + /** * dpu_rm_get_assigned_resources - Get hw resources of the given type that= are * assigned to this encoder diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.h index ea0e49cb7b0d3e05dfa57442784c83acb69c3ada..9cdfa53d7173d41dfefe985fdc7= 7f1885dbec4ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -37,6 +37,12 @@ struct dpu_rm { struct dpu_hw_blk *cdm_blk; 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Sun, 15 Dec 2024 04:40:27 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54120c13be2sm491481e87.195.2024.12.15.04.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2024 04:40:26 -0800 (PST) From: Dmitry Baryshkov Date: Sun, 15 Dec 2024 14:40:17 +0200 Subject: [PATCH v8 2/3] drm/msm/dpu: allow using two SSPP blocks for a single plane Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241215-dpu-virtual-wide-v8-2-65221f213ce1@linaro.org> References: <20241215-dpu-virtual-wide-v8-0-65221f213ce1@linaro.org> In-Reply-To: <20241215-dpu-virtual-wide-v8-0-65221f213ce1@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10016; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=tnabCVU1SaNGNfJfuPGtjX+5svo205A46mZ25LOgd7c=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnXs4zgw0g1NMuBXHYSn79U0Pb6MCr7KeRUAq19 sFxzofeqIaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ17OMwAKCRCLPIo+Aiko 1V72B/9SRkn6NQGBX5zLK1GMEqnx7DjFvFPoNmm290cRH3MaEvHQGhy/cwhii9zXrTp9cxoGZaS wPrS4M1nEyKCuxAAM+LhIcTwyCQ2MTt4iJGEKaNtF8MOt0K0MemZS7fgt8TGPCSvllhylYTXkqq iHxRbvN+tAAaD2WLymXbjV1VGrAyUH2zseRWmRmvXoMHec3l8kQEVX0B/VEqIY6SYgnlhiyWvUt RO2m+hAL3lk75f0cjHLnDQEmGEAupx2zkf1Tm/F1QQpe1aRfHZU97RRvwf8M5UepxuU7TbljLZd LjCfUJOARySPGUM6YCi2NiUCvioWuS855gCtpAEjiSCvAahK X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Virtual wide planes give high amount of flexibility, but it is not always enough: In parallel multirect case only the half of the usual width is supported for tiled formats. Thus the whole width of two tiled multirect rectangles can not be greater than max_linewidth, which is not enough for some platforms/compositors. Another example is as simple as wide YUV plane. YUV planes can not use multirect, so currently they are limited to max_linewidth too. Now that the planes are fully virtualized, add support for allocating two SSPP blocks to drive a single DRM plane. This fixes both mentioned cases and allows all planes to go up to 2*max_linewidth (at the cost of making some of the planes unavailable to the user). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 144 ++++++++++++++++++++------= ---- 1 file changed, 98 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 309a8cdaafcf3dacd1c7ba4e0cddb7f3f56423c0..098abc2c0003cde90ce6219c97e= e18fa055a92a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -20,7 +20,6 @@ #include "msm_drv.h" #include "msm_mdss.h" #include "dpu_kms.h" -#include "dpu_formats.h" #include "dpu_hw_sspp.h" #include "dpu_hw_util.h" #include "dpu_trace.h" @@ -888,6 +887,32 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, return 0; } =20 +static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *ssp= p, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct msm_format *fmt, + uint32_t max_linewidth) +{ + if (drm_rect_width(&pipe_cfg->src_rect) !=3D drm_rect_width(&pipe_cfg->ds= t_rect) || + drm_rect_height(&pipe_cfg->src_rect) !=3D drm_rect_height(&pipe_cfg->= dst_rect)) + return false; + + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) + return false; + + if (MSM_FORMAT_IS_YUV(fmt)) + return false; + + if (MSM_FORMAT_IS_UBWC(fmt) && + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) + return false; + + if (!test_bit(DPU_SSPP_SMART_DMA_V1, &sspp->cap->features) && + !test_bit(DPU_SSPP_SMART_DMA_V2, &sspp->cap->features)) + return false; + + return true; +} + static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, struct drm_atomic_state *state, const struct drm_crtc_state *crtc_state) @@ -901,7 +926,6 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane= *plane, const struct msm_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; - uint32_t max_linewidth; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -923,8 +947,6 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane= *plane, =20 fmt =3D msm_framebuffer_format(new_plane_state->fb); =20 - max_linewidth =3D pdpu->catalog->caps->max_linewidth; - supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; =20 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) @@ -940,48 +962,43 @@ static int dpu_plane_atomic_check_sspp(struct drm_pla= ne *plane, return ret; =20 if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { - /* - * In parallel multirect case only the half of the usual width - * is supported for tiled formats. If we are here, we know that - * full width is more than max_linewidth, thus each rect is - * wider than allowed. - */ - if (MSM_FORMAT_IS_UBWC(fmt) && - drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled form= at\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } + ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, + &crtc_state->adjusted_mode); + if (ret) + return ret; + } =20 - if (drm_rect_width(&pipe_cfg->src_rect) !=3D drm_rect_width(&pipe_cfg->d= st_rect) || - drm_rect_height(&pipe_cfg->src_rect) !=3D drm_rect_height(&pipe_cfg-= >dst_rect) || - (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && - !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || - pipe_cfg->rotation & DRM_MODE_ROTATE_90 || - MSM_FORMAT_IS_YUV(fmt)) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use = split source\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } + return 0; +} + +static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, str= uct dpu_sw_pipe_cfg *pipe_cfg, + struct dpu_sw_pipe *r_pipe, struct dpu_sw_pipe_cfg *r_pipe_cfg, + struct dpu_hw_sspp *sspp, const struct msm_format *fmt, + uint32_t max_linewidth) +{ + r_pipe->sspp =3D NULL; + + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { + if (!dpu_plane_is_multirect_parallel_capable(pipe->sspp, pipe_cfg, fmt, = max_linewidth) || + !dpu_plane_is_multirect_parallel_capable(pipe->sspp, r_pipe_cfg, fmt= , max_linewidth)) + return false; + + r_pipe->sspp =3D pipe->sspp; =20 - /* - * Use multirect for wide plane. We do not support dynamic - * assignment of SSPPs, so we know the configuration. - */ pipe->multirect_index =3D DPU_SSPP_RECT_0; pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; =20 - r_pipe->sspp =3D pipe->sspp; r_pipe->multirect_index =3D DPU_SSPP_RECT_1; r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; - - ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, - &crtc_state->adjusted_mode); - if (ret) - return ret; } =20 - return 0; + return true; } =20 static int dpu_plane_atomic_check(struct drm_plane *plane, @@ -995,16 +1012,16 @@ static int dpu_plane_atomic_check(struct drm_plane *= plane, struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_sw_pipe *pipe =3D &pstate->pipe; struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; const struct drm_crtc_state *crtc_state =3D NULL; + uint32_t max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; =20 if (new_plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); =20 - if (pdpu->pipe !=3D SSPP_NONE) { - pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp =3D NULL; - } + pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); =20 if (!pipe->sspp) return -EINVAL; @@ -1016,10 +1033,17 @@ static int dpu_plane_atomic_check(struct drm_plane = *plane, if (!new_plane_state->visible) return 0; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(new_plane_state->fb), + max_linewidth)) { + DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT + " max_line:%u, can't use split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect), + max_linewidth); + return -E2BIG; + } =20 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } @@ -1054,8 +1078,16 @@ static int dpu_plane_virtual_atomic_check(struct drm= _plane *plane, return 0; } =20 - /* force resource reallocation if the format of FB has changed */ + /* + * Force resource reallocation if the format of FB or src/dst have + * changed. We might need to allocate different SSPP or SSPPs for this + * plane than the one used previously. + */ if (!old_plane_state || !old_plane_state->fb || + old_plane_state->src_w !=3D plane_state->src_w || + old_plane_state->src_h !=3D plane_state->src_h || + old_plane_state->src_w !=3D plane_state->src_w || + old_plane_state->crtc_h !=3D plane_state->crtc_h || msm_framebuffer_format(old_plane_state->fb) !=3D msm_framebuffer_format(plane_state->fb)) crtc_state->planes_changed =3D true; @@ -1075,6 +1107,8 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, struct dpu_plane_state *pstate; struct dpu_sw_pipe *pipe; struct dpu_sw_pipe *r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; =20 if (plane_state->crtc) @@ -1084,6 +1118,8 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, pstate =3D to_dpu_plane_state(plane_state); pipe =3D &pstate->pipe; r_pipe =3D &pstate->r_pipe; + pipe_cfg =3D &pstate->pipe_cfg; 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a=openpgp-sha256; l=1066; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=rtLNZvWI4/c1Z6JTypcd/rzPjp3y7gPITQRLIp73VhE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnXs4zHmqv+4KEvs+fxhU8HXyTshs00svWF3yCZ T6ZvsMWzTaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ17OMwAKCRCLPIo+Aiko 1a/7B/41SmL6WXZHL42KtlTVJqEfm4JwzZrRiO7+EugrG1qKC+8+k1TQMOS8fjmtA9SfefGuwTe qlhWq3y18LWzTMHxLh+BKbguLUrLIP9RsaHzEKF4S6Q5qYrM5BKzKJbYn4AgxOPCKn5ScLAvPqZ jj2K93ctOcK01v9sLQp0bdcIvZWqnhc1algDaWSmFrdpv8FBR+5zOXJnM8nzHbhnU9bqkYieebx 4OvZq2H6wtpipdUTg4Qb2pUkSwjY+ehAhxsL8q07t2SBEfjM7+L53yeF2Y0kuTd/BN0SntNMCSj O9byED58fAcpKgEQr/2GVjwyOMcvx7vR9goNc1p/+p4TDG+p X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Make dpu_rm_print_state() also output the SSPP allocation state. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 2c325bcd328aa475cba9b9a2146ee3e009816551..17b5d53297f23169aba3537f85f= 02f04421ac9e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -941,4 +941,11 @@ void dpu_rm_print_state(struct drm_printer *p, dpu_rm_print_state_helper(p, rm->cdm_blk, global_state->cdm_to_enc_id); drm_puts(p, "\n"); + + drm_puts(p, "\tsspp=3D"); + /* skip SSPP_NONE and start from the next index */ + for (i =3D SSPP_NONE + 1; i < ARRAY_SIZE(global_state->sspp_to_crtc_id); = i++) + dpu_rm_print_state_helper(p, rm->hw_sspp[i] ? &rm->hw_sspp[i]->base : NU= LL, + global_state->sspp_to_crtc_id[i]); + drm_puts(p, "\n"); } --=20 2.39.5