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Sat, 14 Dec 2024 14:43:43 -0800 (PST) Received: from master-x64.sparksnet ([204.111.53.241]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-467b2e8097asm11434201cf.63.2024.12.14.14.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Dec 2024 14:43:42 -0800 (PST) From: Peter Geis To: Heiko Stuebner Cc: Peter Geis , Dragan Simic , Alex Bee , Conor Dooley , Diederik de Haas , Johan Jonker , Jonas Karlman , Krzysztof Kozlowski , Liang Chen , Rob Herring , Sebastian Reichel , Ulf Hansson , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: [PATCH] arm64: dts: rockchip: add hevc power domain clock to rk3328 Date: Sat, 14 Dec 2024 22:43:39 +0000 Message-Id: <20241214224339.24674-1-pgwipeout@gmail.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is a race condition at startup between disabling power domains not used and disabling clocks not used on the rk3328. When the clocks are disabled first, the hevc power domain fails to shut off leading to a splat of failures. Add the hevc core clock to the rk3328 power domain node to prevent this condition. rcu: INFO: rcu_sched detected expedited stalls on CPUs/tasks: { 3-.... } 1087 jiffies s: 89 root: 0x8/. rcu: blocking rcu_node structures (internal RCU debug): Sending NMI from CPU 0 to CPUs 3: NMI backtrace for cpu 3 CPU: 3 UID: 0 PID: 86 Comm: kworker/3:3 Not tainted 6.12.0-rc5+ #53 Hardware name: Firefly ROC-RK3328-CC (DT) Workqueue: pm genpd_power_off_work_fn pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=3D--) pc : regmap_unlock_spinlock+0x18/0x30 lr : regmap_read+0x60/0x88 sp : ffff800081123c00 x29: ffff800081123c00 x28: ffff2fa4c62cad80 x27: 0000000000000000 x26: ffffd74e6e660eb8 x25: ffff2fa4c62cae00 x24: 0000000000000040 x23: ffffd74e6d2f3ab8 x22: 0000000000000001 x21: ffff800081123c74 x20: 0000000000000000 x19: ffff2fa4c0412000 x18: 0000000000000000 x17: 77202c31203d2065 x16: 6c6469203a72656c x15: 6c6f72746e6f632d x14: 7265776f703a6e6f x13: 2063766568206e69 x12: 616d6f64202c3431 x11: 347830206f742030 x10: 3430303034783020 x9 : ffffd74e6c7369e0 x8 : 3030316666206e69 x7 : 205d383738353733 x6 : 332e31202020205b x5 : ffffd74e6c73fc88 x4 : ffffd74e6c73fcd4 x3 : ffffd74e6c740b40 x2 : ffff800080015484 x1 : 0000000000000000 x0 : ffff2fa4c0412000 Call trace: regmap_unlock_spinlock+0x18/0x30 rockchip_pmu_set_idle_request+0xac/0x2c0 rockchip_pd_power+0x144/0x5f8 rockchip_pd_power_off+0x1c/0x30 _genpd_power_off+0x9c/0x180 genpd_power_off.part.0.isra.0+0x130/0x2a8 genpd_power_off_work_fn+0x6c/0x98 process_one_work+0x170/0x3f0 worker_thread+0x290/0x4a8 kthread+0xec/0xf8 ret_from_fork+0x10/0x20 rockchip-pm-domain ff100000.syscon:power-controller: failed to get ack on d= omain 'hevc', val=3D0x88220 Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 S= oCs") Signed-off-by: Peter Geis Reviewed-by: Dragan Simic --- I am pulling this patch out and submitting it standalone. Otherwise there are no changes from the first submission. This was found via educated guessing and extensive testing. This clock is sufficient to permit the power domain to function, but additional clock work will be needed if the hevc block is ever enabled on rk3328. For anyone wishing to attempt enabling the hevc or h265 blocks: Currently the assigned clocks in downstream are not sufficent and the board hard locks if accessed unless clk_ignore_unused is applied. Notes from the rk3328 and rk3228h TRMs show the HEVC and H265 blocks share common clocks and domains, along with a shared sram block that also needs to be enabled. arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts= /rockchip/rk3328.dtsi index 0597de415fe0..7d992c3c01ce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -333,6 +333,7 @@ power: power-controller { =20 power-domain@RK3328_PD_HEVC { reg =3D ; + clocks =3D <&cru SCLK_VENC_CORE>; #power-domain-cells =3D <0>; }; power-domain@RK3328_PD_VIDEO { --=20 2.39.5