From nobody Wed Dec 17 18:05:17 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E298617E472; Sat, 14 Dec 2024 08:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734164272; cv=none; b=EC/WaO40koqVhm9I/8Wp5gkpdp4FaY766r0dN1Dnxt+BFOVAxyGXQfv4AKaszEdO8SFlsP5Aij/Wmr6h25IN2ZGJ43xmbD60kYe1g54HtXHGvoJslYVGR510ZFenX7MHqjKaiEmpE1SXUP5PRcB8ghkJlsRCnMsRTQbJe/6vnIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734164272; c=relaxed/simple; bh=TDZVst93HW3Axin+EiY6SBIjZpf/mWnON2EuEjPJ+bs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fnjCIFQVtHMyvsL6LU5eAFCOIlrIOZJb3pl07N1Tl9ywsQ+aWs7JCZCv2sDQDMclyr8ZdF0qaXyf87z7ypo8fuHnZFOHDgX6NF/K7s/qIxkvrfldlceQknBbBAXUIam+FqjaZF9/hAEcq8THN91lU2x/uuGCIMxke6x3Kvy5ads= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=hrWeQBY4; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hrWeQBY4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=GjbI9 yjF/1xFO2NMYGYkxuegaOWhKvddjGaj/Tq3Puk=; b=hrWeQBY47VenAY7jywHxe Q6/rUgcIAA9Z5/OTWZu61Hi7/urnPlCxY6P7fruRLmx+vucg0kVMAXwcsAvJb7EJ jNyMRbdf3BjpV5yoTYGRbupZr8cP1PB4h5jyHQRGQZ8FFHCKoLgTulJwL5yYalwh UI2RRCyQkWHTqFmDdfnkHs= Received: from ProDesk.. (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wD3fwEQP11ntNLtAQ--.5686S6; Sat, 14 Dec 2024 16:17:28 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, krzk+dt@kernel.org, s.hauer@pengutronix.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, derek.foreman@collabora.com, detlev.casanova@collabora.com, Andy Yan Subject: [PATCH v6 04/16] drm/rockchip: vop2: Setup delay cycle for Esmart2/3 Date: Sat, 14 Dec 2024 16:17:03 +0800 Message-ID: <20241214081719.3330518-5-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241214081719.3330518-1-andyshrk@163.com> References: <20241214081719.3330518-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3fwEQP11ntNLtAQ--.5686S6 X-Coremail-Antispam: 1Uf129KBjvdXoW7JFy8AFW3ZF4UXFy7uF17KFg_yoWkurb_Ka y7WFn8GF4kuFn8X3WUCFWfGrW2g3ZF9F4IyFyDtF98ZF93A3sYya4Syr1UXF15CF4fJr1v 93W8WFnxCr13GjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7IU0zBT5UUUUU== X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqQ61XmddM6y0DAABsQ Content-Type: text/plain; charset="utf-8" From: Andy Yan Each layer needs to set the correct delay cycle to display properly without unexpected offset on screen. Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Andy Yan Tested-by: Derek Foreman --- (no changes since v1) drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 0723a7606cb1..f143df2b13a1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2704,9 +2704,11 @@ static void vop2_setup_dly_for_windows(struct vop2 *= vop2) sdly |=3D FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); break; case ROCKCHIP_VOP2_SMART0: + case ROCKCHIP_VOP2_ESMART2: sdly |=3D FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); break; case ROCKCHIP_VOP2_SMART1: + case ROCKCHIP_VOP2_ESMART3: sdly |=3D FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); break; } --=20 2.34.1