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(unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wD3vwGjPl1n3T_wAQ--.16730S10; Sat, 14 Dec 2024 16:15:41 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, krzk+dt@kernel.org, s.hauer@pengutronix.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, derek.foreman@collabora.com, detlev.casanova@collabora.com, Andy Yan , Michael Riesch Subject: [PATCH v6 08/16] drm/rockchip: vop2: Support 32x8 superblock afbc Date: Sat, 14 Dec 2024 16:15:16 +0800 Message-ID: <20241214081529.3330243-9-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241214081529.3330243-1-andyshrk@163.com> References: <20241209122943.2781431-1-andyshrk@163.com> <20241214081529.3330243-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3vwGjPl1n3T_wAQ--.16730S10 X-Coremail-Antispam: 1Uf129KBjvJXoWxCrW3XFyUGw4xGFykuryUWrg_yoW5Gryrpr W3ZrWqgw4UKF1jqa1DJrWDZF43Aan2k3y7XrnrGr1YqryYkr9rG34DKFyDZrWDt3yfGFW0 vFn3GrW7Zw1Fyr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07j8EfOUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbB0g+1XmddMGzhNQABsF Content-Type: text/plain; charset="utf-8" From: Andy Yan This is the only afbc format supported by the upcoming VOP for rk3576. Add support for it. Signed-off-by: Andy Yan Tested-by: Michael Riesch # on RK3568 Tested-by: Detlev Casanova --- (no changes since v2) Changes in v2: - split it from main patch add support for rk3576 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index b5f35839d5e8..efe7d0cbe155 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1454,16 +1454,18 @@ static void vop2_plane_atomic_update(struct drm_pla= ne *plane, vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en); =20 if (afbc_en) { - u32 stride; + u32 stride, block_w; + + /* the afbc superblock is 16 x 16 or 32 x 8 */ + block_w =3D fb->modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 ? 32 : 16; =20 - /* the afbc superblock is 16 x 16 */ afbc_format =3D vop2_convert_afbc_format(fb->format->format); =20 /* Enable color transform for YTR */ if (fb->modifier & AFBC_FORMAT_MOD_YTR) afbc_format |=3D (1 << 4); =20 - afbc_tile_num =3D ALIGN(actual_w, 16) >> 4; + afbc_tile_num =3D ALIGN(actual_w, block_w) / block_w; =20 /* * AFBC pic_vir_width is count by pixel, this is different @@ -1474,6 +1476,9 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, drm_dbg_kms(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", vp->id, win->data->name, stride); =20 + /* It's for head stride, each head size is 16 byte */ + stride =3D ALIGN(stride, block_w) / block_w * 16; + uv_swap =3D vop2_afbc_uv_swap(fb->format->format); /* * This is a workaround for crazy IC design, Cluster @@ -1504,7 +1509,11 @@ static void vop2_plane_atomic_update(struct drm_plan= e *plane, else vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1); =20 - vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); + if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) + vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 1); + else + vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); + transform_offset =3D vop2_afbc_transform_offset(pstate, half_block_en); vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); --=20 2.34.1