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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241214-dpu-drop-features-v1-28-988f0662cb7e@linaro.org> References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> In-Reply-To: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3942; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=HDBIFP7lmEfohLRdZta0STJnvjaOfr4EoK+lXYqD0Wg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnXLHIlv4aya34bmsQu0LbX/0HpWJVj5ThCnma/ 1TdbRItCBGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ1yxyAAKCRCLPIo+Aiko 1WRaB/4pnAW3brf4JPJfhdjbTwLCg9DaJSGmKWFZkYDkffxlD1HiJSQXH5b2BIkFDBL8nUF6KgT Dr4RTirbZ5jSmPLS4qcoHObGuQoSRQF6vvfeyW/oO2QfyJ308+xeA3MD+cN6BJrfcJ517EqhNeq nuJGK4aKZEO/+FaFkiiz4vVUjEFuzB9EVmJJudSEvWeFe6yXtQ/xn6+DBnG7VhfbYbIj/9DP3dK xBtkybDfFsG5yeHjWVJ88FyBbuFDtR+7S89dlqsbFE706/Dgt6TxFRWR9RO/7a0qXuKitTF28Ad o+PRJkzERJQpUIQAkBm3DSzqxbVdr1zkx4RtttWQStAXjCYZ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Continue migration to the MDSS-revision based checks and replace DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >=3D 4 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++ 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index c23afdbad7b08abed2740e374be5bd89de206bf1..77187b6f5caa8c69498502d7b7e= 9c06b8d01fcb6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -35,12 +35,12 @@ (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) =20 #define VIG_SDM845_MASK \ - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBL= E)) + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) =20 #define VIG_SDM845_MASK_SDMA \ (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 -#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) +#define VIG_QCM2290_MASK (VIG_BASE_MASK) =20 #define DMA_MSM8953_MASK \ (BIT(DPU_SSPP_QOS)) @@ -60,7 +60,7 @@ (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 #define DMA_SDM845_MASK \ - (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ + (BIT(DPU_SSPP_QOS) | \ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 06d1a467921ad53828fc4613d09e4fd766d10339..e1039b731604ef49958ff158d36= e0aef97258ca4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -50,7 +50,6 @@ enum { * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq - * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support @@ -68,7 +67,6 @@ enum { DPU_SSPP_CSC_10BIT, DPU_SSPP_CURSOR, DPU_SSPP_QOS, - DPU_SSPP_QOS_8LVL, DPU_SSPP_EXCL_RECT, DPU_SSPP_SMART_DMA_V1, DPU_SSPP_SMART_DMA_V2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 32c7c80845533d720683dbcde3978d98f4972cce..7dfd0e0a779535e1f6b003f4818= 8bc90d29d6853 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -543,7 +543,7 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_ssp= p *ctx, return; =20 _dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT, - test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features), + ctx->mdss_ver->core_major_ver >=3D 4, cfg); } =20 @@ -703,6 +703,9 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device = *dev, hw_pipe->ubwc =3D mdss_data; hw_pipe->idx =3D cfg->id; hw_pipe->cap =3D cfg; + + hw_pipe->mdss_ver =3D mdss_rev; + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); =20 return hw_pipe; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index 56a0edf2a57c6dcef7cddf4a1bcd6f6df5ad60f6..ed90e78d178a497ae7e2dc12b09= a37c8a3f79621 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -314,6 +314,8 @@ struct dpu_hw_sspp { enum dpu_sspp idx; const struct dpu_sspp_cfg *cap; =20 + const struct dpu_mdss_version *mdss_ver; + /* Ops */ struct dpu_hw_sspp_ops ops; }; --=20 2.39.5