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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241214-dpu-drop-features-v1-16-988f0662cb7e@linaro.org> References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> In-Reply-To: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2459; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=/NnPOG7oiIzewxWYg3YzQ/UzNsq9zG9OnyGw9Ls5kf8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnXLHG6jMDZ5yDcAevjSw28Xh4hS26TBQsquJ6d xULnxrrSrmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ1yxxgAKCRCLPIo+Aiko 1QjECACeBo1ZSnhdDm60oXksK6oQWmuKuKco79Cntx0W+9EwBK+59HdEJ2Zs6J75IoEud9S9mNU 4ukULTZgjbYMu1Em1057NA64f8Z8e/SftJKjkqdyHy9WWTSnB2kh4kJz7i8pOYKSjDY25BX9R+C QulDuJNybExzcu+Z+tEaIZCF9IexXZJwuicHNR4JR899pciHmH+UuIYgBQEVW6Q/o/RcMfwXVk0 RQIVfmAwhEgmZiR9zoRewQLN3C4DaCb56nkpNgYf6q1DaBh0XisTUSGEdSjmoWxubiF4zYpNg3Y Cml6JyZs+gMRLVkjOvli97ZfhA1w8qnMMTLuE3gYa/P8ZFa1 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Continue migration to the MDSS-revision based checks and replace DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 +-- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5d8f89f8a8a6ad772ff5f4cb8421cb3dd09cbc30..0078b203461992267250b6ceae7= 559aeae4bed9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -111,8 +111,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 #define INTF_SC7180_MASK \ - (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_STATUS_SUPPORTED)) + (BIT(DPU_INTF_INPUT_CTRL)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 6c21e1b0ded669b82f5939df748ce267c18d05ae..5afdf7d4324423952f5e9d5735a= d112f600f1b7e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -145,12 +145,10 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from = which * pixel data arrives to this INTF - * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL =3D 0x1, - DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index 8f9733aad2dec3a9b5464d55b00f350348842911..54c2e984ef0ce604e3eda49595d= 2816ea41bd7fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -308,9 +308,8 @@ static void dpu_hw_intf_get_status( struct dpu_hw_intf_status *s) { struct dpu_hw_blk_reg_map *c =3D &intf->hw; - unsigned long cap =3D intf->cap->features; =20 - if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) + if (intf->mdss_ver->core_major_ver >=3D 5) s->is_en =3D DPU_REG_READ(c, INTF_STATUS) & BIT(0); else s->is_en =3D DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); --=20 2.39.5