From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2D1C71E3DE6; Fri, 13 Dec 2024 16:32:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107550; cv=none; b=Y3aWVQfLjtsWbdU2Cq6H9Pv2MDr0h+MwoWavk6tAQyR4xXG+2veEdYg9+ETWXqcJHgO5NuRPcn4KuNWiyrXaASZ4rWkpa33TVdDGhQ0qoMJQCNeR5734ZaLS5hB4Gg5Zo+rICn1noJ51BGo0QXYObU+a7tWLQtpBhZUju5iXX2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107550; c=relaxed/simple; bh=d2wSywQ+sHb/Jc3Nb++hlewo+hF6z7VtpICQMCKwuh0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gc7KWzNARA0GCbT5rREBfwNy1vYETmzYf4vPr5SIqL8VPnzlyZXsqj6wWFeIC4WFB0ZADZVmw/vEpprQzwALYYCcFFTPJt9Y5S8jaZrvCyA0os2eaqayGzGMgOx+XI7EuAZjByL9z2/tkHmHTDCY2HjUXEkMAgwkCwtjfHyseCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 638FA1480; Fri, 13 Dec 2024 08:32:55 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 722933F5A1; Fri, 13 Dec 2024 08:32:26 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring Subject: [PATCH 1/8] dt-bindings: arm: Add Morello compatibility Date: Fri, 13 Dec 2024 16:32:14 +0000 Message-ID: <20241213163221.3626261-2-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to Arm Morello System Development Platform. Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b= /Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 8dd6b6446394..ea5a5e179ed1 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -118,6 +118,9 @@ properties: items: - const: arm,foundation-aarch64 - const: arm,vexpress + - description: Arm Morello System Development Platform + items: + - const: arm,morello =20 arm,vexpress,position: description: When daughterboards are stacked on one site, their positi= on --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2D16357C9F; Fri, 13 Dec 2024 16:32:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107550; cv=none; b=sR3WMABhHCwVABGgvgXHC6Qpc0zizR0U3nEXanEVMTj4wYQ84WEu17t5CVx/tqtXKx2KEb+MBq7a5saE15ZTm85aJJ9hcBaw3G3b/oVqJIfdQ1jyJRARtytcJCQ8+W/JricTt8SbBMCRk3OIfGblX67fvrTjPqEsyg67M0xCq1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107550; c=relaxed/simple; bh=WbsNP70aNF5f1pxp/R9IZQ5P8ZpM4ExN4gGdyhavBmA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TTMtSZ9GasS6WROalf45xdZ0PhGDMzbKZfJDpNhdEqpLInb+3pbiX3ZLcHRTE7D+hgtRnofS3kCv9sMffmj4l42gXrfd9ipxj8Xxtr7WSA4CI/ku4kjDsMh3wjaJTji9kLrSsZ11ucFoYAM1dmYPjEtuw6+oYmIxC/GjNSI45oQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A70E0169C; Fri, 13 Dec 2024 08:32:56 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 96AE13F5A1; Fri, 13 Dec 2024 08:32:27 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring , Viresh Kumar Subject: [PATCH 2/8] dt-bindings: mailbox: arm,mhu: Add missing properties Date: Fri, 13 Dec 2024 16:32:15 +0000 Message-ID: <20241213163221.3626261-3-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for "interrupt-names" and "mbox-name" optional properties. Cc: Sudeep Holla Cc: Rob Herring Cc: Viresh Kumar Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/mailbox/arm,mhu.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Docum= entation/devicetree/bindings/mailbox/arm,mhu.yaml index d9a4f4a02d7c..65a4f66a7273 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -63,6 +63,16 @@ properties: - description: high-priority non-secure - description: Secure =20 + interrupt-names: + minItems: 2 + items: + - const: mhu-lpri-rx + - const: mhu-hpri-rx + - const: mhu-si-rx + + mbox-name: + maxItems: 1 + clocks: maxItems: 1 =20 --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6351C143722; Fri, 13 Dec 2024 16:32:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107552; cv=none; b=bpW/ilMoNRDWb3uFjVkjz8EAjns+ZELrG7G2JbDcKWJL5mWzMPc4lnWvcIph9bAvNye64HR2dwbT3N8T5BCdcFtH4hmAqgU0+S8sPG2CD1pzTpkHH895Yf6WmlpdSdswu6lQodcuq/1qfW+6YlwCx8YTI+yxxktrfmdymz5b6Gs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107552; c=relaxed/simple; bh=7QmUuOLjrlvo8JEWxRoxx5QtErFo+QDPyop3apnkrr4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VrJPzh5oFnbP2UEXV4mRhhQae1jniMIbJLaMsX+9XVeylwMYPZ2imYLrDjTAGwKbqhVeW1ApX7gpWUk/GYPndv4tY7sA9/RWesgRYRtjQv6d5FwlAXHs/cFIEMOWxx1gW4U5jRrHAGDTq60c6Ah7xEaNcMp3/wSNTFZ+a0bmqwM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB7DE1762; Fri, 13 Dec 2024 08:32:57 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA0E13F5A1; Fri, 13 Dec 2024 08:32:28 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring Subject: [PATCH 3/8] arm64: dts: morello: Add support for common functionalities Date: Fri, 13 Dec 2024 16:32:16 +0000 Message-ID: <20241213163221.3626261-4-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/morello.dtsi | 112 +++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm= /morello.dtsi new file mode 100644 index 000000000000..9d84a0840c5b --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + compatible =3D "arm,morello"; + + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &soc_uart0; + }; + + gic: interrupt-controller@2c010000 { + compatible =3D "arm,gic-v3"; + #address-cells =3D <2>; + #interrupt-cells =3D <3>; + #size-cells =3D <2>; + ranges; + interrupt-controller; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + spe-pmu { + compatible =3D "arm,statistical-profiling-extension-v1"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu-doorbell", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "mhu-lpri-rx", + "mhu-hpri-rx"; + #mbox-cells =3D <2>; + mbox-name =3D "ARM-MHU"; + clocks =3D <&soc_refclk50mhz>; + clock-names =3D "apb_pclk"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x06000000 0x0 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x06000000 0x8000>; + + cpu_scp_hpri0: scp-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + + soc_refclk50mhz: refclk50mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_refclk85mhz: refclk85mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <85000000>; + clock-output-names =3D "iofpga:aclk"; + }; + + soc_uartclk: uartclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "uartclk"; + }; + + soc_uart0: serial@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&soc_uartclk>, <&soc_refclk50mhz>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "okay"; + }; +}; --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 86D751E4908; Fri, 13 Dec 2024 16:32:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107553; cv=none; b=b8tqsPUyOresDWuftL0ipSdI2KfS2ObPw8p53kLGfAbCt0XMJWiivdvUggu+EBXU2VR++qW6vX+Y+jBwkDvqUYQycxiNTENl2zPUNAV+qD2BLazxRBEXvL/tdoeg+ZoJAzXiROTqg2S5qY72Ul+0tBoSYuLsLc6s87sCk0SN3lE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107553; c=relaxed/simple; bh=ax1A1fq1ID9TsWzI1wWFDTaeGNPQgEt4Z2I8VkL4lX4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EJCJ/2CNJ4aEh1cLwIqkw0jwJo+zXMV5Xk9TMCISEQM+Pvuye4XKwTaQCG0rchVhE8EhqUV7t5CUlw9wAiEFHCSi0p8Y+dlfNAM0T6qm/46d6rwsXDGlXZ/OWap3/G9Gtafm8OkbrK+tz/MCBC8z/Cg/NMvQ19f8XkUA4fid+vg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F08101595; Fri, 13 Dec 2024 08:32:58 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0ABCE3F5A1; Fri, 13 Dec 2024 08:32:29 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring Subject: [PATCH 4/8] arm64: dts: morello: Add support for soc dts Date: Fri, 13 Dec 2024 16:32:17 +0000 Message-ID: <20241213163221.3626261-5-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/morello-soc.dts | 267 ++++++++++++++++++++++++ 1 file changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/= arm/morello-soc.dts new file mode 100644 index 000000000000..3c5247121e4d --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-soc.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello System Development Platform"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure-firmware@ff000000 { + reg =3D <0 0xff000000 0 0x01000000>; + no-map; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + cpu0: cpu0@0 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 0>; + }; + cpu1: cpu1@100 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 0>; + }; + cpu2: cpu2@10000 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 1>; + }; + cpu3: cpu3@10100 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 1>; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type =3D "memory"; + /* [0x80000000-0xffffffff] */ + reg =3D <0x00000000 0x80000000 0x0 0x7F000000>; + }; + + memory@8080000000 { + device_type =3D "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg =3D <0x00000080 0x80000000 0x3 0x78000000>; + }; + + smmu_pcie: iommu@4f400000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0 0x4f400000 0 0x40000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its2 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + compatible =3D "pci-host-ecam-generic"; + device_type =3D "pci"; + reg =3D <0x28 0xC0000000 0 0x10000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_pcie 0 0x10000>; + iommu-map =3D <0 &smmu_pcie 0 0x10000>; + status =3D "okay"; + }; + + smmu_ccix: iommu@4f000000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0 0x4f000000 0 0x40000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its1 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + compatible =3D "pci-host-ecam-generic"; + device_type =3D "pci"; + reg =3D <0x4F 0xC0000000 0 0x10000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_ccix 0 0x10000>; + iommu-map =3D <0 &smmu_ccix 0 0x10000>; + status =3D "okay"; + }; + + smmu_dp: iommu@2ce00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0 0x2ce00000 0 0x40000>; + interrupts =3D , + , + ; + interrupt-names =3D "eventq", "gerror", "cmdq-sync"; + #iommu-cells =3D <1>; + }; + + dp0: display@2cc00000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "arm,mali-d32", "arm,mali-d71"; + reg =3D <0 0x2cc00000 0 0x20000>; + interrupts =3D <0 69 4>; + clocks =3D <&dpu_aclk>; + clock-names =3D "aclk"; + iommus =3D <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + pl0: pipeline@0 { + reg =3D <0>; + clocks =3D <&dpu_pixel_clk>; + clock-names =3D "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint =3D <&tda998x_0_input>; + }; + }; + }; + }; + + i2c@1c0f0000 { + compatible =3D "cdns,i2c-r1p14"; + reg =3D <0x0 0x1c0f0000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + interrupts =3D ; + clocks =3D <&dpu_aclk>; + + hdmi_tx: hdmi-transmitter@70 { + compatible =3D "nxp,tda998x"; + reg =3D <0x70>; + video-ports =3D <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint =3D <&dp_pl0_out0>; + }; + }; + }; + }; + + dpu_aclk: dpu_aclk { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <350000000>; + clock-output-names =3D "aclk"; + }; + + dpu_pixel_clk: dpu-pixel-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <148500000>; + clock-output-names =3D "pxclk"; + }; + + firmware { + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox 1 0>, <&mailbox 1 1>; + shmem =3D <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; +}; + +&gic { + reg =3D <0x0 0x30000000 0 0x10000>, /* GICD */ + <0x0 0x300c0000 0 0x80000>; /* GICR */ + interrupts =3D ; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30040000 0x0 0x20000>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30060000 0x0 0x20000>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30080000 0x0 0x20000>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + }; +}; --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A746C1E6DDD; Fri, 13 Dec 2024 16:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107554; cv=none; b=V7OvgTqGc82YD7D2JxKl/CuOMfcT3WOXLFjg9z4OQddWQSMlOsqMUwEYepx4XU0hs4mfyEZ+sPz/Tr2BRosoQXjSVDol92JjT9OK+Z5kT0uoto1RxuJajlUK2shbHe4shOFg6Vh7k6bKW9cRrgSIi7VSMQ8yTkQCTPQbjyPKBoc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107554; c=relaxed/simple; bh=IgfT73FbN63LEJMuEc0uWO3bBGLK3ff5ppznG3IGQNk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tg4Rd5hIFQWboxSbzeNkuPAGMeFnNYGFb0lT3OJtj9gEYs7Oco9mBrfKEA09id4khn5ko5IW6kosz3QaiOEn0aNsr4DT+5VBeF3mFfNBlo25WJOXU17cZprkx+Ra5F5ZG9cdAQFJ/1iLSa+3wuqRf+NeM7hCMqOkQfJQIxhahiU= ARC-Authentication-Results: i=1; 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charset="utf-8" Introduce the Kconfig entry for the Arm Morello System Development Platform. Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 370a9d2b6919..1c4867ea9407 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -250,6 +250,11 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. =20 +config ARCH_MORELLO + bool "Arm Morello System Development Platform" + help + Enables support for Arm Morello System Development Platform + config ARCH_PENSANDO bool "AMD Pensando Platforms" help --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C9ED21E885C; Fri, 13 Dec 2024 16:32:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107555; cv=none; b=ZQQug4cCk2uhu4dIZNp46RbmuzpoeOZi60eKf97P/OWUov3DAQFu3bNs/3YIGfW5r+b/pnP4MCBQz2U+TvKrFYY83JDh6/k8lBbKOzMZHVJYyJ+RxnnZntg9x0VgwEFGJbyUMHPlvll2m3sW6Coo6l4WkLSD/SG+uHt/WAVn97s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107555; c=relaxed/simple; bh=aK95q5XfHl9fcLpGyMTNRnTpkt2Q2J5HjjoKL6ecjFs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CwEg8Se8yTy9uM1TKa68stsK31OvI8pnE4WC3vL4wpjV7uuuFi2nolPDUDBCjUOHCddq3dqt5rPXOwOUqEWVTOQLr2s2IpO8n4nDn0pKRSw9qZuGmJciLcj8W+e/T3uL2S+l+I5yHg24GW4MZjdT68k+s4+OzgoXZcGEKcti1gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4544B169C; Fri, 13 Dec 2024 08:33:01 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 53E2F3F5A1; Fri, 13 Dec 2024 08:32:32 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring Subject: [PATCH 6/8] arm64: dts: Add Arm Morello System Development Platform support Date: Fri, 13 Dec 2024 16:32:19 +0000 Message-ID: <20241213163221.3626261-7-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Arm Morello System Development Platform support. Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index d908e96d7ddc..0a821808692e 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_MORELLO) +=3D morello-soc.dtb --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 825491E7648; Fri, 13 Dec 2024 16:32:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107555; cv=none; b=eRrVP/PNa+q0QSVXeymDytKUpADUQlDPSbFkLdgHIcHxdndvZXvxCSzxQC1uMfUU6ORlvDxle0dPRgSmKxan1BEjip8B4c8X1lFG+QjJ2RJ4Y/zRuygBcZf11Mx3QtvmkK7hpDxwwkGP9mFDd6dWeH+2hhq+7WAX6eB1z5UGhgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107555; c=relaxed/simple; bh=5sYNH5xngnbOUzmCesRU/m86+lcwj/yMVwQW7liESdk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lYP1wya1SepbI+TdwXGDleoIGo/gaPf2t0kvvTRKhE9xYzXrau8+4gTLbl3E4DydKa8WLN9sewvtJ4QlUSX3gexSFcEQYKDpp1/AyfYHYmS7javvrDJwUPExAWAoGomT5BnzWDd+3rPeQK1l03Iwsb+LEKBYrsXPHl3Q8DiE6Js= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A4491595; Fri, 13 Dec 2024 08:33:02 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 78C383F5A1; Fri, 13 Dec 2024 08:32:33 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring Subject: [PATCH 7/8] arm64: Enable Arm Morello System Development Platform support Date: Fri, 13 Dec 2024 16:32:20 +0000 Message-ID: <20241213163221.3626261-8-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable Arm Morello System Development Platform support in defconfig. Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c62831e61586..44b97b0b1e62 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -58,6 +58,7 @@ CONFIG_ARCH_LAYERSCAPE=3Dy CONFIG_ARCH_MXC=3Dy CONFIG_ARCH_S32=3Dy CONFIG_ARCH_MA35=3Dy +CONFIG_ARCH_MORELLO=3Dy CONFIG_ARCH_NPCM=3Dy CONFIG_ARCH_QCOM=3Dy CONFIG_ARCH_REALTEK=3Dy --=20 2.43.0 From nobody Mon Feb 9 09:21:59 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A55B51EC00E; Fri, 13 Dec 2024 16:32:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107557; cv=none; b=UksRWVVU0C3GrZHVXA8Xu24sUexEh/YACOyEH6dRhUguW4etxBzThtW10MaZw07cWPRBJiBAjVkBFNnaA3vR7l7RX/2WCI9mZUGXso8i9m/D3IFJ1LTmkwm8mbebjRbSqDviNPaZtr54/wSRGsC5ZeW8hb56CsEQFsdA6OWH4ow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734107557; c=relaxed/simple; bh=T3qmkBuZLQOTIecUS6FsHeZHQVAmH8NCq3yHhaZQbF0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OBeLjZoSqRVtRnNNPKXZ+9O73gccu9x2PzDlfengGBnRaS4N6Tdd4POqWKMOHRtg+P5NCmragotRN6Tqs1YsxRaZzrjkc+AV1r+Qn4geLok1RQN+grTpiK1FaQi6ul7RCBfM64TmFCI/VL72JUkX5owRmmZVVMq9os/MT5DuH+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EAC11480; Fri, 13 Dec 2024 08:33:03 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D5333F5A1; Fri, 13 Dec 2024 08:32:34 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vincenzo.frascino@arm.com Cc: Sudeep Holla , Rob Herring Subject: [PATCH 8/8] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer Date: Fri, 13 Dec 2024 16:32:21 +0000 Message-ID: <20241213163221.3626261-9-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213163221.3626261-1-vincenzo.frascino@arm.com> References: <20241213163221.3626261-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Cc: Sudeep Holla Cc: Rob Herring Signed-off-by: Vincenzo Frascino --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e6e71b05710b..8199e5945fb2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3304,6 +3304,12 @@ F: drivers/clocksource/timer-versatile.c X: drivers/cpufreq/vexpress-spc-cpufreq.c X: Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml =20 +ARM MORELLO PLATFORM SUPPORT +M: Vincenzo Frascino +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm64/boot/dts/arm/morello* + ARM/VFP SUPPORT M: Russell King L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0