From nobody Sun Feb 8 13:49:56 2026 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2069.outbound.protection.outlook.com [40.107.223.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBE6E1B415F; Fri, 13 Dec 2024 10:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734086416; cv=fail; b=JVfpEsVBwHlhZ2OWzjNN9+a2CKk3qAcFCz20Y8vqpUEgOoCwlhtTg+9l8k/PhZfqwToCHf6BsRictwWIXFZi/opqO0Ynd5a/VCAoRQYMyjlXZh6Ix+mVYtDGhssLvNBp06CDR8UIs0ofN+KMDXK3FVPzbsQudtyG6YDmBxu++vQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734086416; c=relaxed/simple; bh=RqKXWU20Hn87zq836ji/BUkRXHC8+HPatpeJT1RIW3M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XuIbGBAKSXBQCYQe2izkOospEAe0aT93XpEqjZcV6LyEy9p/MK6AHDDNT3YmgMt3TGsGp95cvtYI1BzXfUFECg/kDv99xj68nJVR59VAmpH3fOkYSEgbqi+teRcLzGsOmPj7sAh5zfhgPQEd6ygwUV/TOB7DEoyHn6QeilueC4c= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=BRmnNs/o; arc=fail smtp.client-ip=40.107.223.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BRmnNs/o" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=L7GcJcN9CK6kC1j52mA68Vuzs/EioslhAVkvXiWfH+2q1QgaNfDGjeNOaiLfP7c9prcNNx9KEfXbemquGqgH8usOkyqefbVbCErPEzx5gzkFv5t1nrvAEWD5o0plcaJP/PV6z2xmqhiMOqNjZ5JgbdM9aH6A3j5fp48C4uHg7aN91GT+YKojG7ezgmLpxLd5kfV1DHRJ3XLL26RcdYSu7SDgRQV+YT9na1+nANHSHp9MoZUGNuafRk3N9ZasWQRcdr0jNPX60tKCWtAkN1vpH3AC7Fq5vafodJ758vRRdXO/MMQDe6XcSAlAmFPD1lpGH3VBBK1qJJdewI1Dk+oA+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OoCrYcbvwGybbgE24xOKs0EIylThFWF54UQdKYLSiHk=; b=wSR74SzdYBOBtH4FUFqiLvnQAJ5nkUxEOco15QpN03soY4NRfyzwIwraTUxJLJkUhUXyb/BUZvDVHwy+FfjW7kv6sF6AsNZK/9Sfyq9EsydezAKDu7d9nBy6AtlTncI5azyVWuKI5QKKyW+mwPqruCqs4K9N4Pta6zpHQrwHube0aQbcgbe5ZIjKB1py+KPKCpsnzmEE9lC9o651lJYdNQrmIJLLZSd3auKY5PXY18abfq1aWZ8q0r95NltrydS9GZpwX+eETP01jLYufpTReH1aW/9Eya1oCHnrsZ4R1R5565wXIgVnRpYjwHyzSpqinBBZqBaiM6J6obsOon2UbA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OoCrYcbvwGybbgE24xOKs0EIylThFWF54UQdKYLSiHk=; b=BRmnNs/oOG9e4CnhvmSfOFKl6+8kGgY/VAYc4s4t8eOOuPuUH7nwyK6wA6bnGReOu1JxQf49EKmOKFWa8zJWXaf4aTJbVT3RdVFoII6rDuIe7DybNTPTPbl6Ek9LCUw07zTJlwmyDVnqIhEbnxM/iV3XsY1yuL9vbt9SVreSlbl2JrMplS2JqR2DRscNNY4cO03Q1wnbNpzdk3GQN74PHZipvALRVvXmnsyL39sqWra1t6yttdmUJ5/oVXV8Q76wUmp8/0cEBCiSbgM+GBcDQrmvQKu0svBaF8H6J647J6Q1ocg20jIiCyTBXJ/NpkiDBk+zt4MhgBvNO90NT8IzEw== Received: from DS7PR06CA0033.namprd06.prod.outlook.com (2603:10b6:8:54::15) by PH7PR12MB6537.namprd12.prod.outlook.com (2603:10b6:510:1f2::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15; Fri, 13 Dec 2024 10:40:09 +0000 Received: from CY4PEPF0000EDD5.namprd03.prod.outlook.com (2603:10b6:8:54:cafe::ec) by DS7PR06CA0033.outlook.office365.com (2603:10b6:8:54::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8251.16 via Frontend Transport; Fri, 13 Dec 2024 10:40:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EDD5.mail.protection.outlook.com (10.167.241.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15 via Frontend Transport; Fri, 13 Dec 2024 10:40:08 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 13 Dec 2024 02:39:55 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 13 Dec 2024 02:39:55 -0800 Received: from 13db4e1-lcedt.nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 13 Dec 2024 02:39:51 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , Mohan Kumar D Subject: [PATCH v2 1/2] dt-bindings: dma: Support channel page to nvidia,tegra210-adma Date: Fri, 13 Dec 2024 16:09:38 +0530 Message-ID: <20241213103939.3851827-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213103939.3851827-1-mkumard@nvidia.com> References: <20241213103939.3851827-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD5:EE_|PH7PR12MB6537:EE_ X-MS-Office365-Filtering-Correlation-Id: e7892e99-2e8b-4766-ca42-08dd1b628395 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QbzjfaUt6dLukBcdQXE3uFRIq0uHYchFXNduq+ztan+NtMRYFDijU8OLUoVM?= =?us-ascii?Q?B4LtH2It/0la4ypHks4/Ic8BLNiJb4yiQpbuFePRF+gxEVY0H8qaE+2cKLky?= =?us-ascii?Q?N9o4sIvC8nHszfCchk4Kahk9wmgUfMnGzmNjUO2dgh60FV89SUVxOMfNgDtC?= =?us-ascii?Q?rqyPxdY3snrn9fA3+SxfOSEVTrwRu8f0IEvsID4zDRSGq6Te3n6eGBvwCLcf?= =?us-ascii?Q?Rk7ANimRcSbXmmNu/5qyivkEa7Nnvn7UyNQV6AjSR1ApnMtM3sBByps/g7Oa?= =?us-ascii?Q?HC0WaXfeXpn5cYWcJqz1OJG6TMqAOmOOlzwQAl3jCdsJZ5NhZX/qQRrnv4Gp?= =?us-ascii?Q?bhS5mrcIrRVEQ+iDSjO5DzxWlhHUSLXXnlWEOnm5qzPIRb8kTAXeRJCeDcpQ?= =?us-ascii?Q?ZnAZomjfR3kaGtTFOQJtNYbNl5YYJv7WnpKAYqKPopq+ec33ZTggUuwcZKfX?= =?us-ascii?Q?pspbaZn10m5bXQE7fQjwOspQ0I2YYT6mRpsebRIDA7dEMVe6PVyVYBXwcFxq?= =?us-ascii?Q?YYrr6/zn6T39Cv5do6MfLOv6xpXqbew0cSH1jLdfChoOse+koCprKl8cJmYl?= =?us-ascii?Q?QdQ/7tkNgSr51eFeFqRuo16UcOyG2EtHHvZumKRRy6MGYVtrzeiXzDwdF6VG?= =?us-ascii?Q?lNPyEADISuUqhqNBMJKyCJMdvVwOkjy84DgemWdYtetk2PdQnj2vvCHclOCc?= =?us-ascii?Q?ReW/aV9awVe26WG3NR+b7pWxWsbahSrtsLs/GK+q2MbJo+ntYMpkAcvmPUuB?= =?us-ascii?Q?Q9Kkooz1DeNvccQwDHqzIdOUdTXn/0YyrVpjDYPE5kml+mHd2HrRNEi3qbxC?= =?us-ascii?Q?BXXhh3L0hQSTdiUAPCcSPq7Ek8oGQjlPwJ+B0lKIopHzT2ZwNqYI87/PYXlM?= =?us-ascii?Q?DUwTn0/IvsRo8ODLTRTWDEu8qmZa9hPljENGcS3rdmNj4V+Ff7o2vxjzw+Ie?= =?us-ascii?Q?QWPho/KshYnNsk8bJx3bACSArZlOAhEg7jLNVfY66Vux6tmqeUmQrbRUIORv?= =?us-ascii?Q?7joYyS/xcjYnKLikUI1lF7E72KENl9wqSdS20vSSnvUgBWTrM8Kz2DemHZkj?= =?us-ascii?Q?bW7mm4KN/P3goWgJPtP0GCol02eRrhvtN6XoTDag2DdSuCornTkHPnpxxi9/?= =?us-ascii?Q?Xxq9hA70H0slbHWZolZyCIR71tEQ/fluqTTAd30kVrHZQiJxl5CfM1LTUMqF?= =?us-ascii?Q?X7Vsf6WauYOdMkb70JvvxGmJTFwkvvJSjf1dg/o9mBEK563BGMpXHofmoAj+?= =?us-ascii?Q?pBOPsTVrTMFcPo/T9PznIJ9QSWyKVgLawXGTSbtmDfAJA3VNPSBNi5T4ruHt?= =?us-ascii?Q?f8pZpy135xYmdrH2x1mZuorCdWrGEW+h9h7RySuT2ssYDkL68hL3WGE4x6pM?= =?us-ascii?Q?KJPpwRA+8dMA0YslsRyoermqUXXzM2L5YFfmwWmqekFvUqN0t3N/gskdNBij?= =?us-ascii?Q?VsFkWoMnEYd74GLI9GRgNbOQHXHEddGd?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Dec 2024 10:40:08.3761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7892e99-2e8b-4766-ca42-08dd1b628395 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6537 Content-Type: text/plain; charset="utf-8" Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D --- .../bindings/dma/nvidia,tegra210-adma.yaml | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yam= l b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..d3f8c269916c 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -13,9 +13,6 @@ description: | maintainers: - Jon Hunter =20 -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: @@ -29,7 +26,19 @@ properties: - const: nvidia,tegra186-adma =20 reg: - maxItems: 1 + description: + The 'page' region describes the address space of the page + used for accessing the DMA channel registers. The 'global' + region describes the address space of the global DMA registers. + In the absence of the 'reg-names' property, there must be a + single entry that covers the address space of the global DMA + registers and the DMA channel registers. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 =20 interrupts: description: | @@ -63,6 +72,49 @@ required: - clocks - clock-names =20 +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-adma + then: + properties: + reg: + items: + - description: Full address space range of DMA registers. + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + anyOf: + - properties: + reg: + items: + - description: Full address space range of DMA registers. + - properties: + reg: + items: + - description: Channel Page address space range of DMA reg= isters. + reg-names: + items: + - const: page + - properties: + reg: + items: + - description: Channel Page address space range of DMA reg= isters. + - description: Global Page address space range of DMA regi= sters. + reg-names: + items: + - const: page + - const: global + additionalProperties: false =20 examples: --=20 2.25.1 From nobody Sun Feb 8 13:49:56 2026 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2076.outbound.protection.outlook.com [40.107.223.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69D761C3BE7; Fri, 13 Dec 2024 10:40:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734086419; cv=fail; b=nI9sjbsqVwLZ4oG2gDTsxNToBeBFxX4pNTjltQohCRSJBEV6O2jW/APST0qprTNA7xDhTk/liCQn9p55sODnivMlls+DsaYoWMaFadvdPd4ZJHljPzoLiV10EI/JpjtwDp7MWNjvOh6yxpwxSPWvPolLP8Hd2kdH2a3aOFBi1NQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734086419; c=relaxed/simple; bh=t2O0J+ehR56uejV8Dv1PgD98ZExfvTkfzfaRBJIICbg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o5xA2dA3q8wRfHXLdf4CWQqSMVmeQMnCDUjW1sLU7a8WiMSvKXFcEgk+E0yyxS6Dpf4hXW09dpHP2l+5EQBlgHYJm3KSpGlX6g1MIm5D2SSKN+bYZP62KCvIviIHeFpMv4ZTm4RdH/1F6t6NpuYISrSU381tG5yh4vcARcLDxfo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=mFNvNkpP; arc=fail smtp.client-ip=40.107.223.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="mFNvNkpP" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=w68licwPk8ZoHEUwnOI0vXA5jScHQswb0i2Ii7CohP8H/1mcAecelpQ8f0I3SfsPJ98zOPlrmRUFcCpw50XHns0iJm0B/U/fTsr8cfoAqea7W7Ysb51vkFY9rfParvfwTX00jiF3Gp+jhUqrH1kwzOth60r+fkw5EtRq3276YwFs5EQjHXqXMlOcRIJ4j3UYkW4Qz3yx53ckm0TZhoebkDwx5XC0He+hJinGBdU8Xy8xthzRPzpky3K+VrOrXE2OApY5luWT4oAEm5h+8vo+Y5xVHuNiQboinZcneZrsqnOsI5ThLoNCb3NQowX/FrhJsZtCmsAFVSjvscNVXG+CHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=FIIu534TX3lhOryF2fscbWwyfydqGSYwW+sCHVbJG8M=; b=apsDCdF0eTebdhxM8pDJ9bOcvie4Nk8zl7YaKSw8z3uFXeRqi5/wMPH0Cf07FumJa9Ct7KA3FaQl/lbnXCs5ry9gBR1XMyFJePyCVImKcsS2VC87xjcLwW0cKVy2Kt/rOc0g7DlbVm9lL8wHnX45jGNTy84FZXNzbyi7f33a7YOinm1uxe+kKvfIdkdWhpunepFkohiBMXqARPLoYAhwWEMeh0aYCEhhWVjYxeBIOzZaI2B3HKa2KwC3gIdjeInmkAW4N4uZYeM4bQOYoeLMSsX77+WOy0jGlyNrr3iPTrRAq3z7NoScOeQpgVDvfgtwq31mzq8LtxL8dZH9UX88AQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FIIu534TX3lhOryF2fscbWwyfydqGSYwW+sCHVbJG8M=; b=mFNvNkpPSD8bXAfA2bXgHUkmvmgCHIbjWSroqa5QWf8HGEAf6VTZpoZcRn8j9781hLy9efioXFcVlZjvWZSgUO3xw6DnSBz5JgLnYI0MLTHfpvuFhYnb3d3B2tHau0eVYh+0wgiwlVVBZKYv7eLOwovmAyQ4G3OAC6Sq3o/indn1SIdGbo5L0HSutY9FplSAt54zfqLEXO8BvXFFVmN31BSCeu4xCDK5HG3/y5oeQubzuJ8bhPDdDX0QpY22NAyq6a/IfeH9xitTeXB1bVL4uPK0KyWPgKxNXH+XzGb8bGnmddXhqdWRryoZ8OwOEclJ4bnFSKHP5FKyfUQffjO0tA== Received: from SJ0PR13CA0053.namprd13.prod.outlook.com (2603:10b6:a03:2c2::28) by PH7PR12MB5783.namprd12.prod.outlook.com (2603:10b6:510:1d2::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.22; Fri, 13 Dec 2024 10:40:11 +0000 Received: from SJ5PEPF000001F3.namprd05.prod.outlook.com (2603:10b6:a03:2c2:cafe::20) by SJ0PR13CA0053.outlook.office365.com (2603:10b6:a03:2c2::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8272.5 via Frontend Transport; Fri, 13 Dec 2024 10:40:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SJ5PEPF000001F3.mail.protection.outlook.com (10.167.242.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8251.15 via Frontend Transport; Fri, 13 Dec 2024 10:40:11 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 13 Dec 2024 02:39:59 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 13 Dec 2024 02:39:58 -0800 Received: from 13db4e1-lcedt.nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 13 Dec 2024 02:39:55 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , Mohan Kumar D Subject: [PATCH v2 2/2] dmaengine: tegra210-adma: Support channel page Date: Fri, 13 Dec 2024 16:09:39 +0530 Message-ID: <20241213103939.3851827-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213103939.3851827-1-mkumard@nvidia.com> References: <20241213103939.3851827-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|PH7PR12MB5783:EE_ X-MS-Office365-Filtering-Correlation-Id: e89c7fe4-3932-49ce-5e4a-08dd1b628588 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gaMn3aOgLsW+8LaK/3CO3WiNxrjNmQx3zGBisHWOPtyWKzJHRbFkgJ0/XzPK?= =?us-ascii?Q?v3GekCwyv35xLudr3z+EALOkhGGFfGtw4Agc2PvVCq0hSUqm+k+oRznHScSR?= =?us-ascii?Q?qyH2beLCJ1b+NWtOFiG2vZ8JD4nIoz1iHGHM8LVgXj/Hhf4af2E4wvyD9EiE?= =?us-ascii?Q?gMDDgQhNotxfcRnPuEFmtdJcMJYbkGej3Qq91P8I9DsvKU21eAkid5Jo+/HY?= =?us-ascii?Q?Gj+ygceNNiViWpsoD+0kbq1PCIBQp8kuRJU3HRgVg+BSF2HPWurb6m7O6uOu?= =?us-ascii?Q?Wc5M3OfFMpHpGIpHSSJPlOmvWwnDrSu4aR7dukfVQlU3qeJh+C32isHs6Db3?= =?us-ascii?Q?Dmfa8c+XnN79ZVAnGSJv/Zs6HRmViGGcW4E7LByjRV1sTjjA4QvXpLpb7Eu8?= =?us-ascii?Q?CeyESlUDN1mf0r9rIVLYdsNdGZrgVe6ly2FOj2z6iMU8vStgNl2CusmZmju6?= =?us-ascii?Q?YXYcUeb6kaf/zSjoyTNv3K0LZBwtAHN1/ipKTIuCkjTCEO4N0igcCFGxaeC7?= =?us-ascii?Q?tHfhLvghR2MpYYNZjLiMqZm8VDhKbqbfTd48yxHk4ZhYgnZ9GTJjVH3SyKOO?= =?us-ascii?Q?aSsmJ1Z2llKuFe25A3GfMid77p+1cu+uAM46LvqlautkEh6zjh5umQ0utD3I?= =?us-ascii?Q?1O2PRFJwYBcvXUP8GCUkVpNj0JljMSKyAEhIZIYKANnizCc0qm7h3IK2RwkM?= =?us-ascii?Q?j82SQlVvUwCATa3B2QlIOOLKguVH48wOqpRuR9Rd7ZLWQq37WdcZVBHLluM9?= =?us-ascii?Q?9O/tj5ls6uxtDCDBghOWloC572mCGM5qcnQwiLhkpbxm2/xdtCKdYp/BgIu4?= =?us-ascii?Q?H1TFouhVt8cYZwnuun867fydq6n20m1cEsu8l4eLjAMm1MyaXh5XWcCFOYn6?= =?us-ascii?Q?ho3ABuctRocEsSmD02IqGvp6O0cqrN5feVMupO0czUE4X9DElJGO6X/L4DEe?= =?us-ascii?Q?oQNjcJC4TIvcRCAIatXrCt8X341TuApTTr7/FN8eVluTxZ/nN7r+giP59/q6?= =?us-ascii?Q?viAj5oI26NCE1yR2YsFIJMLs9EPCgt8c3BCDTL8eDa4DmAjXuS26x9cHKtFa?= =?us-ascii?Q?49LZSX888jcoJgfw3PG+ewVp0pkCqLR/i9aGu8rNZM7BR8GG9xwmatwwD5vN?= =?us-ascii?Q?YN3wDaB7UPGFgQFfCsnqxTdj10ixynRBZ1ueBd6yr4rVaJQdmnuTK/3HjzFX?= =?us-ascii?Q?N152X/nPTt80oJl9oJGPL1N3sgsyNEZh0TEF4b/p9TTbJMKfWOjnG84urFOJ?= =?us-ascii?Q?MLj/KhMGvbYl9VeFGGP2btjAt/raE5eSgg+pecKoodGuBF5ddjvLBi3kCTjd?= =?us-ascii?Q?WwRQe3nGvEMhmj8hGbSx758j2ZsQEYsQbdTyalTPpZoewTygtFVp3XnIxnPP?= =?us-ascii?Q?GlWEbiUbN3imqaAVrsY8cj1FRX/lAGOcPyQAFO0Ut4oLC6wKIokhv4AdI1v9?= =?us-ascii?Q?w0dqi9uY+EveqkwN3LPExPzxpcoVcz5F?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Dec 2024 10:40:11.6123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e89c7fe4-3932-49ce-5e4a-08dd1b628588 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5783 Content-Type: text/plain; charset="utf-8" Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. - Add support in the tegra adma driver to handle selective channel page usage - Make global register programming optional Signed-off-by: Mohan Kumar D --- drivers/dma/tegra210-adma.c | 86 ++++++++++++++++++++++++++++++++----- 1 file changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 2953008d42ef..6896da8ac7ef 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -43,6 +43,10 @@ #define ADMA_CH_CONFIG_MAX_BUFS 8 #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4) =20 +#define TEGRA186_ADMA_GLOBAL_PAGE_CHGRP 0x30 +#define TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ 0x70 +#define TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ 0x84 + #define ADMA_CH_FIFO_CTRL 0x2c #define ADMA_CH_TX_FIFO_SIZE_SHIFT 8 #define ADMA_CH_RX_FIFO_SIZE_SHIFT 0 @@ -96,6 +100,7 @@ struct tegra_adma_chip_data { unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; bool has_outstanding_reqs; + void (*set_global_pg_config)(struct tegra_adma *tdma); }; =20 /* @@ -151,6 +156,7 @@ struct tegra_adma { struct dma_device dma_dev; struct device *dev; void __iomem *base_addr; + void __iomem *ch_base_addr; struct clk *ahub_clk; unsigned int nr_channels; unsigned long *dma_chan_mask; @@ -159,6 +165,7 @@ struct tegra_adma { =20 /* Used to store global command register state when suspending */ unsigned int global_cmd; + unsigned int ch_page_no; =20 const struct tegra_adma_chip_data *cdata; =20 @@ -176,6 +183,11 @@ static inline u32 tdma_read(struct tegra_adma *tdma, u= 32 reg) return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); } =20 +static inline void tdma_ch_global_write(struct tegra_adma *tdma, u32 reg, = u32 val) +{ + writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg); +} + static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32= val) { writel(val, tdc->chan_addr + reg); @@ -217,13 +229,30 @@ static int tegra_adma_slave_config(struct dma_chan *d= c, return 0; } =20 +static void tegra186_adma_global_page_config(struct tegra_adma *tdma) +{ + /* + * Clear the default page1 channel group configs and program + * the global registers based on the actual page usage + */ + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP + (tdma->ch_page_no * 0x= 4), 0xff); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ + (tdma->ch_page_no * 0= x4), 0x1ffffff); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0= x4), 0xffffff); +} + static int tegra_adma_init(struct tegra_adma *tdma) { u32 status; int ret; =20 - /* Clear any interrupts */ - tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_cl= ear, 0x1); + /* Clear any channels group global interrupts */ + tdma_ch_global_write(tdma, tdma->cdata->global_int_clear, 0x1); + + if (!tdma->base_addr) + return 0; =20 /* Assert soft reset */ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); @@ -237,6 +266,9 @@ static int tegra_adma_init(struct tegra_adma *tdma) if (ret) return ret; =20 + if (tdma->cdata->set_global_pg_config) + tdma->cdata->set_global_pg_config(tdma); + /* Enable global ADMA registers */ tdma_write(tdma, ADMA_GLOBAL_CMD, 1); =20 @@ -736,7 +768,9 @@ static int __maybe_unused tegra_adma_runtime_suspend(st= ruct device *dev) struct tegra_adma_chan *tdc; int i; =20 - tdma->global_cmd =3D tdma_read(tdma, ADMA_GLOBAL_CMD); + if (tdma->base_addr) + tdma->global_cmd =3D tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->global_cmd) goto clk_disable; =20 @@ -777,7 +811,11 @@ static int __maybe_unused tegra_adma_runtime_resume(st= ruct device *dev) dev_err(dev, "ahub clk_enable failed: %d\n", ret); return ret; } - tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + if (tdma->base_addr) { + tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + if (tdma->cdata->set_global_pg_config) + tdma->cdata->set_global_pg_config(tdma); + } =20 if (!tdma->global_cmd) return 0; @@ -817,6 +855,7 @@ static const struct tegra_adma_chip_data tegra210_chip_= data =3D { .ch_fifo_size_mask =3D 0xf, .sreq_index_offset =3D 2, .has_outstanding_reqs =3D false, + .set_global_pg_config =3D NULL, }; =20 static const struct tegra_adma_chip_data tegra186_chip_data =3D { @@ -833,6 +872,7 @@ static const struct tegra_adma_chip_data tegra186_chip_= data =3D { .ch_fifo_size_mask =3D 0x1f, .sreq_index_offset =3D 4, .has_outstanding_reqs =3D true, + .set_global_pg_config =3D tegra186_adma_global_page_config, }; =20 static const struct of_device_id tegra_adma_of_match[] =3D { @@ -846,7 +886,8 @@ static int tegra_adma_probe(struct platform_device *pde= v) { const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; - int ret, i; + struct resource *res_page, *res_base; + int ret, i, page_no; =20 cdata =3D of_device_get_match_data(&pdev->dev); if (!cdata) { @@ -865,9 +906,35 @@ static int tegra_adma_probe(struct platform_device *pd= ev) tdma->nr_channels =3D cdata->nr_channels; platform_set_drvdata(pdev, tdma); =20 - tdma->base_addr =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(tdma->base_addr)) - return PTR_ERR(tdma->base_addr); + res_page =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "page"); + if (res_page) { + tdma->ch_base_addr =3D devm_ioremap_resource(&pdev->dev, res_page); + if (IS_ERR(tdma->ch_base_addr)) + return PTR_ERR(tdma->ch_base_addr); + + res_base =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "global"= ); + if (res_base) { + page_no =3D (res_page->start - res_base->start) / cdata->ch_base_offset; + if (page_no <=3D 0) + return -EINVAL; + tdma->ch_page_no =3D page_no - 1; + tdma->base_addr =3D devm_ioremap_resource(&pdev->dev, res_base); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + } + } else { + /* If no 'page' property found, then reg DT binding would be legacy */ + res_base =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_base) { + tdma->base_addr =3D devm_ioremap_resource(&pdev->dev, res_base); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + } else { + return -ENODEV; + } + + tdma->ch_base_addr =3D tdma->base_addr + cdata->ch_base_offset; + } =20 tdma->ahub_clk =3D devm_clk_get(&pdev->dev, "d_audio"); if (IS_ERR(tdma->ahub_clk)) { @@ -900,8 +967,7 @@ static int tegra_adma_probe(struct platform_device *pde= v) if (!test_bit(i, tdma->dma_chan_mask)) continue; =20 - tdc->chan_addr =3D tdma->base_addr + cdata->ch_base_offset - + (cdata->ch_reg_size * i); + tdc->chan_addr =3D tdma->ch_base_addr + (cdata->ch_reg_size * i); =20 tdc->irq =3D of_irq_get(pdev->dev.of_node, i); if (tdc->irq <=3D 0) { --=20 2.25.1