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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241213-dev-maxh-svukte-v4-v4-2-92762c67f743@sifive.com> References: <20241213-dev-maxh-svukte-v4-v4-0-92762c67f743@sifive.com> In-Reply-To: <20241213-dev-maxh-svukte-v4-v4-0-92762c67f743@sifive.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Max Hsu , Samuel Holland , Deepak Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3057; i=max.hsu@sifive.com; h=from:subject:message-id; bh=LdPuysx21Ofb0xvFzV8QxmW+nt/zKZ5xS3FFhbJOK4c=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBnXBt3eMXow98+LeyNOGLt9sRJUeftUptMMHTfr LOMd2baOgWJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCZ1wbdwAKCRDSA/2dB3lA vaLCC/96w2hpgaZxW2gTD9xyx+m6UFTOHkHPCwOB9gPWzgxY2+SUx/wcYgE/0qnki6dxvO1o6+N a/HfwfIcN+EIHHdaN7OYoZvY0uvVQ/DCw0dH41jsZwrYVsQ3KxwlVEsAFx4LJwxQrNy8LdY60dJ JxZEVae+hLwZeVx/SUSvJzOaJ4L27NOpqHYHY65QgH7ZIKK9GA1ZygKrV1g/kKvSmfzH3Ad56xm JW7gvRfQrEpDAxOlc1vr2GwzlrbbrrfWgli5HiqmnFqVQZ6SyodaYuY6N+TDzBm/Knwy8HtrvRP QU2/h4B2NbuNNfAsfVFFo/oySwbEsxhnRR7oYGmSWgNt6eDsGZVZiW9y7XGlv5pNhpHDsYvGqNA e7GIv9NuLmxirqBSseZQ+C9Yd7W4q2oSdG/LNp9IEmI1zoGDGRB/TZByvI+6Kj6iww3XACvuVc6 NeyaIAIonLUhLS4GCs9hP0CITzjlY4DKMbut0ZR/t+ZgzDaGKMhdbgQ1KVicEZ4VP+6Jo= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Svukte extension introduce senvcfg.UKTE, hstatus.HUKTE. This patch add CSR bit definition, and detects if Svukte ISA extension is available, cpufeature will set the correspond bit field so the svukte-qualified memory accesses are protected in a manner that is timing-independent of the faulting virtual address. Since hstatus.HU is not enabled by linux, enabling hstatus.HUKTE will not be affective. Reviewed-by: Samuel Holland Reviewed-by: Deepak Gupta Signed-off-by: Max Hsu --- arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 37bdea65bbd8a1a313cc7ba00b80fc5071b9809a..aeb62e9901452f8ded56961ab31= dabbb2fd22cc6 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -126,6 +126,7 @@ #define HSTATUS_VSXL _AC(0x300000000, UL) #define HSTATUS_VSXL_SHIFT 32 #endif +#define HSTATUS_HUKTE _AC(0x01000000, UL) #define HSTATUS_VTSR _AC(0x00400000, UL) #define HSTATUS_VTW _AC(0x00200000, UL) #define HSTATUS_VTVM _AC(0x00100000, UL) @@ -204,6 +205,7 @@ #define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32) #define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32) #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) +#define ENVCFG_UKTE (_AC(1, UL) << 8) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 869da082252a460559c9beea3829cc90860d6e9a..811c34d64df88dff116abb52e05= 054715a474dc5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -100,6 +100,7 @@ #define RISCV_ISA_EXT_ZICCRSE 91 #define RISCV_ISA_EXT_SVADE 92 #define RISCV_ISA_EXT_SVADU 93 +#define RISCV_ISA_EXT_SVUKTE 94 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c20e2e2f6354a3a4be1f4437f7f564..932774350de42ec9b66fd7d00ef= b478ad55856f4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -402,6 +402,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_SUPERSET(svukte, RISCV_ISA_EXT_SVUKTE, riscv_xlinuxenvcfg= _exts), __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), }; =20 @@ -944,6 +945,10 @@ void __init riscv_user_isa_enable(void) current->thread.envcfg |=3D ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn("Zicboz disabled as it is unavailable on some harts\n"); + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVUKTE)) + current->thread.envcfg |=3D ENVCFG_UKTE; + } =20 #ifdef CONFIG_RISCV_ALTERNATIVE --=20 2.43.2