From nobody Wed Dec 17 14:34:42 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 11C04239BC3; Thu, 12 Dec 2024 15:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734019098; cv=none; b=fp47clWHJsyFuWfCPUvTEOkxyS4FJzm1CFywVaxN7xz/T2Yi5hmvmRJ3PMavLSTrai2AlbYcqwbWRfTJpnfMtqO2vwo2dRRbioFsJYQRM/KzI5q9EUX6nRhkMVwL4PxpHew3merg0+yGHhzhnHZNy4BuaYHu9AjB1gqI5MCiy74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734019098; c=relaxed/simple; bh=bHJw24O/r1us2R+45Y8hZKLQ+BOX2H7xJ7Z4tDBwpGI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RxQylRNUT0olvNbEpQ6VZxTc5Qp6zrpcRtcZYehCFPk7lSqLMBa93VVmPYMAvkSGaaOUjavGzAto7ASygE5khePdOGX5IJl8bQ89Rva7URDcbdEPpxzphP1sW5dL+ldYfTMrtyVety3N/p1TEeI8AJirGFD3/VszrLwh6cyp7A8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF562176C; Thu, 12 Dec 2024 07:58:44 -0800 (PST) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.39.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 59FE93F720; Thu, 12 Dec 2024 07:58:13 -0800 (PST) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Joey Gouly , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Steven Price Subject: [PATCH v6 26/43] arm64: rme: allow userspace to inject aborts Date: Thu, 12 Dec 2024 15:55:51 +0000 Message-ID: <20241212155610.76522-27-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241212155610.76522-1-steven.price@arm.com> References: <20241212155610.76522-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Joey Gouly Extend KVM_SET_VCPU_EVENTS to support realms, where KVM cannot set the system registers, and the RMM must perform it on next REC entry. Signed-off-by: Joey Gouly Signed-off-by: Steven Price --- Documentation/virt/kvm/api.rst | 2 ++ arch/arm64/kvm/guest.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index df4679415a4c..1c622d8ca602 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -1291,6 +1291,8 @@ User space may need to inject several types of events= to the guest. Set the pending SError exception state for this VCPU. It is not possible to 'cancel' an Serror that has been made pending. =20 +User space cannot inject SErrors into Realms. + If the guest performed an access to I/O memory which could not be handled = by userspace, for example because of missing instruction syndrome decode information or because there is no device mapped at the accessed IPA, then diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 1ee2fe072f1a..920e0fd73698 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -883,6 +883,30 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, bool has_esr =3D events->exception.serror_has_esr; bool ext_dabt_pending =3D events->exception.ext_dabt_pending; =20 + if (vcpu_is_rec(vcpu)) { + /* Cannot inject SError into a Realm. */ + if (serror_pending) + return -EINVAL; + + /* + * If a data abort is pending, set the flag and let the RMM + * inject an SEA when the REC is scheduled to be run. + */ + if (ext_dabt_pending) { + /* + * Can only inject SEA into a Realm if the previous exit + * was due to a data abort of an Unprotected IPA. + */ + if (!(vcpu->arch.rec.run->enter.flags & REC_ENTER_EMULATED_MMIO)) + return -EINVAL; + + vcpu->arch.rec.run->enter.flags &=3D ~REC_ENTER_EMULATED_MMIO; + vcpu->arch.rec.run->enter.flags |=3D REC_ENTER_INJECT_SEA; + } + + return 0; + } + if (serror_pending && has_esr) { if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) return -EINVAL; --=20 2.43.0