From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99D2421C166; Thu, 12 Dec 2024 15:52:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018776; cv=none; b=sIpbYhcjPA9P0tGpdTm5fBRUCF8xP3jhRtJCRqa7nbSYN0P7HcKITgA+ZrZanDhe7nQRXjobFhkkmblp9ktgki2xmz5Y8oQAnVaQ8cTLutCRD7bjyRcTCHp30kG1KZZsG160eHymEmkoj3ejp1jKuNicWoMWCyeHpYp1xZ7sZXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018776; c=relaxed/simple; bh=7Zu2EmcYCI0XQSBGGUbmMJBu6athO5pveyyQaC9mnoE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gc7woUg+Ildjtc3Il0kEDdg7zaTNsVdAPKtprUJnwZ5igJi2LgYO0Z8Wdz7tOY4vXrSyp6GgJzRXOrNm0NnnE8taPuKi3KQdic3PM5rNqOmEuu1yuIEceBukycNALF1lfHXKbxEnAn4Io5vy7gZDtGelIANZufZnaCFml+QM0bY= ARC-Authentication-Results: i=1; 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charset="utf-8" Signed-off-by: Kevin Chen --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 2f92b8ab08fa..600424929df9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -8,6 +8,7 @@ title: Aspeed SoC based boards =20 maintainers: - Joel Stanley + - Kevin Chen =20 properties: $nodename: @@ -101,4 +102,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 =20 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true --=20 2.34.1 From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13796221DA0; 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dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 12 Dec 2024 23:52:41 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 12 Dec 2024 23:52:41 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage. Date: Thu, 12 Dec 2024 23:52:31 +0800 Message-ID: <20241212155237.848336-3-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 1. Because size-cells is no need to use 2, modify to 1 for use. 2. Add minItems to 1 for interrupts for intc1. 3. Add 1 interrupt of intc1 example into yaml file. 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1. --- .../aspeed,ast2700-intc.yaml | 60 +++++++++++++++---- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..eadfbc45326b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -31,6 +31,7 @@ properties: type as defined in interrupt.txt in this directory. =20 interrupts: + minItems: 1 maxItems: 6 description: | Depend to which INTC0 or INTC1 used. @@ -68,19 +69,52 @@ examples: #include =20 bus { + #address-cells =3D <2>; + #size-cells =3D <1>; + + intc0: interrupt-controller@12100000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x12100000 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x4000>; #address-cells =3D <2>; - #size-cells =3D <2>; - - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <2>; - interrupt-controller; - interrupts =3D , - , - , - , - , - ; + #size-cells =3D <1>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0 0x12101b00 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; }; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x14c18000 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x400>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + intc1_4: interrupt-controller@140 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x140 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | I= RQ_TYPE_LEVEL_HIGH)>; + }; + }; + + uart12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x100>; 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Thu, 12 Dec 2024 23:52:41 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/6] dt-bindings: arm: aspeed: Add ASPEED AST27XX SoC Date: Thu, 12 Dec 2024 23:52:32 +0800 Message-ID: <20241212155237.848336-4-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Kevin Chen --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 2f92b8ab08fa..20191fee1f5b 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -101,4 +101,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 =20 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true --=20 2.34.1 From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AA6222330F; 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dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 12 Dec 2024 23:52:41 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 12 Dec 2024 23:52:41 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/6] dt-bindings: interrupt-controller: Fix the size-cells in ast2700-intc Date: Thu, 12 Dec 2024 23:52:33 +0800 Message-ID: <20241212155237.848336-5-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is no need to let size-cells to 2 for the ASPEED AST27XX INTC. Modify the ast2700-intc example usage. Signed-off-by: Kevin Chen --- .../bindings/interrupt-controller/aspeed,ast2700-intc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..69503aa638fb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -69,11 +69,11 @@ examples: =20 bus { #address-cells =3D <2>; - #size-cells =3D <2>; + #size-cells =3D <1>; =20 interrupt-controller@12101b00 { compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; + reg =3D <0 0x12101b00 0x10>; #interrupt-cells =3D <2>; interrupt-controller; interrupts =3D , --=20 2.34.1 From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC9E3223C40; Thu, 12 Dec 2024 15:53:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018784; cv=none; b=WF1qr1JNXX45nLRuxUBZ7fHH8hf+fW77Fj1KPGA6ZDLWBmxfgLpSecGQpt9lDztWXlWBClrmaFot8Yux0Tn+5XRVoyzap9dv/kwlqxIcPSYtFgletD1pFSlY+Pk/h4fn2iYfefbYWMz2wbSL/7QpMEAZE1YZm0v1Ak2ORm1NfIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018784; c=relaxed/simple; bh=PDBcMGSgHlDtMAyhCoGHt+7oogWqv9VrcXPppWF3K0Y=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vCuIM7MiFQKjfHB+KUEpKXnm6n8jvfyayfVAZob/a9OTngkVjdgDnfu1uPhu4wewKKi2x1sSbz/Fqsna60Xde0zO9YvhL8kFcNS0eDnM9MUbd/h5cdOAjdYqIy7GHCXHJPDa/b/FwuZrbJpZdZiJ4TArkDJ064zhLvQsiITbPbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 12 Dec 2024 23:52:41 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 12 Dec 2024 23:52:41 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 3/6] arm64: aspeed: Add support for ASPEED AST27XX BMC SoC Date: Thu, 12 Dec 2024 23:52:34 +0800 Message-ID: <20241212155237.848336-6-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ARCH_ASPEED in current arm64 architecture. Signed-off-by: Kevin Chen --- MAINTAINERS | 1 + arch/arm64/Kconfig.platforms | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 17daa9ee9384..c6d04cea43d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2261,6 +2261,7 @@ Q: https://patchwork.ozlabs.org/project/linux-aspeed/= list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git F: Documentation/devicetree/bindings/arm/aspeed/ F: arch/arm/boot/dts/aspeed/ +F: arch/arm64/boot/dts/aspeed/ F: arch/arm/mach-aspeed/ N: aspeed =20 diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 370a9d2b6919..894b80434776 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,12 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. =20 +config ARCH_ASPEED + bool "Aspeed SoC family" + help + Say yes if you intend to run on an Aspeed ast2700 or similar + seventh generation Aspeed BMCs. + menuconfig ARCH_BCM bool "Broadcom SoC Support" =20 --=20 2.34.1 From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF63F223C6A; Thu, 12 Dec 2024 15:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018786; cv=none; b=ViJr/kNu5sirT0c1/HVGMM2aUYPt2osCzwppBtAcLx3mmO+m3nrsjfaVXapBXZwrYsSdppEMrz/79hajXnVotBEmo9QeSp1E2/J4HRvlkrzNekowMATAlsCvdMVvOXb9zUfFdtdtmTGyRiCr+K0xSo4135hIOxY2EQ9AMAfJG6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018786; c=relaxed/simple; bh=KuQ8PAcDGsjyoshMSkZQUSMVcSegeVk46GL1zQMRlks=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VTabazJy2VIOUp+io4ToKgJRE8kZkL9Yts/fuVAg9qyFbuojZ5SlRnJTtVAybUgnwJgNJPan3hDO3q5jTTO3a6zDRlcTQCU8DH0zmAQRjGjYrDUJhYc+aExa30vBmi4Gj/3rde98+Rgh++tuSLm9CBQHWGnFqMHCFFZur9C0WJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 12 Dec 2024 23:52:42 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 12 Dec 2024 23:52:42 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 4/6] arm64: dts: aspeed: Add initial AST27XX device tree Date: Thu, 12 Dec 2024 23:52:35 +0800 Message-ID: <20241212155237.848336-7-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add aspeed-g7.dtsi to be AST27XX device tree. Signed-off-by: Kevin Chen --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 236 ++++++++++++++++++++++ 2 files changed, 237 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 21cd3a87f385..6a590a66e1a9 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D amlogic subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm +subdir-y +=3D aspeed subdir-y +=3D bitmain subdir-y +=3D broadcom subdir-y +=3D cavium diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dt= s/aspeed/aspeed-g7.dtsi new file mode 100644 index 000000000000..3f1e801dec4c --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include + +/ { + compatible =3D "aspeed,ast2700"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + enable-method =3D "psci"; + reg =3D <0x0 0x1>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + enable-method =3D "psci"; + reg =3D <0x0 0x2>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + enable-method =3D "psci"; + reg =3D <0x0 0x3>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a35-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + soc0: soc@10000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0x10000000 0x10000000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + syscon0: syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg =3D <0x0 0x12c02000 0x1000>; + ranges =3D <0x0 0x0 0 0x12c02000 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + intc0: interrupt-controller@12100000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x12100000 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x1b00 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; + }; + }; + + gic: interrupt-controller@12200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x12200000 0x10000>, /* GICD */ + <0 0x12280000 0x80000>, /* GICR */ + <0 0x40440000 0x1000>; /* GICC */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + interrupt-parent =3D <&gic>; + }; + }; + + soc1: soc@14000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0x14000000 0x10000000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + syscon1: syscon@14c02000 { + compatible =3D "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg =3D <0x0 0x14c02000 0x1000>; + ranges =3D <0x0 0x0 0x0 0x14c02000 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x14c18000 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x400>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x100 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYP= E_LEVEL_HIGH)>; + }; + + intc1_1: interrupt-controller@110 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x110 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYP= E_LEVEL_HIGH)>; + }; + + intc1_2: interrupt-controller@120 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x120 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYP= E_LEVEL_HIGH)>; + }; + + intc1_3: interrupt-controller@130 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x130 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYP= E_LEVEL_HIGH)>; + }; + + intc1_4: interrupt-controller@140 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x140 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYP= E_LEVEL_HIGH)>; + }; + + intc1_5: interrupt-controller@150 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x150 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 5 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYP= E_LEVEL_HIGH)>; + }; + }; + + uart12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x100>; + interrupts-extended =3D <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE= _LEVEL_HIGH)>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART12CLK>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + no-loopback-test; + }; + }; +}; --=20 2.34.1 From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3E0E223E75; Thu, 12 Dec 2024 15:53:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018789; cv=none; b=ekPvpKWWjj4L7CgAeQVPhKQMH7C0rOzVpbiORkiYVGL0R4JvA/X+NW1iEr0D8TTz6s74W+q4YjzoUKK4tOOosQpQ5iaDns5a67Sx1slP5ow7jW5DbH20nfOrBcXbPjN1wNT3/1EIValE9zqkFbIGYsKjq0PEvr3OgM7tjtZIXNY= ARC-Message-Signature: i=1; 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Thu, 12 Dec 2024 23:52:42 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 5/6] arm64: dts: aspeed: Add initial AST2700 EVB device tree Date: Thu, 12 Dec 2024 23:52:36 +0800 Message-ID: <20241212155237.848336-8-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add EVB board of AST2700 in ASPEED Architecture. Signed-off-by: Kevin Chen --- arch/arm64/boot/dts/aspeed/Makefile | 4 ++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 57 ++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspe= ed/Makefile new file mode 100644 index 000000000000..ffe7e15017cc --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ASPEED) +=3D \ + ast2700-evb.dtb diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/d= ts/aspeed/ast2700-evb.dts new file mode 100644 index 000000000000..6dad88c98ce0 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; + +#include "aspeed-g7.dtsi" +#include + +/ { + model =3D "AST2700A1-EVB"; + compatible =3D "aspeed,ast2700-evb", "aspeed,ast2700"; + + aliases { + serial12 =3D &uart12; + }; + + chosen { + bootargs =3D "console=3DttyS12,115200n8"; + stdout-path =3D &uart12; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + mcu_fw: mcu-firmware@42fe00000 { + reg =3D <0x4 0x2fe00000 0x200000>; + no-map; + }; + + atf: trusted-firmware-a@430000000 { + reg =3D <0x4 0x30000000 0x80000>; + no-map; + }; + + optee_core: optee_core@430080000 { + reg =3D <0x4 0x30080000 0x1000000>; + no-map; + }; + }; +}; + +&uart12 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Wed Dec 17 12:46:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FE9E223E9C; Thu, 12 Dec 2024 15:53:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018790; cv=none; b=d8vqGmqFOi9YSzGvHgrITylU4TAj3VUrDoD/s29sguR5Vqenn2PysK/irfWaEKuNvS7/xQ/70CPi2J5AW05Za5KJWYKuOX6Lf8ZPyP6IIESdcqOyMud/2uk/ZY6972PHKcMJhxbzCz1PHu008EzpEAFatJd2nYlHyISGhL3PK0E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018790; c=relaxed/simple; bh=sCfwn1vl381W37kWDW29ndnhO/jyYxada+x67UTn2z4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ChahpGUUU7x6q/oFt14humjCYvtiWV621iCM8KIDcjh1aYuLc72URQ8VOBqfgppJeCL+VLFDy155mBXHzj4uuiPuk4oTaYbEYmkRvyS96IT4101Ihm7VnN7rnegGf53mwUBWUWKdywy5dFl8HMmq9KHXxtk5tME399i3UzP5U90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 12 Dec 2024 23:52:42 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 12 Dec 2024 23:52:42 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 6/6] arm64: defconfig: Add ASPEED AST2700 family support Date: Thu, 12 Dec 2024 23:52:37 +0800 Message-ID: <20241212155237.848336-9-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable CONFIG_ARCH_ASPEED in arm64 defconfig. Signed-off-by: Kevin Chen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c62831e61586..8826068c7c1d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy +CONFIG_ARCH_ASPEED=3Dy CONFIG_ARCH_BCM=3Dy CONFIG_ARCH_BCM2835=3Dy CONFIG_ARCH_BCM_IPROC=3Dy --=20 2.34.1