From nobody Sun Dec 14 12:18:00 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5EBB20E327; Thu, 12 Dec 2024 09:01:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733994069; cv=none; b=Dmzsjvb/CkOB39ctdfT1hpOFDdBNXmxgaZ3JLDxckU/jm1LrsCIcJPZ9ZVz4yhcv1UhCKa6NSkhuThpkYBm+/7EpoIH16PsdjeTk6jaTi91TriRFvWWP42dekVKaG3woHOoP4YNtthcX5Rcy2rMh2mfwZnAPD2EHw9lX96fU/AQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733994069; c=relaxed/simple; bh=qT+U3Mo0Dkiypc+kNwjgrU+9E4Two+7GYNm6H7GQHAI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eWei1pWbD126BGTcsgx5KwZ29Hlox5vW3iCuCCQ3I8W6jZYzLvO4QasmhLz+5G62YHrmhlMAJX4kIm8B7Qi0g+l9S3XhR5L7OfvVcOrNCnXQH9+uLmsE/ZeT/K2SzOFGGXpCNbsTgHCWUQOwWri7CeKtFvt4p7NWOUTR8870dcQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=hcgm2wZQ; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="hcgm2wZQ" X-UUID: 9a78f9aab86711efbd192953cf12861f-20241212 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CgQXnLuYZP9qq+qDcEvs7smqNEhL8gzcKfKL9qKTQmU=; b=hcgm2wZQ8mLwNq5F2EANfnyzXt3Lp52aOQnFOnNbWYv+OthErvm/HVUuy22YYm3HdeGq3M46NIIrIbnATDJUnsk6nzv/k8d5w4H206hoAZoy+FfElhOsLHp/Gu0JTs4p5P3jQ8lwZ/8N6RNrDF0N+GPOrG/Le2GZK3v/hAnttVQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.45,REQID:71c9f99d-7b28-443e-8228-5e2614af478b,IP:0,U RL:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-50 X-CID-META: VersionHash:6493067,CLOUDID:da15db3b-e809-4df3-83cd-88f012b9e9ba,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0,EDM:1,IP: nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,L ES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 9a78f9aab86711efbd192953cf12861f-20241212 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1939231980; Thu, 12 Dec 2024 17:00:58 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 12 Dec 2024 17:00:57 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 12 Dec 2024 17:00:56 +0800 From: Crystal Guo To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Crystal Guo CC: , , , , Subject: [PATCH 1/2] memory/mediatek: Add an interface to get current DDR data rate Date: Thu, 12 Dec 2024 16:59:47 +0800 Message-ID: <20241212090029.13692-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241212090029.13692-1-crystal.guo@mediatek.com> References: <20241212090029.13692-1-crystal.guo@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add MediaTek DRAMC driver to provide an interface that can obtain current DDR data rate. Signed-off-by: Crystal Guo --- drivers/memory/Kconfig | 1 + drivers/memory/Makefile | 1 + drivers/memory/mediatek/Kconfig | 21 ++ drivers/memory/mediatek/Makefile | 2 + drivers/memory/mediatek/mtk-dramc.c | 325 +++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-dramc.h | 41 ++++ 6 files changed, 391 insertions(+) create mode 100644 drivers/memory/mediatek/Kconfig create mode 100644 drivers/memory/mediatek/Makefile create mode 100644 drivers/memory/mediatek/mtk-dramc.c create mode 100644 include/linux/soc/mediatek/mtk-dramc.h diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index c82d8d8a16ea..b1698549ff81 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -227,5 +227,6 @@ config STM32_FMC2_EBI =20 source "drivers/memory/samsung/Kconfig" source "drivers/memory/tegra/Kconfig" +source "drivers/memory/mediatek/Kconfig" =20 endif diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index d2e6ca9abbe0..cf1091449d2e 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_STM32_FMC2_EBI) +=3D stm32-fmc2-ebi.o =20 obj-$(CONFIG_SAMSUNG_MC) +=3D samsung/ obj-$(CONFIG_TEGRA_MC) +=3D tegra/ +obj-$(CONFIG_HAVE_MTK_MC) +=3D mediatek/ obj-$(CONFIG_TI_EMIF_SRAM) +=3D ti-emif-sram.o obj-$(CONFIG_FPGA_DFL_EMIF) +=3D dfl-emif.o =20 diff --git a/drivers/memory/mediatek/Kconfig b/drivers/memory/mediatek/Kcon= fig new file mode 100644 index 000000000000..00764cdb157e --- /dev/null +++ b/drivers/memory/mediatek/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +config HAVE_MTK_MC + bool "MediaTek Memory Controller support" + help + This option allows to enable MediaTek memory controller drivers, + which may include controllers for DRAM or others. + Select Y here if you need support for MediaTek memory controller. + If you don't need, select N. + +if HAVE_MTK_MC + +config MTK_DRAMC + tristate "MediaTek DRAMC driver" + depends on HAVE_MTK_MC + help + This option selects the MediaTek DRAMC driver, which provides + an interface for reporting the current data rate of DRAM. + Select Y here if you need support for the MediaTek DRAMC driver. + If you don't need, select N. + +endif diff --git a/drivers/memory/mediatek/Makefile b/drivers/memory/mediatek/Mak= efile new file mode 100644 index 000000000000..a1395fc55b41 --- /dev/null +++ b/drivers/memory/mediatek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_MTK_DRAMC) +=3D mtk-dramc.o diff --git a/drivers/memory/mediatek/mtk-dramc.c b/drivers/memory/mediatek/= mtk-dramc.c new file mode 100644 index 000000000000..9c2c8e187a4a --- /dev/null +++ b/drivers/memory/mediatek/mtk-dramc.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct platform_device *dramc_pdev; +static struct platform_driver dramc_drv; + +static int fmeter_init(struct platform_device *pdev, + struct fmeter_dev_t *fmeter_dev_ptr, unsigned int fmeter_version) +{ + struct device_node *dramc_node =3D pdev->dev.of_node; + int ret; + + ret =3D of_property_read_u32(dramc_node, + "crystal-freq", &(fmeter_dev_ptr->crystal_freq)); + ret |=3D of_property_read_u32(dramc_node, + "shu-of", &(fmeter_dev_ptr->shu_of)); + ret |=3D of_property_read_u32_array(dramc_node, + "shu-lv", (unsigned int *)&(fmeter_dev_ptr->shu_lv), 3); + ret |=3D of_property_read_u32_array(dramc_node, + "pll-id", (unsigned int *)&(fmeter_dev_ptr->pll_id), 3); + ret |=3D of_property_read_u32_array(dramc_node, + "sdmpcw", (unsigned int *)(fmeter_dev_ptr->sdmpcw), 6); + ret |=3D of_property_read_u32_array(dramc_node, + "posdiv", (unsigned int *)(fmeter_dev_ptr->posdiv), 6); + ret |=3D of_property_read_u32_array(dramc_node, + "fbksel", (unsigned int *)(fmeter_dev_ptr->fbksel), 6); + ret |=3D of_property_read_u32_array(dramc_node, + "dqsopen", (unsigned int *)(fmeter_dev_ptr->dqsopen), 6); + if (fmeter_version =3D=3D 1) { + fmeter_dev_ptr->version =3D 1; + ret |=3D of_property_read_u32_array(dramc_node, + "async-ca", (unsigned int *)(fmeter_dev_ptr->async_ca), 6); + ret |=3D of_property_read_u32_array(dramc_node, + "dq-ser-mode", (unsigned int *)(fmeter_dev_ptr->dq_ser_mode), 6); + } + return ret; +} + +static ssize_t dram_data_rate_show(struct device_driver *driver, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "DRAM data rate =3D %d\n", + mtk_dramc_get_data_rate()); +} + +static DRIVER_ATTR_RO(dram_data_rate); + +static int dramc_probe(struct platform_device *pdev) +{ + struct device_node *dramc_node =3D pdev->dev.of_node; + struct dramc_dev_t *dramc_dev_ptr; + unsigned int fmeter_version; + struct resource *res; + unsigned int i, size; + int ret; + + pr_info("%s: module probe.\n", __func__); + dramc_pdev =3D pdev; + dramc_dev_ptr =3D devm_kmalloc(&pdev->dev, + sizeof(struct dramc_dev_t), GFP_KERNEL); + + if (!dramc_dev_ptr) + return -ENOMEM; + + ret =3D of_property_read_u32(dramc_node, + "support-ch-cnt", &dramc_dev_ptr->support_ch_cnt); + if (ret) { + pr_info("%s: get support_ch_cnt fail\n", __func__); + return -EINVAL; + } + + dramc_dev_ptr->sleep_base =3D of_iomap(dramc_node, + dramc_dev_ptr->support_ch_cnt * 4); + if (IS_ERR(dramc_dev_ptr->sleep_base)) { + pr_info("%s: unable to map sleep base\n", __func__); + return -EINVAL; + } + + size =3D sizeof(phys_addr_t) * dramc_dev_ptr->support_ch_cnt; + dramc_dev_ptr->dramc_chn_base_ao =3D devm_kmalloc(&pdev->dev, + size, GFP_KERNEL); + if (!(dramc_dev_ptr->dramc_chn_base_ao)) + return -ENOMEM; + dramc_dev_ptr->dramc_chn_base_nao =3D devm_kmalloc(&pdev->dev, + size, GFP_KERNEL); + if (!(dramc_dev_ptr->dramc_chn_base_nao)) + return -ENOMEM; + dramc_dev_ptr->ddrphy_chn_base_ao =3D devm_kmalloc(&pdev->dev, + size, GFP_KERNEL); + if (!(dramc_dev_ptr->ddrphy_chn_base_ao)) + return -ENOMEM; + dramc_dev_ptr->ddrphy_chn_base_nao =3D devm_kmalloc(&pdev->dev, + size, GFP_KERNEL); + if (!(dramc_dev_ptr->ddrphy_chn_base_nao)) + return -ENOMEM; + + for (i =3D 0; i < dramc_dev_ptr->support_ch_cnt; i++) { + res =3D platform_get_resource(pdev, IORESOURCE_MEM, i); + dramc_dev_ptr->dramc_chn_base_ao[i] =3D + devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dramc_dev_ptr->dramc_chn_base_ao[i])) { + pr_info("%s: unable to map ch%d DRAMC AO base\n", + __func__, i); + return -EINVAL; + } + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, + i + dramc_dev_ptr->support_ch_cnt); + dramc_dev_ptr->dramc_chn_base_nao[i] =3D + devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dramc_dev_ptr->dramc_chn_base_nao[i])) { + pr_info("%s: unable to map ch%d DRAMC NAO base\n", + __func__, i); + return -EINVAL; + } + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, + i + dramc_dev_ptr->support_ch_cnt * 2); + dramc_dev_ptr->ddrphy_chn_base_ao[i] =3D + devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dramc_dev_ptr->ddrphy_chn_base_ao[i])) { + pr_info("%s: unable to map ch%d DDRPHY AO base\n", + __func__, i); + return -EINVAL; + } + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, + i + dramc_dev_ptr->support_ch_cnt * 3); + dramc_dev_ptr->ddrphy_chn_base_nao[i] =3D + devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dramc_dev_ptr->ddrphy_chn_base_nao[i])) { + pr_info("%s: unable to map ch%d DDRPHY NAO base\n", + __func__, i); + return -EINVAL; + } + } + + ret =3D of_property_read_u32(dramc_node, "fmeter-version", &fmeter_versio= n); + if (ret) { + pr_info("%s: get fmeter_version fail\n", __func__); + return -EINVAL; + } + pr_info("%s: fmeter_version(%d)\n", __func__, fmeter_version); + + if (fmeter_version =3D=3D 1) { + dramc_dev_ptr->fmeter_dev_ptr =3D devm_kmalloc(&pdev->dev, + sizeof(struct fmeter_dev_t), + GFP_KERNEL); + if (!(dramc_dev_ptr->fmeter_dev_ptr)) { + pr_info("%s: memory alloc fail\n", __func__); + return -ENOMEM; + } + ret =3D fmeter_init(pdev, dramc_dev_ptr->fmeter_dev_ptr, fmeter_version); + if (ret) { + pr_info("%s: fmeter_init fail\n", __func__); + return -EINVAL; + } + } else { + dramc_dev_ptr->fmeter_dev_ptr =3D NULL; + } + ret =3D driver_create_file(pdev->dev.driver, &driver_attr_dram_data_rate); + if (ret) { + pr_info("%s: fail to create dram_data_rate sysfs\n", __func__); + return ret; + } + + platform_set_drvdata(pdev, dramc_dev_ptr); + pr_info("%s: DRAM data rate =3D %d\n", __func__, + mtk_dramc_get_data_rate()); + + return ret; +} + +static unsigned int fmeter_v1(struct dramc_dev_t *dramc_dev_ptr) +{ + struct fmeter_dev_t *fmeter_dev_ptr =3D + (struct fmeter_dev_t *)dramc_dev_ptr->fmeter_dev_ptr; + unsigned int shu_lv_val; + unsigned int pll_id_val; + unsigned int sdmpcw_val; + unsigned int posdiv_val; + unsigned int ckdiv4_val; + unsigned int offset; + unsigned int vco_freq; + unsigned int fbksel; + unsigned int dqsopen; + unsigned int async_ca; + unsigned int dq_ser_mode; + + shu_lv_val =3D (readl(dramc_dev_ptr->ddrphy_chn_base_ao[0] + + fmeter_dev_ptr->shu_lv.offset) & + fmeter_dev_ptr->shu_lv.mask) >> + fmeter_dev_ptr->shu_lv.shift; + + pll_id_val =3D (readl(dramc_dev_ptr->ddrphy_chn_base_ao[0] + + fmeter_dev_ptr->pll_id.offset) & + fmeter_dev_ptr->pll_id.mask) >> + fmeter_dev_ptr->pll_id.shift; + + offset =3D fmeter_dev_ptr->sdmpcw[pll_id_val].offset + + fmeter_dev_ptr->shu_of * shu_lv_val; + sdmpcw_val =3D (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] + offset) & + fmeter_dev_ptr->sdmpcw[pll_id_val].mask) >> + fmeter_dev_ptr->sdmpcw[pll_id_val].shift; + + offset =3D fmeter_dev_ptr->posdiv[pll_id_val].offset + + fmeter_dev_ptr->shu_of * shu_lv_val; + posdiv_val =3D (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] + offset) & + fmeter_dev_ptr->posdiv[pll_id_val].mask) >> + fmeter_dev_ptr->posdiv[pll_id_val].shift; + + offset =3D fmeter_dev_ptr->fbksel[pll_id_val].offset + + fmeter_dev_ptr->shu_of * shu_lv_val; + fbksel =3D (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] + offset) & + fmeter_dev_ptr->fbksel[pll_id_val].mask) >> + fmeter_dev_ptr->fbksel[pll_id_val].shift; + + offset =3D fmeter_dev_ptr->dqsopen[pll_id_val].offset + + fmeter_dev_ptr->shu_of * shu_lv_val; + dqsopen =3D (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] + offset) & + fmeter_dev_ptr->dqsopen[pll_id_val].mask) >> + fmeter_dev_ptr->dqsopen[pll_id_val].shift; + + offset =3D fmeter_dev_ptr->async_ca[pll_id_val].offset + + fmeter_dev_ptr->shu_of * shu_lv_val; + async_ca =3D (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] + offset) & + fmeter_dev_ptr->async_ca[pll_id_val].mask) >> + fmeter_dev_ptr->async_ca[pll_id_val].shift; + + offset =3D fmeter_dev_ptr->dq_ser_mode[pll_id_val].offset + + fmeter_dev_ptr->shu_of * shu_lv_val; + dq_ser_mode =3D (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] + offset) & + fmeter_dev_ptr->dq_ser_mode[pll_id_val].mask) >> + fmeter_dev_ptr->dq_ser_mode[pll_id_val].shift; + ckdiv4_val =3D (dq_ser_mode =3D=3D 1); // 1: DIV4, 2: DIV8, 3: DIV16 + + posdiv_val &=3D ~(0x4); + + vco_freq =3D ((fmeter_dev_ptr->crystal_freq) * + (sdmpcw_val >> 7)) >> posdiv_val >> 1 >> ckdiv4_val + << fbksel; + + if ((dqsopen =3D=3D 1) && (async_ca =3D=3D 1)) + vco_freq >>=3D 1; + + return vco_freq; +} + +/* + * mtk_dramc_get_data_rate - calculate DRAM data rate + * + * Returns DRAM data rate (MB/s) + */ +unsigned int mtk_dramc_get_data_rate(void) +{ + struct dramc_dev_t *dramc_dev_ptr; + struct fmeter_dev_t *fmeter_dev_ptr; + + if (!dramc_pdev) + return 0; + + dramc_dev_ptr =3D + (struct dramc_dev_t *)platform_get_drvdata(dramc_pdev); + + fmeter_dev_ptr =3D (struct fmeter_dev_t *)dramc_dev_ptr->fmeter_dev_ptr; + if (!fmeter_dev_ptr) + return 0; + + if (fmeter_dev_ptr->version =3D=3D 1) + return fmeter_v1(dramc_dev_ptr); + return 0; +} +EXPORT_SYMBOL(mtk_dramc_get_data_rate); + +static int dramc_remove(struct platform_device *pdev) +{ + dramc_pdev =3D NULL; + + return 0; +} + +static const struct of_device_id dramc_of_ids[] =3D { + {.compatible =3D "mediatek,common-dramc",}, + {} +}; + +static struct platform_driver dramc_drv =3D { + .probe =3D dramc_probe, + .remove =3D dramc_remove, + .driver =3D { + .name =3D "dramc_drv", + .owner =3D THIS_MODULE, + .of_match_table =3D dramc_of_ids, + }, +}; + +static int __init dramc_drv_init(void) +{ + int ret; + + ret =3D platform_driver_register(&dramc_drv); + if (ret) { + pr_info("%s: init fail, ret 0x%x\n", __func__, ret); + return ret; + } + + return ret; +} + +module_init(dramc_drv_init); + +MODULE_AUTHOR("Mediatek Corporation"); +MODULE_DESCRIPTION("MediaTek DRAMC Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/soc/mediatek/mtk-dramc.h b/include/linux/soc/med= iatek/mtk-dramc.h new file mode 100644 index 000000000000..95e7dbfe7d0e --- /dev/null +++ b/include/linux/soc/mediatek/mtk-dramc.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef __MTK_DRAMC_H__ +#define __MTK_DRAMC_H__ + +struct reg_ctrl_t { + unsigned int offset; + unsigned int mask; + unsigned int shift; +}; + +struct fmeter_dev_t { + unsigned int version; + unsigned int crystal_freq; + unsigned int shu_of; + struct reg_ctrl_t shu_lv; + struct reg_ctrl_t pll_id; + struct reg_ctrl_t sdmpcw[2]; + struct reg_ctrl_t posdiv[2]; + struct reg_ctrl_t fbksel[2]; + struct reg_ctrl_t dqsopen[2]; + struct reg_ctrl_t async_ca[2]; + struct reg_ctrl_t dq_ser_mode[2]; +}; + +struct dramc_dev_t { + unsigned int support_ch_cnt; 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Thu, 12 Dec 2024 17:01:00 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 12 Dec 2024 17:00:58 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 12 Dec 2024 17:00:58 +0800 From: Crystal Guo To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Crystal Guo CC: , , , , Subject: [PATCH 2/2] dt-bindings: memory-controllers: Add mediatek common-dramc dt-bindings Date: Thu, 12 Dec 2024 16:59:48 +0800 Message-ID: <20241212090029.13692-3-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241212090029.13692-1-crystal.guo@mediatek.com> References: <20241212090029.13692-1-crystal.guo@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add devicetree binding for mediatek common-dramc driver. The DRAM controller of MediaTek SoC provides an interface to get the current data rate of DRAM. Signed-off-by: Crystal Guo --- .../mediatek,common-dramc.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/me= diatek,common-dramc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= common-dramc.yaml b/Documentation/devicetree/bindings/memory-controllers/me= diatek,common-dramc.yaml new file mode 100644 index 000000000000..c9e608c7f183 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,common-= dramc.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) 2024 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,common-dram= c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Common DRAMC (DRAM Controller) + +maintainers: + - Crystal Guo + +description: | + The DRAM controller of MediaTek SoC provides an interface to + get the current data rate of DRAM. + +properties: + compatible: + const: mediatek,common-dramc + + reg: + minItems: 9 + items: + - description: DRAMC_AO_CHA_BASE + - description: DRAMC_AO_CHB_BASE + - description: DRAMC_AO_CHC_BASE + - description: DRAMC_AO_CHD_BASE + - description: DRAMC_NAO_CHA_BASE + - description: DRAMC_NAO_CHB_BASE + - description: DRAMC_NAO_CHC_BASE + - description: DRAMC_NAO_CHD_BASE + - description: DDRPHY_AO_CHA_BASE + - description: DDRPHY_AO_CHB_BASE + - description: DDRPHY_AO_CHC_BASE + - description: DDRPHY_AO_CHD_BASE + - description: DDRPHY_NAO_CHA_BASE + - description: DDRPHY_NAO_CHB_BASE + - description: DDRPHY_NAO_CHC_BASE + - description: DDRPHY_NAO_CHD_BASE + - description: SLEEP_BASE + + support-ch-cnt: + maxItems: 1 + + fmeter-version: + maxItems: 1 + description: + Fmeter version for calculating dram data rate + + crystal-freq: + maxItems: 1 + description: + Reference clock rate in MHz + + shu-of: + maxItems: 1 + + pll-id: true + shu-lv: true + sdmpcw: true + posdiv: true + fbksel: true + dqsopen: true + async-ca: true + dq-ser-mode: true + +required: + - compatible + - reg + - support-ch-cnt + - fmeter-version + - crystal-freq + - pll-id + - shu-lv + - shu-of + - sdmpcw + - posdiv + - fbksel + - dqsopen + - async-ca + - dq-ser-mode + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + dramc: dramc@10230000 { + compatible =3D "mediatek,common-dramc"; + reg =3D <0 0x10230000 0 0x2000>, /* DRAMC_AO_CHA_BASE */ + <0 0x10240000 0 0x2000>, /* DRAMC_AO_CHB_BASE */ + <0 0x10250000 0 0x2000>, /* DRAMC_AO_CHC_BASE */ + <0 0x10260000 0 0x2000>, /* DRAMC_AO_CHD_BASE */ + <0 0x10234000 0 0x1000>, /* DRAMC_NAO_CHA_BASE */ + <0 0x10244000 0 0x1000>, /* DRAMC_NAO_CHB_BASE */ + <0 0x10254000 0 0x1000>, /* DRAMC_NAO_CHC_BASE */ + <0 0x10264000 0 0x1000>, /* DRAMC_NAO_CHD_BASE */ + <0 0x10238000 0 0x2000>, /* DDRPHY_AO_CHA_BASE */ + <0 0x10248000 0 0x2000>, /* DDRPHY_AO_CHB_BASE */ + <0 0x10258000 0 0x2000>, /* DDRPHY_AO_CHC_BASE */ + <0 0x10268000 0 0x2000>, /* DDRPHY_AO_CHD_BASE */ + <0 0x10236000 0 0x2000>, /* DDRPHY_NAO_CHA_BASE */ + <0 0x10246000 0 0x2000>, /* DDRPHY_NAO_CHB_BASE */ + <0 0x10256000 0 0x2000>, /* DDRPHY_NAO_CHC_BASE */ + <0 0x10266000 0 0x2000>, /* DDRPHY_NAO_CHD_BASE */ + <0 0x10006000 0 0x1000>; /* SLEEP_BASE */ + support-ch-cnt =3D <4>; + fmeter-version =3D <1>; + crystal-freq =3D <26>; + pll-id =3D <0x0e98 0x02000000 25>; + shu-lv =3D <0x0e98 0x0000c000 14>; + shu-of =3D <0x700>; + sdmpcw =3D <0x0908 0x0007fff8 3>, + <0x0928 0x0007fff8 3>; + posdiv =3D <0x090c 0x00003800 11>, + <0x092c 0x00003800 11>; + fbksel =3D <0x0910 0x00000040 6>, + <0x0910 0x00000040 6>; + dqsopen =3D <0x0d94 0x04000000 26>, + <0x0d94 0x04000000 26>; + async-ca =3D <0x0d08 0x00000001 0>, + <0x0d08 0x00000001 0>; + dq-ser-mode =3D <0x0dc4 0x00000018 3>, + <0x0dc4 0x00000018 3>; + }; + }; --=20 2.18.0