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Wed, 11 Dec 2024 16:25:56 -0800 (PST) From: Alexey Klimov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, krzk+dt@kernel.org Cc: konradybcio@kernel.org, konrad.dybcio@oss.qualcomm.com, robh@kernel.org, conor+dt@kernel.org, srinivas.kandagatla@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 RESEND 2/2] clk: qcom: Add SM6115 LPASSCC Date: Thu, 12 Dec 2024 00:25:51 +0000 Message-ID: <20241212002551.2902954-3-alexey.klimov@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241212002551.2902954-1-alexey.klimov@linaro.org> References: <20241212002551.2902954-1-alexey.klimov@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Konrad Dybcio SM6115 (and its derivatives or similar SoCs) has an LPASS clock controller block which provides audio-related resets. Add the required code to support them. Cc: Konrad Dybcio Cc: Konrad Dybcio Cc: Srinivas Kandagatla Signed-off-by: Konrad Dybcio [alexey.klimov] fixed compilation errors after rebase, slightly changed the commit message Signed-off-by: Alexey Klimov --- drivers/clk/qcom/Kconfig | 9 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sm6115.c | 85 +++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sm6115.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ef89d686cbc4..b2b53e09cc33 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1230,6 +1230,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_LPASSCC_6115 + tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_6115 + help + Support for the LPASS clock controller on SM6115 devices. + Say Y if you want to toggle LPASS-adjacent resets within + this clock controller to reset the LPASS subsystem. + config SM_TCSRCC_8550 tristate "SM8550 TCSR Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b09dbdc210eb..cc435afcda37 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -154,6 +154,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o +obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) +=3D tcsrcc-sm8650.o obj-$(CONFIG_SM_VIDEOCC_7150) +=3D videocc-sm7150.o diff --git a/drivers/clk/qcom/lpasscc-sm6115.c b/drivers/clk/qcom/lpasscc-s= m6115.c new file mode 100644 index 000000000000..8ffdab71b948 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sm6115.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, 2023 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpass_audiocc_sm6115_resets[] =3D { + [LPASS_AUDIO_SWR_RX_CGCR] =3D { .reg =3D 0x98, .bit =3D 1, .udelay =3D 5= 00 }, +}; + +static struct regmap_config lpass_audiocc_sm6115_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .name =3D "lpass-audio-csr", + .max_register =3D 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_sm6115_reset_desc =3D { + .config =3D &lpass_audiocc_sm6115_regmap_config, + .resets =3D lpass_audiocc_sm6115_resets, + .num_resets =3D ARRAY_SIZE(lpass_audiocc_sm6115_resets), +}; + +static const struct qcom_reset_map lpasscc_sm6115_resets[] =3D { + [LPASS_SWR_TX_CONFIG_CGCR] =3D { .reg =3D 0x100, .bit =3D 1, .udelay =3D = 500 }, +}; + +static struct regmap_config lpasscc_sm6115_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .name =3D "lpass-tcsr", + .max_register =3D 0x1000, +}; + +static const struct qcom_cc_desc lpasscc_sm6115_reset_desc =3D { + .config =3D &lpasscc_sm6115_regmap_config, + .resets =3D lpasscc_sm6115_resets, + .num_resets =3D ARRAY_SIZE(lpasscc_sm6115_resets), +}; + +static const struct of_device_id lpasscc_sm6115_match_table[] =3D { + { + .compatible =3D "qcom,sm6115-lpassaudiocc", + .data =3D &lpass_audiocc_sm6115_reset_desc, + }, { + .compatible =3D "qcom,sm6115-lpasscc", + .data =3D &lpasscc_sm6115_reset_desc, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, lpasscc_sm6115_match_table); + +static int lpasscc_sm6115_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc =3D of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_sm6115_driver =3D { + .probe =3D lpasscc_sm6115_probe, + .driver =3D { + .name =3D "lpasscc-sm6115", + .of_match_table =3D lpasscc_sm6115_match_table, + }, +}; + +module_platform_driver(lpasscc_sm6115_driver); + +MODULE_DESCRIPTION("QTI LPASSCC SM6115 Driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2