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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org> References: <20241212-x1e80100-qcp-sdhc-v4-0-a74c48ee68a3@linaro.org> In-Reply-To: <20241212-x1e80100-qcp-sdhc-v4-0-a74c48ee68a3@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=4749; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=sIhmfEp6EiWv8csO0CuaF4kwgOWRRyIe0k01jMlrCDc=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnWxRmQ6u1rxFVhZtdOrF+LjRiF8NBF3DTNfeOX HH6tRECqyuJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZ1sUZgAKCRAbX0TJAJUV VjbFD/9UJ2SdMeBUGcbC3/7E5MkmE8dCQcpFkS4MavlMx/iS2StReAuYNwlnXBM770m6DPDCydH jxuFr0iWVnjpvRz5EtvXpHTdhR4UUY5x6lNmXjpw5/+vsgMuQhjOQPFK4lF2J41xC1vcM8zI4BN +y3YSj0pJuheV8rVHVc80aYYLvELZd7VdSeZLprlSfDetOSVMU5dfPTOQPaaqG99VQlFk0anW7L POsMV0nTxNfUbI6kbfQGvY4hui1IToIiKBxNEIqcXclG8jVud5KRyafwlpSCWPwL63DLPTMMxpb v6BGDyfTp9ZciLn2wKr+Y1cHM+KGxF0ehVaOPP644XulIQmFsNjltL32MJazMSVZuD3Bxi6V2n0 ISxa//MGbv/IEAghXp2qgPzT0aC68H5NjMHhSbDBMfRsPK2GhB+urAvuMzi5ARmtLQCSTpoPdHA 7CosmoeUrfzkfV63kL9PMEy3ynbCA3tdg0kaecamvL3T0NLyFVRoTOdSI/htmdkvLIGJjhP7Wtx 3hi81wK9KEzi53rYaY98drW8RIm22tOjHuB24V207OVjXw/qEp2iJDE8w7LbtOn56OcAHqbsadT PjFTk/MQKt24pFIh5HkD1CmNeTIHm7kL71zxOdUN7KeRO79ZVvvbEMq6WvJ6u+Id3oALk75FfA+ GbbTO136/Mj1oxA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The X Elite platform features two SDHC v5 controllers. Describe the controllers along with the pin configuration in TLMM for the SDC2, since they are hardwired and cannot be muxed to any other function. The SDC4 pin configuration can be muxed to different functions, so leave those to board specific dts. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 142 +++++++++++++++++++++++++++++= ++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..1584df66ea915230995f0cf662c= de813f4ae02a1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4094,6 +4094,108 @@ lpass_lpicx_noc: interconnect@7430000 { #interconnect-cells =3D <2>; }; =20 + sdhc_2: mmc@8804000 { + compatible =3D "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08804000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + iommus =3D <&apps_smmu 0x520 0>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + interconnects =3D <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + bus-width =3D <4>; + dma-coherent; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + sdhc_4: mmc@8844000 { + compatible =3D "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08844000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC4_AHB_CLK>, + <&gcc GCC_SDCC4_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + iommus =3D <&apps_smmu 0x160 0>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc4_opp_table>; + + interconnects =3D <&aggre2_noc MASTER_SDCC_4 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_4 0>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + bus-width =3D <4>; + dma-coherent; + + status =3D "disabled"; + + sdhc4_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_2_hsphy: phy@88e0000 { compatible =3D "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -5852,6 +5954,46 @@ rx-pins { bias-disable; }; }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; }; =20 apps_smmu: iommu@15000000 { --=20 2.34.1