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Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a36076e3c56b..6a2074297030 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie6a_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + status =3D "disabled"; }; =20 @@ -3115,6 +3119,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie5_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + status =3D "disabled"; }; =20 @@ -3235,6 +3241,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie4_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + status =3D "disabled"; =20 pcie4_port0: pcie@0 { --=20 2.34.1 From nobody Sun Dec 14 12:17:56 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D0942116E3 for ; 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a=ed25519-sha256; t=1733999565; l=4075; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=BTyoDXzoLq9s40NBa/pshroRWzYAGvXUT/nxju8J8D0=; b=nVg9cssNaQJ9+5SJTZAjsoxOtUvy8tYvhLTbHmdNdffFV9SKzEw+2nrOjQ1fRbr950FjIAWhj 4dQQDRCIdSKAtKZxhXpjwHYT0v12HBhDr+ihQ37E3gwobNfUZwM74jx X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: WiRAEaQvOOX3jRrYj2fBwpXXrd8aG4Ly X-Proofpoint-ORIG-GUID: WiRAEaQvOOX3jRrYj2fBwpXXrd8aG4Ly X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 mlxscore=0 clxscore=1011 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120074 From: Krishna chaitanya chundru PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 17 +++++++++++++++-- 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index dacea3fc5128..99e0e7ae12e9 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -826,3 +826,48 @@ u32 of_pci_get_slot_power_limit(struct device_node *no= de, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + char name[20]; + void **preset; + void *temp; + int ret; + + if (of_property_present(dev->of_node, "eq-presets-8gts")) { + presets->eq_presets_8gts =3D devm_kzalloc(dev, sizeof(u16) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_8gts) + return -ENOMEM; + + ret =3D of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + } + + for (int i =3D 1; i < sizeof(struct pci_eq_presets) / sizeof(void *); i++= ) { + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << i); + if (of_property_present(dev->of_node, name)) { + temp =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, GFP_KERNEL); + if (!temp) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, name, + temp, num_lanes); + if (ret) { + dev_err(dev, "Error %s %d\n", name, ret); + return ret; + } + + preset =3D (void **)((u8 *)presets + i * sizeof(void *)); + *preset =3D temp; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..82362d58bedc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -731,7 +731,12 @@ static inline u64 pci_rebar_size_to_bytes(int size) } =20 struct device_node; - +struct pci_eq_presets { + void *eq_presets_8gts; + void *eq_presets_16gts; + void *eq_presets_32gts; + void *eq_presets_64gts; +}; #ifdef CONFIG_OF int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 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Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..2cd0acbf9e18 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 + if (pci->num_lanes < 1) + pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 6d6cbc8b5b2c..acb2a963ae1a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -736,6 +736,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie = *pci) =20 } =20 +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u32 lnkcap; + u8 cap; + + cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { u32 lnkcap, lwsc, plc; @@ -1069,6 +1079,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { + int num_lanes =3D dw_pcie_link_get_max_link_width(pci); u32 val; =20 dw_pcie_link_set_max_speed(pci); @@ -1102,5 +1113,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |=3D PORT_LINK_DLL_LINK_EN; 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Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 2cd0acbf9e18..5f017b7ab932 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -694,10 +694,28 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus= *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); =20 +static int dw_pcie_host_start_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp =3D bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + + return dw_pcie_start_link(pci); +} + +static void dw_pcie_host_stop_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp =3D bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + + dw_pcie_stop_link(pci); +} + static struct pci_ops dw_pcie_ops =3D { .map_bus =3D dw_pcie_own_conf_map_bus, .read =3D pci_generic_config_read, .write =3D pci_generic_config_write, + .start_link =3D dw_pcie_host_start_link, + .stop_link =3D dw_pcie_host_stop_link, }; =20 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) --=20 2.34.1