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Thu, 12 Dec 2024 16:09:43 -0800 (PST) From: Atish Patra Date: Thu, 12 Dec 2024 16:09:32 -0800 Subject: [PATCH v2 1/3] drivers/perf: riscv: Fix Platform firmware event data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241212-pmu_event_fixes_v2-v2-1-813e8a4f5962@rivosinc.com> References: <20241212-pmu_event_fixes_v2-v2-0-813e8a4f5962@rivosinc.com> In-Reply-To: <20241212-pmu_event_fixes_v2-v2-0-813e8a4f5962@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Mayuresh Chitale , Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Platform firmware event data field is allowed to be 62 bits for Linux as uppper most two bits are reserved to indicate SBI fw or platform specific firmware events. However, the event data field is masked as per the hardware raw event mask which is not correct. Fix the platform firmware event data field with proper mask. Fixes: f0c9363db2dd ("perf/riscv-sbi: Add platform specific firmware event = handling") Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 1 + drivers/perf/riscv_pmu_sbi.c | 12 +++++------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6c82318065cf..3d250824178b 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -159,6 +159,7 @@ struct riscv_pmu_snapshot_data { }; =20 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) +#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 #define RISCV_PLAT_FW_EVENT 0xFFFF =20 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 1aa303f76cc7..3473ba02abf3 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -507,7 +507,6 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; - u64 raw_config_val; int ret; =20 /* @@ -528,21 +527,20 @@ static int pmu_sbi_event_map(struct perf_event *event= , u64 *econfig) case PERF_TYPE_RAW: /* * As per SBI specification, the upper 16 bits must be unused - * for a raw event. + * for a hardware raw event. * Bits 63:62 are used to distinguish between raw events * 00 - Hardware raw event * 10 - SBI firmware events * 11 - Risc-V platform specific firmware event */ - raw_config_val =3D config & RISCV_PMU_RAW_EVENT_MASK; + switch (config >> 62) { case 0: ret =3D RISCV_PMU_RAW_EVENT_IDX; - *econfig =3D raw_config_val; + *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; break; case 2: - ret =3D (raw_config_val & 0xFFFF) | - (SBI_PMU_EVENT_TYPE_FW << 16); + ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); break; case 3: /* @@ -551,7 +549,7 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) * Event data - raw event encoding */ ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT; - *econfig =3D raw_config_val; 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Thu, 12 Dec 2024 16:09:44 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-725f0a0779dsm7441455b3a.154.2024.12.12.16.09.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 16:09:44 -0800 (PST) From: Atish Patra Date: Thu, 12 Dec 2024 16:09:33 -0800 Subject: [PATCH v2 2/3] drivers/perf: riscv: Return error for default case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241212-pmu_event_fixes_v2-v2-2-813e8a4f5962@rivosinc.com> References: <20241212-pmu_event_fixes_v2-v2-0-813e8a4f5962@rivosinc.com> In-Reply-To: <20241212-pmu_event_fixes_v2-v2-0-813e8a4f5962@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Mayuresh Chitale , Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 If the upper two bits has an invalid valid (0x1), the event mapping is not reliable as it returns an uninitialized variable. Return appropriate value for the default case. Fixes: f0c9363db2dd ("perf/riscv-sbi: Add platform specific firmware event = handling") Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3473ba02abf3..da3651d32906 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -507,7 +507,7 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; - int ret; + int ret =3D -ENOENT; =20 /* * Ensure we are finished checking standard hardware events for @@ -551,10 +551,11 @@ static int pmu_sbi_event_map(struct perf_event *event= , u64 *econfig) ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT; *econfig =3D config & RISCV_PMU_PLAT_FW_EVENT_MASK; break; + default: + break; } break; default: - ret =3D -ENOENT; break; } =20 --=20 2.34.1 From nobody Sat Dec 28 05:07:27 2024 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CE3763D for ; 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Thu, 12 Dec 2024 16:09:45 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-725f0a0779dsm7441455b3a.154.2024.12.12.16.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 16:09:45 -0800 (PST) From: Atish Patra Date: Thu, 12 Dec 2024 16:09:34 -0800 Subject: [PATCH v2 3/3] drivers/perf: riscv: Do not allow invalid raw event config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241212-pmu_event_fixes_v2-v2-3-813e8a4f5962@rivosinc.com> References: <20241212-pmu_event_fixes_v2-v2-0-813e8a4f5962@rivosinc.com> In-Reply-To: <20241212-pmu_event_fixes_v2-v2-0-813e8a4f5962@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Mayuresh Chitale , Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The SBI specification allows only lower 48bits of hpmeventX to be configured via SBI PMU. Currently, the driver masks of the higher bits but doesn't return an error. This will lead to an additional SBI call for config matching which should return for an invalid event error in most of the cases. However, if a platform(i.e Rocket and sifive cores) implements a bitmap of all bits in the event encoding this will lead to an incorrect event being programmed leading to user confusion. Report the error to the user if higher bits are set during the event mapping itself to avoid the confusion and save an additional SBI call. Suggested-by: Samuel Holland Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index da3651d32906..194c153e5d71 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -536,8 +536,11 @@ static int pmu_sbi_event_map(struct perf_event *event,= u64 *econfig) =20 switch (config >> 62) { case 0: - ret =3D RISCV_PMU_RAW_EVENT_IDX; - *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + /* Return error any bits [48-63] is set as it is not allowed by the sp= ec */ + if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) { + *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + ret =3D RISCV_PMU_RAW_EVENT_IDX; + } break; case 2: ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); --=20 2.34.1