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Signed-off-by: Pengfei Li Signed-off-by: Frank Li Reviewed-by: Krzysztof Kozlowski --- Change from v2 to v3 - add ref thermal-sensor - restrict #thermal-sensor-cells to 0 only - Change to unevaluatedProperties --- .../devicetree/bindings/thermal/fsl,imx91-tmu.yaml | 67 ++++++++++++++++++= ++++ 1 file changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/fsl,imx91-tmu.yaml b= /Documentation/devicetree/bindings/thermal/fsl,imx91-tmu.yaml new file mode 100644 index 0000000000000..8411f3233bf44 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/fsl,imx91-tmu.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/fsl,imx91-tmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX91 Thermal + +maintainers: + - Pengfei Li + +description: + i.MX91 features a new temperature sensor. It includes programmable + temperature threshold comparators for both normal and privileged + accesses and allows a programmable measurement frequency for the + Periodic One-Shot Measurement mode. Additionally, it provides + status registers for indicating the end of measurement and threshold + violation events. + +properties: + compatible: + items: + - const: fsl,imx91-tmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + nvmem-cells: + items: + - description: Phandle to the trim control 1 provided by ocotp + - description: Phandle to the trim control 2 provided by ocotp + + nvmem-cell-names: + items: + - const: trim1 + - const: trim2 + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: thermal-sensor.yaml + +unevaluatedProperties: false + +examples: + - | + #include + + thermal-sensor@44482000 { + compatible =3D "fsl,imx91-tmu"; + reg =3D <0x44482000 0x1000>; + #thermal-sensor-cells =3D <0>; + clocks =3D <&clk IMX93_CLK_TMC_GATE>; + nvmem-cells =3D <&tmu_trim1>, <&tmu_trim2>; + nvmem-cell-names =3D "trim1", "trim2"; + }; + +... --=20 2.34.1 From nobody Sun Dec 14 19:13:39 2025 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2043.outbound.protection.outlook.com [40.107.20.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 565F71C5F07; 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The register layout differs from other chips, necessitating the creation of a dedicated file for this. Signed-off-by: Pengfei Li Signed-off-by: Peng Fan Signed-off-by: Frank Li Reviewed-by: Marco Felsch --- change from v2 to v3 - add IMX91_TMU_ prefix for register define - remove unused register define - fix missed pm_runtime_put() at error path in imx91_tmu_get_temp() - use dev variable in probe function - use pm_runtime_set_active() in probe - move START to imx91_tmu_get_temp() - use DEFINE_RUNTIME_DEV_PM_OPS() - keep set reset value because there are not sw "reset" bit in controller, uboot may change and enable tmu. change from v1 to v2 - use low case for hexvalue - combine struct imx91_tmu and tmu_sensor - simplify imx91_tmu_start() and imx91_tmu_enable() - use s16 for imx91_tmu_get_temp(), which may negative value - use reverse christmas tree style - use run time pm - use oneshot to sample temp - register thermal zone after hardware init --- drivers/thermal/Kconfig | 10 ++ drivers/thermal/Makefile | 1 + drivers/thermal/imx91_thermal.c | 263 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 274 insertions(+) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index d3f9686e26e71..da403ed86aeb1 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -296,6 +296,16 @@ config IMX8MM_THERMAL cpufreq is used as the cooling device to throttle CPUs when the passive trip is crossed. =20 +config IMX91_THERMAL + tristate "Temperature sensor driver for NXP i.MX91 SoC" + depends on ARCH_MXC || COMPILE_TEST + depends on OF + help + Support for Temperature sensor found on NXP i.MX91 SoC. + It supports one critical trip point and one passive trip point. The + cpufreq is used as the cooling device to throttle CPUs when the passive + trip is crossed. + config K3_THERMAL tristate "Texas Instruments K3 thermal support" depends on ARCH_K3 || COMPILE_TEST diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 9abf43a74f2bb..08da241e6a598 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_ARMADA_THERMAL) +=3D armada_thermal.o obj-$(CONFIG_IMX_THERMAL) +=3D imx_thermal.o obj-$(CONFIG_IMX_SC_THERMAL) +=3D imx_sc_thermal.o obj-$(CONFIG_IMX8MM_THERMAL) +=3D imx8mm_thermal.o +obj-$(CONFIG_IMX91_THERMAL) +=3D imx91_thermal.o obj-$(CONFIG_MAX77620_THERMAL) +=3D max77620_thermal.o obj-$(CONFIG_QORIQ_THERMAL) +=3D qoriq_thermal.o obj-$(CONFIG_DA9062_THERMAL) +=3D da9062-thermal.o diff --git a/drivers/thermal/imx91_thermal.c b/drivers/thermal/imx91_therma= l.c new file mode 100644 index 0000000000000..62b579365fd03 --- /dev/null +++ b/drivers/thermal/imx91_thermal.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2024 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX91_TMU_STAT0 0x10 +#define IMX91_TMU_STAT0_DRDY0_IF_MASK BIT(16) + +#define IMX91_TMU_DATA0 0x20 + +#define IMX91_TMU_CTRL1_SET 0x204 +#define IMX91_TMU_CTRL1_CLR 0x208 +#define IMX91_TMU_CTRL1_EN BIT(31) +#define IMX91_TMU_CTRL1_START BIT(30) +#define IMX91_TMU_CTRL1_STOP BIT(29) +#define IMX91_TMU_CTRL1_RES_MASK GENMASK(19, 18) +#define IMX91_TMU_CTRL1_MEAS_MODE_MASK GENMASK(25, 24) +#define IMX91_TMU_CTRL1_MEAS_MODE_SINGLE 0 +#define IMX91_TMU_CTRL1_MEAS_MODE_CONTINUES 1 +#define IMX91_TMU_CTRL1_MEAS_MODE_PERIODIC 2 + +#define IMX91_TMU_REF_DIV 0x280 +#define IMX91_TMU_DIV_EN BIT(31) +#define IMX91_TMU_DIV_MASK GENMASK(23, 16) +#define IMX91_TMU_DIV_MAX 255 + +#define IMX91_TMU_PUD_ST_CTRL 0x2b0 +#define IMX91_TMU_PUDL_MASK GENMASK(23, 16) + +#define IMX91_TMU_TRIM1 0x2e0 +#define IMX91_TMU_TRIM2 0x2f0 + +#define IMX91_TMU_TEMP_LOW_LIMIT -40000 +#define IMX91_TMU_TEMP_HIGH_LIMIT 125000 + +#define IMX91_TMU_DEFAULT_TRIM1_CONFIG 0xb561bc2d +#define IMX91_TMU_DEFAULT_TRIM2_CONFIG 0x65d4 + +struct imx91_tmu { + void __iomem *base; + struct clk *clk; + struct device *dev; + struct thermal_zone_device *tzd; +}; + +static void imx91_tmu_start(struct imx91_tmu *tmu, bool start) +{ + u32 val =3D start ? IMX91_TMU_CTRL1_START : IMX91_TMU_CTRL1_STOP; + + writel_relaxed(val, tmu->base + IMX91_TMU_CTRL1_SET); +} + +static void imx91_tmu_enable(struct imx91_tmu *tmu, bool enable) +{ + u32 reg =3D enable ? IMX91_TMU_CTRL1_SET : IMX91_TMU_CTRL1_CLR; + + writel_relaxed(IMX91_TMU_CTRL1_EN, tmu->base + reg); +} + +static int imx91_tmu_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct imx91_tmu *tmu =3D thermal_zone_device_priv(tz); + s16 data; + int ret; + u32 val; + + ret =3D pm_runtime_resume_and_get(tmu->dev); + if (ret < 0) + return ret; + + imx91_tmu_start(tmu, true); + + ret =3D readl_relaxed_poll_timeout(tmu->base + IMX91_TMU_STAT0, val, + val & IMX91_TMU_STAT0_DRDY0_IF_MASK, 1000, 40000); + if (ret) { + ret =3D -EAGAIN; + goto out; + } + + /* DATA0 is 16bit signed number */ + data =3D readw_relaxed(tmu->base + IMX91_TMU_DATA0); + *temp =3D data * 1000 / 64; + if (*temp < IMX91_TMU_TEMP_LOW_LIMIT || *temp > IMX91_TMU_TEMP_HIGH_LIMIT) + ret =3D -EAGAIN; + +out: + pm_runtime_put(tmu->dev); + + return ret; +} + +static struct thermal_zone_device_ops tmu_tz_ops =3D { + .get_temp =3D imx91_tmu_get_temp, +}; + +static int imx91_init_from_nvmem_cells(struct imx91_tmu *tmu) +{ + struct device *dev =3D tmu->dev; + u32 trim1, trim2; + int ret; + + ret =3D nvmem_cell_read_u32(dev, "trim1", &trim1); + if (ret) + return ret; + + ret =3D nvmem_cell_read_u32(dev, "trim2", &trim2); + if (ret) + return ret; + + if (trim1 =3D=3D 0 || trim2 =3D=3D 0) + return -EINVAL; + + writel_relaxed(trim1, tmu->base + IMX91_TMU_TRIM1); + writel_relaxed(trim2, tmu->base + IMX91_TMU_TRIM2); + + return 0; +} + +static int imx91_tmu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct imx91_tmu *tmu; + unsigned long rate; + u32 div; + int ret; + + tmu =3D devm_kzalloc(dev, sizeof(struct imx91_tmu), GFP_KERNEL); + if (!tmu) + return -ENOMEM; + + tmu->dev =3D dev; + + tmu->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tmu->base)) + return dev_err_probe(dev, PTR_ERR(tmu->base), "failed to get io resource= "); + + tmu->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(tmu->clk)) + return dev_err_probe(dev, PTR_ERR(tmu->clk), "failed to get tmu clock\n"= ); + + platform_set_drvdata(pdev, tmu); + + /* disable the monitor during initialization */ + imx91_tmu_enable(tmu, false); + imx91_tmu_start(tmu, false); + + ret =3D imx91_init_from_nvmem_cells(tmu); + if (ret) { + writel_relaxed(IMX91_TMU_DEFAULT_TRIM1_CONFIG, tmu->base + IMX91_TMU_TRI= M1); + writel_relaxed(IMX91_TMU_DEFAULT_TRIM2_CONFIG, tmu->base + IMX91_TMU_TRI= M2); + } + + /* The typical conv clk is 4MHz, the output freq is 'rate / (div + 1)' */ + rate =3D clk_get_rate(tmu->clk); + div =3D (rate / 4000000) - 1; + if (div > IMX91_TMU_DIV_MAX) + return dev_err_probe(dev, -EINVAL, "clock divider exceed hardware limiat= ion"); + + /* Set divider value and enable divider */ + writel_relaxed(IMX91_TMU_DIV_EN | FIELD_PREP(IMX91_TMU_DIV_MASK, div), + tmu->base + IMX91_TMU_REF_DIV); + + /* Set max power up delay: 'Tpud(ms) =3D 0xFF * 1000 / 4000000' */ + writel_relaxed(FIELD_PREP(IMX91_TMU_PUDL_MASK, 100U), tmu->base + IMX91_T= MU_PUD_ST_CTRL); + + /* + * Set resolution mode + * 00b - Conversion time =3D 0.59325 ms + * 01b - Conversion time =3D 1.10525 ms + * 10b - Conversion time =3D 2.12925 ms + * 11b - Conversion time =3D 4.17725 ms + */ + writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL1_RES_MASK, 0x3), tmu->base + IMX= 91_TMU_CTRL1_CLR); + writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL1_RES_MASK, 0x1), tmu->base + IMX= 91_TMU_CTRL1_SET); + + writel_relaxed(IMX91_TMU_CTRL1_MEAS_MODE_MASK, tmu->base + IMX91_TMU_CTRL= 1_CLR); + writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL1_MEAS_MODE_MASK, IMX91_TMU_CTRL1= _MEAS_MODE_SINGLE), + tmu->base + IMX91_TMU_CTRL1_SET); + + imx91_tmu_enable(tmu, true); + pm_runtime_set_active(dev); + devm_pm_runtime_enable(dev); + + tmu->tzd =3D devm_thermal_of_zone_register(dev, 0, tmu, &tmu_tz_ops); + if (IS_ERR(tmu->tzd)) + return dev_err_probe(dev, PTR_ERR(tmu->tzd), + "failed to register thermal zone sensor\n"); + + pm_runtime_put(dev); + + return 0; +} + +static void imx91_tmu_remove(struct platform_device *pdev) +{ + struct imx91_tmu *tmu =3D platform_get_drvdata(pdev); + + /* disable tmu */ + imx91_tmu_start(tmu, false); + imx91_tmu_enable(tmu, false); +} + +static int imx91_tmu_runtime_suspend(struct device *dev) +{ + struct imx91_tmu *tmu =3D dev_get_drvdata(dev); + + /* disable tmu */ + imx91_tmu_enable(tmu, false); + + clk_disable_unprepare(tmu->clk); + + return 0; +} + +static int imx91_tmu_runtime_resume(struct device *dev) +{ + struct imx91_tmu *tmu =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_prepare_enable(tmu->clk); + if (ret) + return ret; + + imx91_tmu_enable(tmu, true); + + return 0; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(imx91_tmu_pm_ops, imx91_tmu_runtime_suspe= nd, + imx91_tmu_runtime_resume, NULL); + +static const struct of_device_id imx91_tmu_table[] =3D { + { .compatible =3D "fsl,imx91-tmu", }, + { }, +}; +MODULE_DEVICE_TABLE(of, imx91_tmu_table); + +static struct platform_driver imx91_tmu =3D { + .driver =3D { + .name =3D "imx91_thermal", + .pm =3D pm_ptr(&imx91_tmu_pm_ops), + .of_match_table =3D imx91_tmu_table, + }, + .probe =3D imx91_tmu_probe, + .remove =3D imx91_tmu_remove, +}; +module_platform_driver(imx91_tmu); + +MODULE_AUTHOR("Peng Fan "); +MODULE_DESCRIPTION("i.MX91 Thermal Monitor Unit driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1