From nobody Tue Feb 10 02:48:08 2026 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30A2D1F2C5D for ; Wed, 11 Dec 2024 23:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733960541; cv=none; b=mQjFv3ngD5YD3xSO2o006G/50n9l5D02cyVHd/3rlZ/PMmlruBvJk2mKuWTRCv9BzeZAe9W1cQVMWMnnhNmNJ5blkDLttbmv7U/DbJwOR9HHDdNgK0As1zdEiSnZcysx+Z3siv7x72ow5r2KDomsyp3Dt6KP5Jt4aLuCeFwlA4g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733960541; c=relaxed/simple; bh=ISbtWAbgbH8suuQWPxhz35KRwNuteJaYb06zfrxXSgQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VEODch1cpa43kTYdhm7bRMV1cOE/zib5v3xzMHxE31vVWoyqeKKRwa6eLQiYjbHJWbbKx2y5HwiT5m8g7SREx5GwoIIi9h16g0wjQ+gEwbiNkLnA/1JmWxELTGbphflkblRbKG8lONJfw83LybgiXsH7OOLzW720EjQ6gkJpnAs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KI1oirik; arc=none smtp.client-ip=209.85.167.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KI1oirik" Received: by mail-lf1-f53.google.com with SMTP id 2adb3069b0e04-53e28cf55cdso636e87.3 for ; Wed, 11 Dec 2024 15:42:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733960537; x=1734565337; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YYSiFqg6LOE1SzoDwt1N0XfguLIG+iXmgPLsdKO+JKI=; b=KI1oirikmO37h+9XQPmOVe5DSGy9T7VwhOu/P7KHvsOBiAYhUWXISsnKM5GbkRvd6D fpxny3OP3BoR+9f182V8tQNXsg/9nuo44ZZ2Nx2I+O3yjVSh1en8wZT6ETmIN7pjUB1o l6JRU5fGe7sChMbW1+8g2YvF2U34vm2ZWGI7bSwu8JNtJ7qzD3ul2Uuzo0ytwdLakdtK MFCtFt0FT+PJS/+gVQ2lgys9+kZ4zkyvweCmCHCtJnAJffltAlZTsr8WcQhJPWJo1gl8 g5s+y5V2/nog2f3d7QxK04xWPoGBrIJ6Vw9ZC85IPLt/ZrkeTKdMH28kJA02VIeKIG1T GUMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733960537; x=1734565337; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YYSiFqg6LOE1SzoDwt1N0XfguLIG+iXmgPLsdKO+JKI=; b=BKLjpk2m2FBfIsPXG1b2/FGJroksSKUeGwlKMvP0Aah3+sM4nKBuJiWmZI5KciW4sg KYd6DTO5Icw/Fc/y4mvNrmxHrpOxMx5OOBtNmbxWQXRZGywbzFvp/0gg0ju0952alqft uVJ1wVQ6r0jA2Rvs1JjPMhqKWFq8R3PheTHnyh6EOR1Uvz1mHrRgDbqnu6qIc6VDPklk b+PtMOD5/Zd2mrgTopAVBJFUKRjTRDCPxU8xkQQAPTR+WZss+HH8TQ8shq+cRxe8ZGk9 8CkOuBSWSMpQ0Dx17I9gKMAwnJzF8XyiuRSriPX4UilXEFMox3d4djQaOzptH28COqBZ X+3w== X-Forwarded-Encrypted: i=1; AJvYcCXiwlGAYK3JXIIURYhBaoq5xHgKiSNrgCZHmODjvPEOjo7YZWLVrZLXhsPvtXMWu6SEmdelgUdJ2TPWd+8=@vger.kernel.org X-Gm-Message-State: AOJu0YzF1zZYgkI8bbnCWRUrdaRGxgvM0F5H+a3nnonFNyUypyVNnHAG UH5NZpDXula+13j3lDRVbCTsdu6R7cVZEOZ3jKpICAE1LKNrX6GS5UjssmVSsgA= X-Gm-Gg: ASbGncvwLn4/CIQ5AzK2Hp6HRPVAiJ/Pr/5j51ec05DEvug1HZEuyAVhSUC+x42G6qi 6a0K39xzHjIDfJ9HnpMkrkat8h1Xa6seXyGBfZW0LrXlNsc7xQAQOvpnib6721aJh1GWmyTwp/Z XxonaxPxPYoxnC4DjtJNNShu97EydLJbTH0YucrbhUCsHCuUWrU+CObb0ZAoKn0oc5wOwzYYQ8W Gmdr2q3RD1alHyRupEvzmSvTqr5OSreQn2xhPnkbWK2WNTlDpX7U86OyNfWlw== X-Google-Smtp-Source: AGHT+IGCsiofK1N2EuUtLgduVy7VtNsSN/YPkp9+nebhQZyvQ4GnJv6b94YBm2ozk+8zzNRVWd7wEA== X-Received: by 2002:a05:6512:3b25:b0:540:29ac:bda5 with SMTP id 2adb3069b0e04-5402eff09f7mr475254e87.4.1733960537482; Wed, 11 Dec 2024 15:42:17 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5401cc76909sm1222207e87.58.2024.12.11.15.42.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 15:42:16 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 12 Dec 2024 01:41:47 +0200 Subject: [PATCH v3 12/14] drm/msm/dp: move more AUX functions to dp_aux.c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241212-fd-dp-audio-fixup-v3-12-0b1c65e7dba3@linaro.org> References: <20241212-fd-dp-audio-fixup-v3-0-0b1c65e7dba3@linaro.org> In-Reply-To: <20241212-fd-dp-audio-fixup-v3-0-0b1c65e7dba3@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14140; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ISbtWAbgbH8suuQWPxhz35KRwNuteJaYb06zfrxXSgQ=; b=owEBbAGT/pANAwAKAYs8ij4CKSjVAcsmYgBnWiM5XMfIx+BW6UYqs6KbjCBIgl3DoW0Gvy/yd 3bxNmM42JeJATIEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ1ojOQAKCRCLPIo+Aiko 1WT0B/iYwBzVJ6Jgm3Ut57vLSmS4wx037LlkornwGKmE0ao4c3gOeXW2Fe6ZQr/tCz0De5P3Gf9 4dKuKtr4gDEbMVIv8FBZSfD5xXcjx3vbQ3sQTaY7bP+VXjxSnma8s93g5kdOvsd1qrSYGzD9agv VIEKAA5IQgu2S+PhIzNjFhf+hhjy5WzndgWqKsNIJ1t5wp3MQHf/iJGmrgQZRBF/RR3ZySXk3RT klUaVgv7J8tHOAzQZWU/IQWt6JsLVp5BNngFhzCK9yyhw8Gp3U0BQJXEpnXFxWShdxV0ixpWBRn p+skVrrzH203/mULYyH4PMft3IpN4gho86cWY8HexgdS5yw= X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move several misnamed functions accessing AUX bus to dp_aux.c, further cleaning up dp_catalog submodule. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 94 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_aux.h | 7 +++ drivers/gpu/drm/msm/dp/dp_catalog.c | 75 +---------------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 6 --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++--- drivers/gpu/drm/msm/dp/dp_panel.c | 2 +- 7 files changed, 113 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index cdcab948ae7086964d9e913dadadacc333f46231..f8ea1754665afa37ff9dbaf3f88= 3d94c48bf07b8 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -403,7 +403,7 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, phy_calibrate(aux->phy); } /* reset aux if link is in connected state */ - if (msm_dp_catalog_link_is_connected(aux->catalog)) + if (msm_dp_aux_is_link_connected(msm_dp_aux)) msm_dp_aux_reset(aux); } else { aux->retry_cnt =3D 0; @@ -591,6 +591,98 @@ static int msm_dp_wait_hpd_asserted(struct drm_dp_aux = *msm_dp_aux, return ret; } =20 +void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + /* Configure REFTIMER and enable it */ + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg |=3D DP_DP_HPD_REFTIMER_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + + /* Enable HPD */ + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); +} + +void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg &=3D ~DP_DP_HPD_REFTIMER_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); +} + +void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg |=3D DP_DP_HPD_INT_MASK; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + reg & DP_DP_HPD_INT_MASK); +} + +void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg &=3D ~DP_DP_HPD_INT_MASK; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + reg & DP_DP_HPD_INT_MASK); +} + +u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + int isr, mask; + + isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, + (isr & DP_DP_HPD_INT_MASK)); + mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + + /* + * We only want to return interrupts that are unmasked to the caller. + * However, the interrupt status field also contains other + * informational bits about the HPD state status, so we only mask + * out the part of the register that tells us about which interrupts + * are pending. + */ + return isr & (mask | ~DP_DP_HPD_INT_MASK); +} + +u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 status; + + status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; + status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; + + return status; +} + struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, struct phy *phy, bool is_edp) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_au= x.h index 39c5b4c8596ab28d822493a6b4d479f5f786cdee..624395a41ed0a75ead4826e78d0= 5ca21e8fb8967 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -17,6 +17,13 @@ void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux); =20 +void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux); +u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux); +u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux); + struct phy; struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, struct phy *phy, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 2eea02fc4cca3f7183e97d0fc086b8d6fa27ad00..22e2b3147399c0dcce21b9138c2= 4eb699660f21a 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -85,8 +85,8 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm= _dp_catalog) intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, intr_ack | - DP_INTERRUPT_STATUS1_MASK); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; =20 @@ -119,77 +119,6 @@ void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_cata= log *msm_dp_catalog, } } =20 -void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, - u32 intr_mask, bool en) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 config =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); - - config =3D (en ? config | intr_mask : config & ~intr_mask); - - drm_dbg_dp(catalog->drm_dev, "intr_mask=3D%#x config=3D%#x\n", - intr_mask, config); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, - config & DP_DP_HPD_INT_MASK); -} - -void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); - - /* Configure REFTIMER and enable it */ - reftimer |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - - /* Enable HPD */ - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); -} - -void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); - - reftimer &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); -} - -u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 status; - - status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); - status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; - status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; - - return status; -} - -u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og) -{ - int isr, mask; - - isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, - (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); - - /* - * We only want to return interrupts that are unmasked to the caller. - * However, the interrupt status field also contains other - * informational bits about the HPD state status, so we only mask - * out the part of the register that tells us about which interrupts - * are pending. - */ - return isr & (mask | ~DP_DP_HPD_INT_MASK); -} - u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) { u32 intr, intr_ack; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index a6d662f5a0d95cdb8f40a9d03be1e7627907b176..789403e332c1a2108ded4f96b04= 9fd00bb34e326 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -118,12 +118,6 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *= msm_dp_catalog); /* DP Controller APIs */ u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog= ); void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); -void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, - u32 intr_mask, bool en); -void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog); -void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog= ); -u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog= ); -u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og); int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index cde667bf8eeec95035b2feb3661686c99acf5b7d..5f32ee2fa0438cd12726540a59a= b4849d47ee8c2 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2162,7 +2162,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) break; } else if (training_step =3D=3D DP_TRAINING_1) { /* link train_1 failed */ - if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) + if (!msm_dp_aux_is_link_connected(ctrl->aux)) break; =20 msm_dp_ctrl_read_link_status(ctrl, link_status); @@ -2187,7 +2187,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) } } else if (training_step =3D=3D DP_TRAINING_2) { /* link train_2 failed */ - if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) + if (!msm_dp_aux_is_link_connected(ctrl->aux)) break; =20 msm_dp_ctrl_read_link_status(ctrl, link_status); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index aff51bb973ebe0835c96420d16547ebae0c6c0f2..cb02d5d5b404925707c737ed75e= 9e83fbec34f83 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1145,7 +1145,7 @@ static irqreturn_t msm_dp_display_irq_handler(int irq= , void *dev_id) return IRQ_NONE; } =20 - hpd_isr_status =3D msm_dp_catalog_hpd_get_intr_status(dp->catalog); + hpd_isr_status =3D msm_dp_aux_get_hpd_intr_status(dp->aux); =20 if (hpd_isr_status & 0x0F) { drm_dbg_dp(dp->drm_dev, "type=3D%d isr=3D0x%x\n", @@ -1360,7 +1360,7 @@ static int msm_dp_pm_runtime_suspend(struct device *d= ev) =20 if (dp->msm_dp_display.is_edp) { msm_dp_display_host_phy_exit(dp); - msm_dp_catalog_ctrl_hpd_disable(dp->catalog); + msm_dp_aux_hpd_disable(dp->aux); } msm_dp_display_host_deinit(dp); =20 @@ -1381,7 +1381,7 @@ static int msm_dp_pm_runtime_resume(struct device *de= v) */ msm_dp_display_host_init(dp); if (dp->msm_dp_display.is_edp) { - msm_dp_catalog_ctrl_hpd_enable(dp->catalog); + msm_dp_aux_hpd_enable(dp->aux); msm_dp_display_host_phy_init(dp); } =20 @@ -1668,10 +1668,8 @@ void msm_dp_bridge_hpd_enable(struct drm_bridge *bri= dge) return; } =20 - msm_dp_catalog_ctrl_hpd_enable(dp->catalog); - - /* enable HDP interrupts */ - msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, true); + msm_dp_aux_hpd_enable(dp->aux); + msm_dp_aux_hpd_intr_enable(dp->aux); =20 msm_dp_display->internal_hpd =3D true; mutex_unlock(&dp->event_mutex); @@ -1684,9 +1682,9 @@ void msm_dp_bridge_hpd_disable(struct drm_bridge *bri= dge) struct msm_dp_display_private *dp =3D container_of(msm_dp_display, struct= msm_dp_display_private, msm_dp_display); =20 mutex_lock(&dp->event_mutex); - /* disable HDP interrupts */ - msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false); - msm_dp_catalog_ctrl_hpd_disable(dp->catalog); + + msm_dp_aux_hpd_intr_disable(dp->aux); + msm_dp_aux_hpd_disable(dp->aux); =20 msm_dp_display->internal_hpd =3D false; =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index cd91de21c8e658570b8d43251ef815981f801ae4..25869e2ac93aba0bffeddae9f95= 917d81870d8cb 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -165,7 +165,7 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *ms= m_dp_panel, if (!msm_dp_panel->drm_edid) { DRM_ERROR("panel edid read failed\n"); /* check edid read fail is due to unplug */ - if (!msm_dp_catalog_link_is_connected(panel->catalog)) { + if (!msm_dp_aux_is_link_connected(panel->aux)) { rc =3D -ETIMEDOUT; goto end; } --=20 2.39.5