From nobody Sun Dec 14 21:24:59 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C11D41D6DB9 for ; Wed, 11 Dec 2024 15:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733932011; cv=none; b=d27gVFfeqF0RGHofgM85tm8e+3tfhDqa/h3vBqt47ljr2RukWiDg5Q/+PZbJ9BBDjaQvmBhreZwDOlvRfleKyABh63wQ/E07SN4IQET4NhJhLDw92U+0ynJTw+zSBJhNFJkMs9FHuwrsFsqZfHqCSXAugJR9CSocIDWqUxChlLY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733932011; c=relaxed/simple; bh=M12C/rqNOn4PmgzITi2hwHA4DckgrKjjVVNmtRic7Ns=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QWnr/TTMPTgXNB5QO6VtnIxMJW30J+sOtm/gZ5hoqbP3Tc3Abfw9dGGD7bdVqrKdQNJjpKViG+PVgiToHRu0FGagMLaDxHurhE5DkOfhuU39aOBPEIssAevpn+dWbRz/3BNHYCXuhKK3aKCCGO/58OJsCWad/Z2b+Ck3gVz0AZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C87EFEC; Wed, 11 Dec 2024 07:47:17 -0800 (PST) Received: from mazurka.cambridge.arm.com (mazurka.cambridge.arm.com [10.1.196.66]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 78DAA3F5A1; Wed, 11 Dec 2024 07:46:47 -0800 (PST) From: =?UTF-8?q?Miko=C5=82aj=20Lenczewski?= To: catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com Cc: =?UTF-8?q?Miko=C5=82aj=20Lenczewski?= , linux-arm-kernel@lists.infradead.org, liunx-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvmarm@vger.kernel.org Subject: [RFC PATCH v1 1/5] arm64: Add TLB Conflict Abort Exception handler to KVM Date: Wed, 11 Dec 2024 15:45:02 +0000 Message-ID: <20241211154611.40395-2-miko.lenczewski@arm.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211154611.40395-1-miko.lenczewski@arm.com> References: <20241211154611.40395-1-miko.lenczewski@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Currently, KVM does not handle the case of a stage 2 TLB conflict abort exception. The Arm ARM specifies that the worst-case handling of such an exception requires a `tlbi vmalls12e1`. Perform such an invalidation when this exception is encountered. Signed-off-by: Miko=C5=82aj Lenczewski --- arch/arm64/include/asm/esr.h | 8 ++++++++ arch/arm64/kvm/mmu.c | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index d1b1a33f9a8b..8a66f81ca291 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -121,6 +121,7 @@ #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) #define ESR_ELx_FSC_SECC (0x18) #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) +#define ESR_ELx_FSC_TLBABT (0x30) =20 /* Status codes for individual page table levels */ #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) @@ -464,6 +465,13 @@ static inline bool esr_fsc_is_access_flag_fault(unsign= ed long esr) (esr =3D=3D ESR_ELx_FSC_ACCESS_L(0)); } =20 +static inline bool esr_fsc_is_tlb_conflict_abort(unsigned long esr) +{ + esr =3D esr & ESR_ELx_FSC; + + return esr =3D=3D ESR_ELx_FSC_TLBABT; +} + /* Indicate whether ESR.EC=3D=3D0x1A is for an ERETAx instruction */ static inline bool esr_iss_is_eretax(unsigned long esr) { diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index c9d46ad57e52..c8c6f5a97a1b 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1756,6 +1756,12 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) ipa =3D fault_ipa =3D kvm_vcpu_get_fault_ipa(vcpu); is_iabt =3D kvm_vcpu_trap_is_iabt(vcpu); =20 + if (esr_fsc_is_tlb_conflict_abort(esr)) { + // does a `tlbi vmalls12e1is` + __kvm_tlb_flush_vmid(&vcpu->kvm->arch.mmu); + return 1; + } + if (esr_fsc_is_translation_fault(esr)) { /* Beyond sanitised PARange (which is the IPA limit) */ if (fault_ipa >=3D BIT_ULL(get_kvm_ipa_limit())) { --=20 2.45.2