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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Dege , Christian Mardmoeller , Dennis Ostermann , Nikita Yushchenko Subject: [PATCH net v2] net: renesas: rswitch: fix initial MPIC register setting Date: Wed, 11 Dec 2024 10:30:12 +0500 Message-Id: <20241211053012.368914-1-nikita.yoush@cogentembedded.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPIC.PIS must be set per phy interface type. MPIC.LSC must be set per speed. Do that strictly per datasheet, instead of hardcoding MPIC.PIS to GMII. Fixes: 3590918b5d07 ("net: ethernet: renesas: Add support for "Ethernet Swi= tch"") Signed-off-by: Nikita Yushchenko Reviewed-by: Michal Swiatkowski --- v1: https://lore.kernel.org/netdev/20241209075951.163924-1-nikita.yoush@cog= entembedded.com/ changes: regenerate against top of net tree (commit 3dd002f20098 "net: renesas: rswitch: handle stop vs interrupt race") to ensure it applies cleanly --- drivers/net/ethernet/renesas/rswitch.c | 27 ++++++++++++++++++++------ drivers/net/ethernet/renesas/rswitch.h | 14 ++++++------- 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/= renesas/rswitch.c index 6ec714789573..dbbbf024e7ab 100644 --- a/drivers/net/ethernet/renesas/rswitch.c +++ b/drivers/net/ethernet/renesas/rswitch.c @@ -1116,25 +1116,40 @@ static int rswitch_etha_wait_link_verification(stru= ct rswitch_etha *etha) =20 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) { - u32 val; + u32 pis, lsc; =20 rswitch_etha_write_mac_address(etha, mac); =20 + switch (etha->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + pis =3D MPIC_PIS_GMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_5GBASER: + pis =3D MPIC_PIS_XGMII; + break; + default: + pis =3D FIELD_GET(MPIC_PIS, ioread32(etha->addr + MPIC)); + break; + } + switch (etha->speed) { case 100: - val =3D MPIC_LSC_100M; + lsc =3D MPIC_LSC_100M; break; case 1000: - val =3D MPIC_LSC_1G; + lsc =3D MPIC_LSC_1G; break; case 2500: - val =3D MPIC_LSC_2_5G; + lsc =3D MPIC_LSC_2_5G; break; default: - return; + lsc =3D FIELD_GET(MPIC_LSC, ioread32(etha->addr + MPIC)); + break; } =20 - iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC); + rswitch_modify(etha->addr, MPIC, MPIC_PIS | MPIC_LSC, + FIELD_PREP(MPIC_PIS, pis) | FIELD_PREP(MPIC_LSC, lsc)); } =20 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/= renesas/rswitch.h index 72e3ff596d31..e020800dcc57 100644 --- a/drivers/net/ethernet/renesas/rswitch.h +++ b/drivers/net/ethernet/renesas/rswitch.h @@ -724,13 +724,13 @@ enum rswitch_etha_mode { =20 #define EAVCC_VEM_SC_TAG (0x3 << 16) =20 -#define MPIC_PIS_MII 0x00 -#define MPIC_PIS_GMII 0x02 -#define MPIC_PIS_XGMII 0x04 -#define MPIC_LSC_SHIFT 3 -#define MPIC_LSC_100M (1 << MPIC_LSC_SHIFT) -#define MPIC_LSC_1G (2 << MPIC_LSC_SHIFT) -#define MPIC_LSC_2_5G (3 << MPIC_LSC_SHIFT) +#define MPIC_PIS GENMASK(2, 0) +#define MPIC_PIS_GMII 2 +#define MPIC_PIS_XGMII 4 +#define MPIC_LSC GENMASK(5, 3) +#define MPIC_LSC_100M 1 +#define MPIC_LSC_1G 2 +#define MPIC_LSC_2_5G 3 =20 #define MDIO_READ_C45 0x03 #define MDIO_WRITE_C45 0x01 --=20 2.39.5