From nobody Sun Dec 14 08:06:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14F4917736 for ; Wed, 11 Dec 2024 01:42:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881338; cv=none; b=Kln4xs0fb8kdOrkjuOHyIgS7TPZqvk68qu6fec8+fuBFAMhqSfMc40/w/F2SD1bmKgjvB0YjOGFNrAEklUWglY/N+jJDgcj6qjexGBDAnUrisQkgJ2/OSSCoWI3fVOreGFjonxkPQvxFZFOoeDCT0id/qHh2W81nfF6vMHut650= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881338; c=relaxed/simple; bh=57H56OVlleoffXbP8jWPOJE1INbC7Zl4KRINZxyt8to=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ftIkYgJDTA6tg+SGWOnm0ufS/+t8aAnY/NyIAt56tXldurdp6v+CqVhPvPo3uUKz0uHkbadDNyFicB28aZ3nj4K/Px8oUWwlPe1AeDv3pdS+5UC+0CZnA62+1wUvIxKlB53qi+yws56vEM4rYvkexftyN+so9tDDR5vHaw5/85Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=es3Jh81c; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="es3Jh81c" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733881337; x=1765417337; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=57H56OVlleoffXbP8jWPOJE1INbC7Zl4KRINZxyt8to=; b=es3Jh81cAu37pgvTvtMY49kAFwi47DoxKs+iHRHBQ88MaIsNeCMJ87u3 pyLnLsFaWUq20eJ2dIHGcENEgfSkhJpo9ns5FtnMuuS+6Gj0XOiZgvxvD T9ezLwHfqD/THmllZAjgup4Ld92wcxoOa3aZy19dhSToipyxaWDKGb6Bc msOuom5OZyluihP6jatjVXhkQoMxf11DpZHtu5mc0l2cSSpvG463h7KF7 ZyEoNu/iMlG6qJO90CzLvdZW59iRDMYrtwjkaSzlE2laJoE+ZgAVXY6IK 36v1OsMRZX+H82J3OaC4PK36YcAci9UB9maTdj1PRADsItei8r76M7d78 w==; X-CSE-ConnectionGUID: T4p9rAkaThGZjehCkrhT5w== X-CSE-MsgGUID: qTUwBwOrSmK83Jw/ifejeA== X-IronPort-AV: E=McAfee;i="6700,10204,11282"; a="33570538" X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="33570538" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 17:42:16 -0800 X-CSE-ConnectionGUID: f1c19SwZSySpZPj7PuLP0w== X-CSE-MsgGUID: EecU6/u6RmGHy9WNgEslKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="96051726" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.134.127]) by orviesa007.jf.intel.com with ESMTP; 10 Dec 2024 17:42:15 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 1/6] x86/microcode: Introduce staging option to reduce late-loading latency Date: Tue, 10 Dec 2024 17:42:07 -0800 Message-ID: <20241211014213.3671-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211014213.3671-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> <20241211014213.3671-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As microcode patch sizes continue to grow, the latency during late-loading can spike, leading to timeouts and interruptions in running workloads. This trend of increasing patch sizes is expected to continue, so a foundational solution is needed to address the issue. To mitigate the problem, a new staging feature is introduced. This option processes most of the microcode update (excluding activation) on a non-critical path, allowing CPUs to remain operational during the majority of the update. By moving most of the work off the critical path, the latency spike can be significantly reduced. Integrate the staging process as an additional step in the late-loading flow. Introduce a new callback for staging, which is invoked after the microcode patch image is prepared but before entering the CPU rendezvous for triggering the update. Staging follows an opportunistic model: it is attempted when available. If successful, it reduces CPU rendezvous time; if not, the process falls back to the legacy loading, potentially exposing the system to higher latency. Extend struct microcode_ops to incorporate staging properties, which will be updated in the vendor code from subsequent patches. Signed-off-by: Chang S. Bae --- RFC-V1 -> V1: Rename the function name to the do_something() style (Boris). Note. Whether staging should be mandatory is a policy decision that is beyond the scope of this patch at the moment. For now, the focus is on establishing a basic flow, with the intention of attracting focused reviews, while deferring the discussion on staging policy later. In terms of the flow, an alternative approach could be to integrate staging as part of microcode preparation on the vendor code side. However, this was deemed too implicit, as staging involves loading and validating the microcode image, which differs from typical microcode file handling. --- arch/x86/kernel/cpu/microcode/core.c | 12 ++++++++++-- arch/x86/kernel/cpu/microcode/internal.h | 4 +++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index b3658d11e7b6..0967fd15be6e 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -676,19 +676,27 @@ static bool setup_cpus(void) =20 static int load_late_locked(void) { + bool is_safe =3D false; + if (!setup_cpus()) return -EBUSY; =20 switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { case UCODE_NEW: - return load_late_stop_cpus(false); + break; case UCODE_NEW_SAFE: - return load_late_stop_cpus(true); + is_safe =3D true; + break; case UCODE_NFOUND: return -ENOENT; default: return -EBADFD; } + + if (microcode_ops->use_staging) + microcode_ops->stage_microcode(); + + return load_late_stop_cpus(is_safe); } =20 static ssize_t reload_store(struct device *dev, diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 21776c529fa9..b27cb8e1228d 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,10 +31,12 @@ struct microcode_ops { * See also the "Synchronization" section in microcode_core.c. */ enum ucode_state (*apply_microcode)(int cpu); + void (*stage_microcode)(void); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); unsigned int nmi_safe : 1, - use_nmi : 1; + use_nmi : 1, + use_staging : 1; }; =20 struct early_load_data { --=20 2.45.2 From nobody Sun Dec 14 08:06:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2093D3A8F7 for ; Wed, 11 Dec 2024 01:42:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881339; cv=none; b=hCx/7h0AIngq/0/M+uNv9IigDljLrtaJMkQC32v1FwAWaTeijVGsYOMBp7h688n7sAmnB6YT0B8IA8TcReMVouCaywesJsWAOLSXcAUXPKfNKpvzjC25NKi+dRhHJDCX/fG4WiHAoEBvdgjmoMJ9eTZnhLbcR2sPpaE5mLHPNgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881339; c=relaxed/simple; bh=VneD3LX91mMVNS9V8upIgzYFKlv4ELAQ7huR/BuL67s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VWfMaQNJ4OTwEvy+RccfiqKoPwYrj7rMXbufVw/XEcbHY1FOSOaX0kUB7w5jt2E8AnNIGq0FtyNCr//GGkjgK1pHpKIOPM/+oaSzl/nIWUmEaUWh87NUht5W5wwWbo9sFmDDnwnQwWOv4NuamL2/j7TmZlu/GxyaEzj9GcmtB90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TwHXfvLV; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TwHXfvLV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733881338; x=1765417338; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VneD3LX91mMVNS9V8upIgzYFKlv4ELAQ7huR/BuL67s=; b=TwHXfvLVcObxhOvzDV+/y8I260CkRKiQVtDQbDTkSAxwIE2SlPPYb2HP pyqFLZ00svmsWWNKrS4Rgasxy6lNq/lhbOVsIek0MtKWiewoOX5CM9HT2 9T4GqijCH17+oTQbg2OBWOhDLLYRx6J2Bn0AvQkIhN3CN00vya5BtOv8A oI50oTMFlpNaDvT6T0npc2OQFOxv+AVMHrxfo/VkPKxUzkhTE1Y9kD2zK 1mfRUq5d6eJehbizPscFRkQoYDU41e522B4cUOke5R6HzQHDAYmnfpJ2G brZzJh767+k9pVeOWA6sj3dobtfUNUk9vFMpJEwBtn4xpEb3vbGq0gGJ/ Q==; X-CSE-ConnectionGUID: 471NLaQkTyKlbTXbyNGzxg== X-CSE-MsgGUID: IzgFHl0ZTBmn0+kD12PH2w== X-IronPort-AV: E=McAfee;i="6700,10204,11282"; a="33570542" X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="33570542" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 17:42:17 -0800 X-CSE-ConnectionGUID: XlCur5jzQS2volmAQWlBYg== X-CSE-MsgGUID: tMrViD0DQN+iZxjVa8Gqog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="96051745" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.134.127]) by orviesa007.jf.intel.com with ESMTP; 10 Dec 2024 17:42:17 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 2/6] x86/msr-index: Define MSR index and bit for the microcode staging feature Date: Tue, 10 Dec 2024 17:42:08 -0800 Message-ID: <20241211014213.3671-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211014213.3671-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> <20241211014213.3671-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The microcode staging feature involves two key MSR entities, the presence of which is indicated by bit 16 of IA32_ARCH_CAPABILITIES: * Bit 4 in IA32_MCU_ENUMERATION shows the availability of the microcode staging feature. * Staging is managed through MMIO registers, with IA32_MCU_STAGING_MBOX_ADDR MSR specifying the physical address of the first MMIO register. Define the MSR index and bit assignments, helping the upcoming staging code to make use of the hardware feature. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/msr-index.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3ae84c3b8e6d..2840a2fe340b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -164,6 +164,10 @@ * Processor MMIO stale data * vulnerabilities. */ +#define ARCH_CAP_MCU_ENUM BIT(16) /* + * Indicates the presence of microcode update + * feature enumeration and status information + */ #define ARCH_CAP_FB_CLEAR BIT(17) /* * VERW clears CPU fill buffer * even on MDS_NO CPUs. @@ -884,6 +888,11 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b =20 +#define MSR_IA32_MCU_ENUMERATION 0x0000007b +#define MCU_STAGING BIT(4) + +#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 + /* Intel SGX Launch Enclave Public Key Hash MSRs */ #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D --=20 2.45.2 From nobody Sun Dec 14 08:06:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57E1717D358 for ; Wed, 11 Dec 2024 01:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881344; cv=none; b=QS00FD9kfzrvyupVGGwsvjYTYZXfwp2t9jGNGFJgg8X+lzJJ+VKV5rzxS5TxAwRsQ2U0zi+U0xmIbdzV1pGt4cze6aosQXikiR1NOrzv0spg+HUO735TYRRwSICjPLrK2ewH0GuYHKpIKL4BHVWORj3uL0CA3MXFvXvwg70J6Kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881344; c=relaxed/simple; bh=s8zd5KKT7bLDGEnc2DPSJFBeXiiU6rD6ciO1nDnYBio=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IjvFkI3UrunkPv77IRMyxON4ld38sQ8IcwFu7GefdIgB2lU+N92eroTQvho+viGkWWYEWxebMGKJ7tVlkdtIpDm56abzNYZ+XsRtEHQlh5RBZ5abx0ub0ovnaeSuHc02hewmHlA4gU+VTlUyX/0GJf3Kqisz3DtyeBCsn944c0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LS8EsN+Y; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LS8EsN+Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733881341; x=1765417341; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s8zd5KKT7bLDGEnc2DPSJFBeXiiU6rD6ciO1nDnYBio=; b=LS8EsN+YeC+NqJ1VZ+ctKNhMU5ROAUcnoexhKkyEcLOeDz7AAVBcohHA N/2rR9btjTMrM3PmVdYMmQ/x8njCquwj+FW5i0QobUSGQHOzS2Ku5HvpR IZc3aJ+iCHo9DRNaLSC8BVzwiLi2h8yC4ZBffPVg0p7pbomF+bvmJXp1F Tlo0dpw/DNnbNEh8mOB7jAUQmCqAf54MyBdNCc+9Nd7t6tF/pmZLWLEb2 bCfLM+tD5RgqzoKWJAMQaFL6FB0VjaCFLIgr3WfiIfGn3I9+wIX0AGSzo vjY2W/VwTxxRYIUsPuFOujD6/ObQn4ZWniQa4/ONcfMHWekdYHLjrlLih A==; X-CSE-ConnectionGUID: zkV8UPVWQNKRS5KbdZ5pgA== X-CSE-MsgGUID: FQWzJTLISCm/dGpqBzlm5w== X-IronPort-AV: E=McAfee;i="6700,10204,11282"; a="33570548" X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="33570548" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 17:42:18 -0800 X-CSE-ConnectionGUID: fJ1ry+HFTCWe8X6XDWSdiQ== X-CSE-MsgGUID: ykI9WMBTSGGJXfxGF1k6zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="96051756" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.134.127]) by orviesa007.jf.intel.com with ESMTP; 10 Dec 2024 17:42:18 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 3/6] x86/microcode/intel: Prepare for microcode staging Date: Tue, 10 Dec 2024 17:42:09 -0800 Message-ID: <20241211014213.3671-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211014213.3671-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> <20241211014213.3671-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When microcode staging is initiated, operations are carried out through an MMIO interface. Each package has a unique interface specified by the IA32_MCU_STAGING_MBOX_ADDR MSR, which points to a set of dword-sized registers. Prepare staging with the following steps: First, ensure the microcode image is dword-aligned to correspond with MMIO registers. Next, identify each MMIO interface based on its per-package scope. Then, invoke the staging function for each identified interface. Suggested-by: Thomas Gleixner Signed-off-by: Chang S. Bae --- RFC-V1 -> V1: * Simplify code by leveraging the architectural per-package staging scope (Thomas). * Fix MSR read code (Boris and Dave). * Rename the staging function: staging_work() -> do_stage() (Boris). * Polish the result messages (Boris). * Add a prototype for builds without CONFIG_CPU_SUP_INTEL (Boris). * Massage the changelog. Note: 1. Using a direct reference to 'cpu_primary_thread_mask' in for_each_cpu(...) causes a build error when !CONFIG_SMP. Instead, use the wrapper function topology_is_primary_thread() to avoid it. 2. Ideally, the do_stage() function would be as simple as a single WRMSR execution. If this were the case, the staging flow could be completed with this patch. From this perspective, the software handling for interacting with the staging firmware has been separated from this vendor code and moved into a new file dedicated to staging logic. --- arch/x86/kernel/cpu/microcode/intel.c | 36 ++++++++++++++++++++++++ arch/x86/kernel/cpu/microcode/internal.h | 7 +++++ 2 files changed, 43 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index f3d534807d91..325068bb5524 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -299,6 +299,41 @@ static __init struct microcode_intel *scan_microcode(v= oid *data, size_t size, return size ? NULL : patch; } =20 +static void stage_microcode(void) +{ + unsigned int totalsize, pkg_id =3D UINT_MAX; + enum ucode_state state; + int cpu; + u64 pa; + + totalsize =3D get_totalsize(&ucode_patch_late->hdr); + if (!IS_ALIGNED(totalsize, sizeof(u32))) + return; + + /* + * The MMIO address is unique per package, and all the SMT + * primary threads are online here. Find each MMIO space by + * their package ids to avoid duplicate staging. + */ + for_each_cpu(cpu, cpu_online_mask) { + if (!topology_is_primary_thread(cpu) || topology_logical_package_id(cpu)= =3D=3D pkg_id) + continue; + pkg_id =3D topology_logical_package_id(cpu); + + rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &pa); + + state =3D do_stage(pa, ucode_patch_late, totalsize); + if (state !=3D UCODE_OK) { + pr_err("Error: staging failed with %s for CPU%d at package %u.\n", + state =3D=3D UCODE_TIMEOUT ? "timeout" : "error state", cpu, pkg= _id); + return; + } + } + + pr_info("Staging of patch revision 0x%x succeeded.\n", + ((struct microcode_header_intel *)ucode_patch_late)->rev); +} + static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, u32 *cur_rev) @@ -627,6 +662,7 @@ static struct microcode_ops microcode_intel_ops =3D { .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, + .stage_microcode =3D stage_microcode, .use_nmi =3D IS_ENABLED(CONFIG_X86_64), }; =20 diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index b27cb8e1228d..158429d80f93 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -120,11 +120,18 @@ void load_ucode_intel_bsp(struct early_load_data *ed); void load_ucode_intel_ap(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); +static inline enum ucode_state do_stage(u64 pa, void *ucode_ptr, unsigned = int totalsize) +{ + pr_debug_once("Need to implement the staging code.\n"); + return UCODE_ERROR; +} #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(struct early_load_data *ed) { } static inline void load_ucode_intel_ap(void) { } static inline void reload_ucode_intel(void) { } static inline struct microcode_ops *init_intel_microcode(void) { return NU= LL; } +static inline enum ucode_state +do_stage(u64 pa, void *ucode_ptr, unsigned int totalsize) { return UCODE_E= RROR; } #endif /* !CONFIG_CPU_SUP_INTEL */ =20 #endif /* _X86_MICROCODE_INTERNAL_H */ --=20 2.45.2 From nobody Sun Dec 14 08:06:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C696D1494CC for ; Wed, 11 Dec 2024 01:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881341; cv=none; b=q3/C+xhU9+/R8nmOcoYG496c2M8/8DZBUNcREGO4G7YADqjpchjko4YUfdZ5wwwRgj63BsD5jv01nURQ9yHTmXoSR8tJR5H7znWi1zomM8PVBJy4eRx1ySrOjepndzX3btkj6gqS9gob2i+QVS/IF8w1lI+cDom3qfkLBXzKCyc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733881341; c=relaxed/simple; bh=DUIH1w/BOjTwUrlULnXMLR6HxahjuQBSWikikRSPEzY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DnLIwDZY0X2c1sL2db/d13vaNpyFYyzPuAF5iwRcv//Dup7JWysD8BzFN/X633OGrTPQ+s76hx63Aqs7DSddgm1+MBLa0PFXGh6UaAVZaNnnMUm6ljdiKDS3uoKwuJfC9sJ0blsIxKCJeXikRZjRQoH2LOE9H7c6kx2ueC4QEaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TellIruS; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TellIruS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733881339; x=1765417339; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DUIH1w/BOjTwUrlULnXMLR6HxahjuQBSWikikRSPEzY=; b=TellIruSOqeTzufVdQTYj28MUDzbar0oy1W/u5QucBhxbHUGE1LbThOq xuSdW4JbLyGCrvr+PDzknudf/Z/d5dGOUlRdWy9Hc7f9TqcmSoWkKCdAh Tov9ZY7gJbnGyBGS/OITHpED5grhrI+pslGptM0dnt6t+9yb/8tSMw3gZ UrS0HKXG4YH62Y7T8nZAotabr6y7ngbSqQoSexMmNsP75pIscIoNNddpN oiuczzXnzIBwEPNkSq92Fsxm5JEO6P1pgsmG/1CYoTV/dLwFwuJLHpGPu JF7V/Tgr31wJ/JzUvoYrD4VFGs09JF87mQ9BgxB5K/MvcX8TiCg/ixpEh Q==; X-CSE-ConnectionGUID: Fy1v8BtOTs2zFIWYur9cMg== X-CSE-MsgGUID: +PzDHKPYQG62p37QK8fvZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11282"; a="33570553" X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="33570553" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 17:42:19 -0800 X-CSE-ConnectionGUID: Ydo5LzeaQYm1CD9knU2ykg== X-CSE-MsgGUID: Ocgj/pnLTYC4wgdxaFrWeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="96051765" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.134.127]) by orviesa007.jf.intel.com with ESMTP; 10 Dec 2024 17:42:19 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 4/6] x86/microcode/intel_staging: Implement staging logic Date: Tue, 10 Dec 2024 17:42:10 -0800 Message-ID: <20241211014213.3671-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211014213.3671-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> <20241211014213.3671-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The staging firmware operates through a protocol via the MMIO interface. The protocol defines a serialized sequence that begins by clearing the hardware with an abort request. It then proceeds through iterative process of sending data, initiating transactions, waiting for processing, and reading responses. To facilitate this interaction, follow the outlined protocol. Refactor the waiting code to manage loop breaks more effectively. Data transfer involves a next level of detail to handle the mailbox format. While defining helpers, leave them empty for now. Signed-off-by: Chang S. Bae --- RFC-V1 -> V1: Rename the function name and change the return type. --- arch/x86/kernel/cpu/microcode/Makefile | 2 +- arch/x86/kernel/cpu/microcode/intel_staging.c | 100 ++++++++++++++++++ arch/x86/kernel/cpu/microcode/internal.h | 6 +- 3 files changed, 102 insertions(+), 6 deletions(-) create mode 100644 arch/x86/kernel/cpu/microcode/intel_staging.c diff --git a/arch/x86/kernel/cpu/microcode/Makefile b/arch/x86/kernel/cpu/m= icrocode/Makefile index 193d98b33a0a..a9f79aaffcb0 100644 --- a/arch/x86/kernel/cpu/microcode/Makefile +++ b/arch/x86/kernel/cpu/microcode/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only microcode-y :=3D core.o obj-$(CONFIG_MICROCODE) +=3D microcode.o -microcode-$(CONFIG_CPU_SUP_INTEL) +=3D intel.o +microcode-$(CONFIG_CPU_SUP_INTEL) +=3D intel.o intel_staging.o microcode-$(CONFIG_CPU_SUP_AMD) +=3D amd.o diff --git a/arch/x86/kernel/cpu/microcode/intel_staging.c b/arch/x86/kerne= l/cpu/microcode/intel_staging.c new file mode 100644 index 000000000000..2fc8667cab45 --- /dev/null +++ b/arch/x86/kernel/cpu/microcode/intel_staging.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#define pr_fmt(fmt) "microcode: " fmt +#include +#include + +#include "internal.h" + +#define MBOX_REG_NUM 4 +#define MBOX_REG_SIZE sizeof(u32) + +#define MBOX_CONTROL_OFFSET 0x0 +#define MBOX_STATUS_OFFSET 0x4 + +#define MASK_MBOX_CTRL_ABORT BIT(0) + +#define MASK_MBOX_STATUS_ERROR BIT(2) +#define MASK_MBOX_STATUS_READY BIT(31) + +#define MBOX_XACTION_LEN PAGE_SIZE +#define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2) +#define MBOX_XACTION_TIMEOUT (10 * MSEC_PER_SEC) + +#define STAGING_OFFSET_END 0xffffffff + +static inline void abort_xaction(void __iomem *base) +{ + writel(MASK_MBOX_CTRL_ABORT, base + MBOX_CONTROL_OFFSET); +} + +static void request_xaction(void __iomem *base, u32 *chunk, unsigned int c= hunksize) +{ + pr_debug_once("Need to implement staging mailbox loading code.\n"); +} + +static enum ucode_state wait_for_xaction(void __iomem *base) +{ + u32 timeout, status; + + for (timeout =3D 0; timeout < MBOX_XACTION_TIMEOUT; timeout++) { + msleep(1); + status =3D readl(base + MBOX_STATUS_OFFSET); + if (status & MASK_MBOX_STATUS_READY) + break; + } + + status =3D readl(base + MBOX_STATUS_OFFSET); + if (status & MASK_MBOX_STATUS_ERROR) + return UCODE_ERROR; + if (!(status & MASK_MBOX_STATUS_READY)) + return UCODE_TIMEOUT; + + return UCODE_OK; +} + +static enum ucode_state read_xaction_response(void __iomem *base, unsigned= int *offset) +{ + pr_debug_once("Need to implement staging response handler.\n"); + return UCODE_ERROR; +} + +static inline unsigned int get_chunksize(unsigned int totalsize, unsigned = int offset) +{ + WARN_ON_ONCE(totalsize < offset); + return min(MBOX_XACTION_LEN, totalsize - offset); +} + +enum ucode_state do_stage(u64 pa, void *ucode_ptr, unsigned int totalsize) +{ + unsigned int xaction_bytes =3D 0, offset =3D 0, chunksize; + void __iomem *mmio_base; + enum ucode_state state; + + mmio_base =3D ioremap(pa, MBOX_REG_NUM * MBOX_REG_SIZE); + if (WARN_ON_ONCE(!mmio_base)) + return UCODE_ERROR; + + abort_xaction(mmio_base); + + while (offset !=3D STAGING_OFFSET_END) { + chunksize =3D get_chunksize(totalsize, offset); + if (xaction_bytes + chunksize > MBOX_XACTION_MAX(totalsize)) { + state =3D UCODE_TIMEOUT; + break; + } + + request_xaction(mmio_base, ucode_ptr + offset, chunksize); + state =3D wait_for_xaction(mmio_base); + if (state !=3D UCODE_OK) + break; + + xaction_bytes +=3D chunksize; + state =3D read_xaction_response(mmio_base, &offset); + if (state !=3D UCODE_OK) + break; + } + + iounmap(mmio_base); + return state; +} diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 158429d80f93..787524e4ef1e 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -120,11 +120,7 @@ void load_ucode_intel_bsp(struct early_load_data *ed); void load_ucode_intel_ap(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); -static inline enum ucode_state do_stage(u64 pa, void *ucode_ptr, unsigned = int totalsize) -{ - pr_debug_once("Need to implement the staging code.\n"); - return UCODE_ERROR; -} +enum ucode_state do_stage(u64 pa, void *ucode_ptr, unsigned int totalsize); #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(struct early_load_data *ed) { } static inline void load_ucode_intel_ap(void) { } --=20 2.45.2 From nobody Sun Dec 14 08:06:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5676217C9E8 for ; Wed, 11 Dec 2024 01:42:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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10 Dec 2024 17:42:20 -0800 X-CSE-ConnectionGUID: mP4DrLrrT/WgJSGdouCOXA== X-CSE-MsgGUID: fhiTND9sSM+xWs8o4Fli2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="96051770" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.134.127]) by orviesa007.jf.intel.com with ESMTP; 10 Dec 2024 17:42:20 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 5/6] x86/microcode/intel_staging: Support mailbox data transfer Date: Tue, 10 Dec 2024 17:42:11 -0800 Message-ID: <20241211014213.3671-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211014213.3671-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> <20241211014213.3671-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The staging architecture features a narrowed interface for data transfer. Instead of allocating MMIO space based on data chunk size, it utilizes two data registers: one for reading and one for writing, enforcing the serialization of read and write operations. Additionally, it defines a mailbox data format. To facilitate data transfer, implement helper functions in line with this specified format for reading and writing staging data. This mailbox format is a customized version and is not compatible with the existing mailbox code, so reuse is not feasible. Signed-off-by: Chang S. Bae --- arch/x86/kernel/cpu/microcode/intel_staging.c | 55 ++++++++++++++++++- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel_staging.c b/arch/x86/kerne= l/cpu/microcode/intel_staging.c index 2fc8667cab45..eab6e891db9c 100644 --- a/arch/x86/kernel/cpu/microcode/intel_staging.c +++ b/arch/x86/kernel/cpu/microcode/intel_staging.c @@ -3,6 +3,7 @@ #define pr_fmt(fmt) "microcode: " fmt #include #include +#include =20 #include "internal.h" =20 @@ -11,17 +12,44 @@ =20 #define MBOX_CONTROL_OFFSET 0x0 #define MBOX_STATUS_OFFSET 0x4 +#define MBOX_WRDATA_OFFSET 0x8 +#define MBOX_RDDATA_OFFSET 0xc =20 #define MASK_MBOX_CTRL_ABORT BIT(0) +#define MASK_MBOX_CTRL_GO BIT(31) =20 #define MASK_MBOX_STATUS_ERROR BIT(2) #define MASK_MBOX_STATUS_READY BIT(31) =20 +#define MASK_MBOX_RESP_SUCCESS BIT(0) +#define MASK_MBOX_RESP_PROGRESS BIT(1) +#define MASK_MBOX_RESP_ERROR BIT(2) + +#define MBOX_CMD_LOAD 0x3 +#define MBOX_OBJ_STAGING 0xb +#define MBOX_HDR (PCI_VENDOR_ID_INTEL | (MBOX_OBJ_STAGING << 16)) +#define MBOX_HDR_SIZE 16 + #define MBOX_XACTION_LEN PAGE_SIZE #define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2) #define MBOX_XACTION_TIMEOUT (10 * MSEC_PER_SEC) =20 #define STAGING_OFFSET_END 0xffffffff +#define DWORD_SIZE(s) ((s) / sizeof(u32)) + +static inline u32 read_mbox_dword(void __iomem *base) +{ + u32 dword =3D readl(base + MBOX_RDDATA_OFFSET); + + /* Inform the read completion to the staging firmware */ + writel(0, base + MBOX_RDDATA_OFFSET); + return dword; +} + +static inline void write_mbox_dword(void __iomem *base, u32 dword) +{ + writel(dword, base + MBOX_WRDATA_OFFSET); +} =20 static inline void abort_xaction(void __iomem *base) { @@ -30,7 +58,18 @@ static inline void abort_xaction(void __iomem *base) =20 static void request_xaction(void __iomem *base, u32 *chunk, unsigned int c= hunksize) { - pr_debug_once("Need to implement staging mailbox loading code.\n"); + unsigned int i, dwsize =3D DWORD_SIZE(chunksize); + + write_mbox_dword(base, MBOX_HDR); + write_mbox_dword(base, dwsize + DWORD_SIZE(MBOX_HDR_SIZE)); + + write_mbox_dword(base, MBOX_CMD_LOAD); + write_mbox_dword(base, 0); + + for (i =3D 0; i < dwsize; i++) + write_mbox_dword(base, chunk[i]); + + writel(MASK_MBOX_CTRL_GO, base + MBOX_CONTROL_OFFSET); } =20 static enum ucode_state wait_for_xaction(void __iomem *base) @@ -55,8 +94,18 @@ static enum ucode_state wait_for_xaction(void __iomem *b= ase) =20 static enum ucode_state read_xaction_response(void __iomem *base, unsigned= int *offset) { - pr_debug_once("Need to implement staging response handler.\n"); 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d="scan'208";a="96051776" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.134.127]) by orviesa007.jf.intel.com with ESMTP; 10 Dec 2024 17:42:21 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH 6/6] x86/microcode/intel: Enable staging when available Date: Tue, 10 Dec 2024 17:42:12 -0800 Message-ID: <20241211014213.3671-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241211014213.3671-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> <20241211014213.3671-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the staging code being ready, check the relevant MSRs and set the feature chicken bit to allow staging to be invoked from the core microcode update process. Signed-off-by: Chang S. Bae --- RFC-V1 -> V1: Massage the enabling message. --- arch/x86/kernel/cpu/microcode/intel.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 325068bb5524..c988b6f8672f 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -674,6 +674,18 @@ static __init void calc_llc_size_per_core(struct cpuin= fo_x86 *c) llc_size_per_core =3D (unsigned int)llc_size; } =20 +static __init bool staging_available(void) +{ + u64 val; + + val =3D x86_read_arch_cap_msr(); + if (!(val & ARCH_CAP_MCU_ENUM)) + return false; + + rdmsrl(MSR_IA32_MCU_ENUMERATION, val); + return !!(val & MCU_STAGING); +} + struct microcode_ops * __init init_intel_microcode(void) { struct cpuinfo_x86 *c =3D &boot_cpu_data; @@ -684,6 +696,11 @@ struct microcode_ops * __init init_intel_microcode(voi= d) return NULL; } =20 + if (staging_available()) { + microcode_intel_ops.use_staging =3D true; + pr_info("Enabled staging feature.\n"); + } + calc_llc_size_per_core(c); =20 return µcode_intel_ops; --=20 2.45.2