From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B8971B3924; Tue, 10 Dec 2024 14:49:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842198; cv=none; b=njbq7upODUWwaECIOYKh2k5vGSA2jo5RrCHLeskevn5D6blQtssZC34Sf1wq5c9JAzQvf3kTldwXVfze1yuXo23UbxkPcvyGKNkw8BG31uEgO3U9f5W7g5Zu7njU8eI46IHXvjkfcurEbIY4bAPUvQu0KIGzLg6SgDqijuvfpZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842198; c=relaxed/simple; bh=RlkJX0MrhsJeOtYwbzKz9uU11pc4QQCMS9xkZOpuwfo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DkZXskzDVTbw6ZC4F0HqfuBI8q0XzYWSr/Hk4ksV2d3RmS/G0ADPFg7f/vhLEi3kqjj6XXSUBTE6ceM2pQfqGpWBihsfzoZFH1fA3KSTpHutcV5MHChKHNuxXavA3eG4xQnIw6bCwZyduprihWvuTKFIryQd3LmVU3WNLOjjJag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tpE22AAz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tpE22AAz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4BE3AC4CED6; Tue, 10 Dec 2024 14:49:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842197; bh=RlkJX0MrhsJeOtYwbzKz9uU11pc4QQCMS9xkZOpuwfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tpE22AAz8JnIoPsTCivKa+MP48cXGfDjPi6iVhnuTX92pP2L1fwFaF74b1AouRM3I hw8/z2N4/GHt3TxCzaLEefNkLiX4J0GHt7PqbhcWrZlmiHYF4ka7L2RoWqPgPWslTf ETjvJfCrMRH3W9uWYkTHS0dW6fMRvc43jmxIunnLCll0x6u3twOgvvadqUvUh7Znl4 2HOf4pGw3LfIJN0eI+mRrSKQ7RNA2oqwSfbnzsP1TK7ZkqYIlBxQvMuReZ3U+6Dx53 LFrQcZHE6+dM89gKR/EIsfsel/b+BJU8Yt5zwDE54ZFcDOsyUZjOxXbn/pdXUQDwf3 7I54gtiBA0Yhw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox , stable@vger.kernel.org Subject: [PATCH v2 01/11] x86/Kconfig: Geode CPU has cmpxchg8b Date: Tue, 10 Dec 2024 15:49:35 +0100 Message-Id: <20241210144945.2325330-2-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann An older cleanup of mine inadvertently removed geode-gx1 and geode-lx from the list of CPUs that are known to support a working cmpxchg8b. Fixes: 88a2b4edda3d ("x86/Kconfig: Rework CONFIG_X86_PAE dependency") Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig.cpu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..42e6a40876ea 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -368,7 +368,7 @@ config X86_HAVE_PAE =20 config X86_CMPXCHG64 def_bool y - depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 + depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 = || MGEODE_LX =20 # this should be set for all -march=3D.. options where the compiler # generates cmov. --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD6911B87FA for ; Tue, 10 Dec 2024 14:50:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842200; cv=none; b=bdHdRIGzV7XSy3vkSlYURxHTu+AjJM2/s+k2xpbRxqs3jsft6SNYg0d94ChvxaynG6XgbkaWynCu595zwReRDMvf4orFkakVBS8OOmWL8rrg7mYij14dLqAgnODue8V8I5/5cdruDS8W4yidV9uLr8LkQkJs1JFIKpALN5KB2aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842200; c=relaxed/simple; bh=b1cZNxiVFqQ5SFPUxXzkmZBB1Y/QaruM9Xym7kFraA4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NeOi35nGT1XUtOqcICLZSO2YqPG2rgsJp+lSuoeN0dfJpcg5Aed8aDxYt9mjydqfbFGyTYtuX09KWscIqoMV13Rl17yUaJ7nDm4rVXgshMBnMOO8CqS9Ez1htDnyP97rYQlH4HWkm57o9TPKNRYLgQiWZwVKLbtp2Igf+c3rcNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E0n6mJJC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E0n6mJJC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5AFC0C4CEE1; Tue, 10 Dec 2024 14:49:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842200; bh=b1cZNxiVFqQ5SFPUxXzkmZBB1Y/QaruM9Xym7kFraA4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E0n6mJJCvbUC587/rxwFXIuMXFpNrfF0MM7pMhse9yIUuIBmxFkO4ikkpHhfYZ6xT wu9qCzOrLCGEVorawCyPKd9+wrAMVVnvUv5+7jG+7cW1H62s6X/0u23jShvK+EuhCc vW2c2vl8PnhE6N+49H6X8zGX1bPwDpWl83g5L7qmiVqoz4uTl+n2hG9/Yi2tkJp+gy A962YfYiDupBaNz3AfyzbOqrSzoBP04eovyrFOkPivfutIi/dc9Sw/SfEZ5Y7to81K vaomqxSE9qkioN10dxsq2XVYbqMFvIEoO/XAtEztr5W8Pd5bObFKAh5QLaEKnpx7fI aT42/3SgHnj8A== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 02/11] x86: drop 32-bit "bigsmp" machine support Date: Tue, 10 Dec 2024 15:49:36 +0100 Message-Id: <20241210144945.2325330-3-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The x86-32 kernel used to support multiple platforms with more than eight logical CPUs, from the 1999-2003 timeframe: Sequent NUMA-Q, IBM Summit, Unisys ES7000 and HP F8. Support for all except the latter was dropped back in 2014, leaving only the F8 based DL740 and DL760 G2 machines in this catery, with up to eight single-core Socket-603 Xeon-MP processors with hyperthreading. Like the already removed machines, the HP F8 servers at the cost upwards of $100k in typical configurations, but were quickly obsoleted by their 64-bit Socket-604 cousins and the AMD Opteron. Earlier servers with up to 8 Pentium Pro or Xeon processors remain fully supported as they had no hyperthreading. Similarly, the more common 4-socket Xeon-MP machines with hyperthreading using Intel or ServerWorks chipsets continue to work without this, and all the multi-core Xeon processors also run 64-bit kernels. While the "bigsmp" support can also be used to run on later 64-bit machines (including VM guests), it seems best to discourage that and get any remaining users to update their kernels to 64-bit builds on these. As a side-effect of this, there is also no more need to support NUMA configurations on 32-bit x86, as all true 32-bit NUMA platforms are already gone. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- .../admin-guide/kernel-parameters.txt | 4 - arch/x86/Kconfig | 20 +--- arch/x86/kernel/apic/Makefile | 3 - arch/x86/kernel/apic/apic.c | 3 - arch/x86/kernel/apic/bigsmp_32.c | 105 ------------------ arch/x86/kernel/apic/local.h | 13 --- arch/x86/kernel/apic/probe_32.c | 29 ----- 7 files changed, 4 insertions(+), 173 deletions(-) delete mode 100644 arch/x86/kernel/apic/bigsmp_32.c diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index dc663c0ca670..eca370e99844 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -410,10 +410,6 @@ Format: { quiet (default) | verbose | debug } Change the amount of debugging information output when initialising the APIC and IO-APIC components. - For X86-32, this can also be used to specify an APIC - driver name. - Format: apic=3Ddriver_name - Examples: apic=3Dbigsmp =20 apic_extnmi=3D [APIC,X86,EARLY] External NMI delivery setting Format: { bsp (default) | all | none } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d7bd0ae48c4..42494739344d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -526,12 +526,6 @@ config X86_FRED ring transitions and exception/interrupt handling if the system supports it. =20 -config X86_BIGSMP - bool "Support for big SMP systems with more than 8 CPUs" - depends on SMP && X86_32 - help - This option is needed for the systems that have more than 8 CPUs. - config X86_EXTENDED_PLATFORM bool "Support for extended (non-PC) x86 platforms" default y @@ -730,8 +724,8 @@ config X86_32_NON_STANDARD depends on X86_32 && SMP depends on X86_EXTENDED_PLATFORM help - This option compiles in the bigsmp and STA2X11 default - subarchitectures. It is intended for a generic binary + This option compiles in the STA2X11 default + subarchitecture. It is intended for a generic binary kernel. If you select them all, kernel will probe it one by one and will fallback to default. =20 @@ -1008,8 +1002,7 @@ config NR_CPUS_RANGE_BEGIN config NR_CPUS_RANGE_END int depends on X86_32 - default 64 if SMP && X86_BIGSMP - default 8 if SMP && !X86_BIGSMP + default 8 if SMP default 1 if !SMP =20 config NR_CPUS_RANGE_END @@ -1022,7 +1015,6 @@ config NR_CPUS_RANGE_END config NR_CPUS_DEFAULT int depends on X86_32 - default 32 if X86_BIGSMP default 8 if SMP default 1 if !SMP =20 @@ -1568,8 +1560,7 @@ config AMD_MEM_ENCRYPT config NUMA bool "NUMA Memory Allocation and Scheduler Support" depends on SMP - depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP) - default y if X86_BIGSMP + depends on X86_64 select USE_PERCPU_NUMA_NODE_ID select OF_NUMA if OF help @@ -1582,9 +1573,6 @@ config NUMA For 64-bit this is recommended if the system is Intel Core i7 (or later), AMD Opteron, or EM64T NUMA. =20 - For 32-bit this is only needed if you boot a 32-bit - kernel on a 64-bit NUMA platform. - Otherwise, you should say N. =20 config AMD_NUMA diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile index 3bf0487cf3b7..52d1808ee360 100644 --- a/arch/x86/kernel/apic/Makefile +++ b/arch/x86/kernel/apic/Makefile @@ -23,8 +23,5 @@ obj-$(CONFIG_X86_X2APIC) +=3D x2apic_cluster.o obj-y +=3D apic_flat_64.o endif =20 -# APIC probe will depend on the listing order here -obj-$(CONFIG_X86_BIGSMP) +=3D bigsmp_32.o - # For 32bit, probe_32 need to be listed last obj-$(CONFIG_X86_LOCAL_APIC) +=3D probe_$(BITS).o diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index c5fb28e6451a..cb453bacf281 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1371,8 +1371,6 @@ void __init apic_intr_mode_init(void) =20 x86_64_probe_apic(); =20 - x86_32_install_bigsmp(); - if (x86_platform.apic_post_init) x86_platform.apic_post_init(); =20 @@ -1674,7 +1672,6 @@ static __init void apic_read_boot_cpu_id(bool x2apic) boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); } topology_register_boot_apic(boot_cpu_physical_apicid); - x86_32_probe_bigsmp_early(); } =20 #ifdef CONFIG_X86_X2APIC diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp= _32.c deleted file mode 100644 index 9285d500d5b4..000000000000 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs. - * - * Drives the local APIC in "clustered mode". - */ -#include -#include -#include - -#include -#include - -#include "local.h" - -static u32 bigsmp_get_apic_id(u32 x) -{ - return (x >> 24) & 0xFF; -} - -static void bigsmp_send_IPI_allbutself(int vector) -{ - default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector); -} - -static void bigsmp_send_IPI_all(int vector) -{ - default_send_IPI_mask_sequence_phys(cpu_online_mask, vector); -} - -static int dmi_bigsmp; /* can be set by dmi scanners */ - -static int hp_ht_bigsmp(const struct dmi_system_id *d) -{ - printk(KERN_NOTICE "%s detected: force use of apic=3Dbigsmp\n", d->ident); - dmi_bigsmp =3D 1; - - return 0; -} - - -static const struct dmi_system_id bigsmp_dmi_table[] =3D { - { hp_ht_bigsmp, "HP ProLiant DL760 G2", - { DMI_MATCH(DMI_BIOS_VENDOR, "HP"), - DMI_MATCH(DMI_BIOS_VERSION, "P44-"), - } - }, - - { hp_ht_bigsmp, "HP ProLiant DL740", - { DMI_MATCH(DMI_BIOS_VENDOR, "HP"), - DMI_MATCH(DMI_BIOS_VERSION, "P47-"), - } - }, - { } /* NULL entry stops DMI scanning */ -}; - -static int probe_bigsmp(void) -{ - return dmi_check_system(bigsmp_dmi_table); -} - -static struct apic apic_bigsmp __ro_after_init =3D { - - .name =3D "bigsmp", - .probe =3D probe_bigsmp, - - .dest_mode_logical =3D false, - - .disable_esr =3D 1, - - .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - - .max_apic_id =3D 0xFE, - .get_apic_id =3D bigsmp_get_apic_id, - - .calc_dest_apicid =3D apic_default_calc_apicid, - - .send_IPI =3D default_send_IPI_single_phys, - .send_IPI_mask =3D default_send_IPI_mask_sequence_phys, - .send_IPI_mask_allbutself =3D NULL, - .send_IPI_allbutself =3D bigsmp_send_IPI_allbutself, - .send_IPI_all =3D bigsmp_send_IPI_all, - .send_IPI_self =3D default_send_IPI_self, - - .read =3D native_apic_mem_read, - .write =3D native_apic_mem_write, - .eoi =3D native_apic_mem_eoi, - .icr_read =3D native_apic_icr_read, - .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, -}; - -bool __init apic_bigsmp_possible(bool cmdline_override) -{ - return apic =3D=3D &apic_bigsmp || !cmdline_override; -} - -void __init apic_bigsmp_force(void) -{ - if (apic !=3D &apic_bigsmp) - apic_install_driver(&apic_bigsmp); -} - -apic_driver(apic_bigsmp); diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 842fe28496be..bdcf609eb283 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -65,17 +65,4 @@ void default_send_IPI_self(int vector); void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); -void x86_32_probe_bigsmp_early(void); -void x86_32_install_bigsmp(void); -#else -static inline void x86_32_probe_bigsmp_early(void) { } -static inline void x86_32_install_bigsmp(void) { } -#endif - -#ifdef CONFIG_X86_BIGSMP -bool apic_bigsmp_possible(bool cmdline_selected); -void apic_bigsmp_force(void); -#else -static inline bool apic_bigsmp_possible(bool cmdline_selected) { return fa= lse; }; -static inline void apic_bigsmp_force(void) { } #endif diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_3= 2.c index f75ee345c02d..87bc9e7ca5d6 100644 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -93,35 +93,6 @@ static int __init parse_apic(char *arg) } early_param("apic", parse_apic); =20 -void __init x86_32_probe_bigsmp_early(void) -{ - if (nr_cpu_ids <=3D 8 || xen_pv_domain()) - return; - - if (IS_ENABLED(CONFIG_X86_BIGSMP)) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - if (!APIC_XAPIC(boot_cpu_apic_version)) - break; - /* P4 and above */ - fallthrough; - case X86_VENDOR_HYGON: - case X86_VENDOR_AMD: - if (apic_bigsmp_possible(cmdline_apic)) - return; - break; - } - } - pr_info("Limiting to 8 possible CPUs\n"); - set_nr_cpu_ids(8); -} - -void __init x86_32_install_bigsmp(void) -{ - if (nr_cpu_ids > 8 && !xen_pv_domain()) - apic_bigsmp_force(); -} - void __init x86_32_probe_apic(void) { if (!cmdline_apic) { --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F2D31BD51F for ; Tue, 10 Dec 2024 14:50:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842204; cv=none; b=Y5xwO7VJllMJEp0JVNFQZrdeheLH8EBW4U2ziM2bvFEg/c7uDlMdq6W4T94qHpt0j46Rt5FOpwQiQNz3rSJAaNnce6MeHeZkUE2foHSrsanbGi0dhWl7kz3/x9g1JVa9u0/0A9jHj24LFBjbsZC/imXLgcF5YlXlKA5r7wVKI8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842204; c=relaxed/simple; bh=RaOxny5lKPwI/fcP9pPId4nMHRz9abskR9v27E849o0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 03/11] x86: rework CONFIG_GENERIC_CPU compiler flags Date: Tue, 10 Dec 2024 15:49:37 +0100 Message-Id: <20241210144945.2325330-4-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann Building an x86-64 kernel with CONFIG_GENERIC_CPU is documented to run on all CPUs, but the Makefile does not actually pass an -march=3D argument, instead relying on the default that was used to configure the toolchain. In many cases, gcc will be configured to -march=3Dx86-64 or -march=3Dk8 for maximum compatibility, but in other cases a distribution default may be either raised to a more recent ISA, or set to -march=3Dnative to build for the CPU used for compilation. This still works in the case of building a custom kernel for the local machine. The point where it breaks down is building a kernel for another machine that is older the the default target. Changing the default to -march=3Dx86-64 would make it work reliable, but possibly produce worse code on distros that intentionally default to a newer ISA. To allow reliably building a kernel for either the oldest x86-64 CPUs, pass the -march=3Dx86-64 flag to the compiler. This was not possible in early versions of x86-64 gcc, but works on all currently supported versions down to at least gcc-5. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 5b773b34768d..5af3172fd51c 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -183,14 +183,14 @@ else cflags-$(CONFIG_MPSC) +=3D -march=3Dnocona cflags-$(CONFIG_MCORE2) +=3D -march=3Dcore2 cflags-$(CONFIG_MATOM) +=3D -march=3Datom - cflags-$(CONFIG_GENERIC_CPU) +=3D -mtune=3Dgeneric + cflags-$(CONFIG_GENERIC_CPU) +=3D -march=3Dx86-64 -mtune=3Dgeneric KBUILD_CFLAGS +=3D $(cflags-y) =20 rustflags-$(CONFIG_MK8) +=3D -Ctarget-cpu=3Dk8 rustflags-$(CONFIG_MPSC) +=3D -Ctarget-cpu=3Dnocona rustflags-$(CONFIG_MCORE2) +=3D -Ctarget-cpu=3Dcore2 rustflags-$(CONFIG_MATOM) +=3D -Ctarget-cpu=3Datom - rustflags-$(CONFIG_GENERIC_CPU) +=3D -Ztune-cpu=3Dgeneric + rustflags-$(CONFIG_GENERIC_CPU) +=3D -Ctarget-cpu=3Dx86-64 -Ztune-= cpu=3Dgeneric KBUILD_RUSTFLAGS +=3D $(rustflags-y) =20 KBUILD_CFLAGS +=3D -mno-red-zone --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 050211BD9FB for ; Tue, 10 Dec 2024 14:50:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842207; cv=none; b=mgw0QQprfe/u2Arf4c/R7imfePg0ZBqH2Ts4mkuqKWbAamtQt0zfAV7kb50nVIkaB2LWE/mAeCrAzjOGN5ATDLMgv7bE0uEVc40e/7XSGyhV1wDdh5IpC/dI3F0EotbV/ydKDIyHpA0tXsgywi/rE0hIFF6Hh8dJjhcOpFiTIg4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842207; c=relaxed/simple; bh=rrTm035FMZ6jPcTCYgwd6AAGCEWqVHAjB1QvrC4DWjE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dKsoNx8YCy84ATlpSmqY3VL2hoquIlKKO0GISSKpXUGu8aRMGBF+aM2182/wOTCPS4StZJryT2k+c1tbGczV1+htgTDiwnhZCCZhVOVCgIqLHreTSgUk5JiySyObLJzGq4lVSojHHhpfR2WQUuZiWZf/Nva9MO2NSPiolLhFmTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dmxbohrR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dmxbohrR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19B06C4CED6; Tue, 10 Dec 2024 14:50:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842206; bh=rrTm035FMZ6jPcTCYgwd6AAGCEWqVHAjB1QvrC4DWjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dmxbohrRU36Taua6XH9NdIsZHDe9nVl+CcBrjgbyaUrrYLoqLC4yWqNU7GbAIQ+ep MWZrtKNcJLJo2Di0csICa9L/WiV+EUjbEb/nkj1q2hiAlM0eNrL8zMpz2w1+J4pzcI z2uQukAKIdAtEybeZJW5/iRt6sY3urTJ+Wmrj8IBKqos4FVpKztHY/H95zBAS3v2q9 ntfDHH98aGQaxunGx7WGqOFhAqjuMhjeSZZxKbbBzb/JCxDXQMR1TGOFF73Zqa/IDw gvfFW9OMeqeRpsYA1q3W1cBn1RrydI2B+LhcpS9OQa99J2RpnpWwvpKGg1D7acjhbj agI5tLItGnFBw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 04/11] x86: drop configuration options for early 64-bit CPUs Date: Tue, 10 Dec 2024 15:49:38 +0100 Message-Id: <20241210144945.2325330-5-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The x86 CPU selection menu is confusing for a number of reasons: When configuring 32-bit kernels, it shows a small number of early 64-bit microarchitectures (K8, Core 2) but not the regular generic 64-bit target that is the normal default. There is no longer a reason to run 32-bit kernels on production 64-bit systems, so only actual 32-bit CPUs need to be shown here. When configuring 64-bit kernels, the options also pointless as there is no way to pick any CPU from the past 15 years, leaving GENERIC_CPU as the only sensible choice. Address both of the above by removing the obsolete options and making all 64-bit kernels run on both Intel and AMD CPUs from any generation. Testing generic 32-bit kernels on 64-bit hardware remains possible, just not building a 32-bit kernel that requires a 64-bit CPU. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig.cpu | 95 +++++---------------------------- arch/x86/Makefile | 16 +----- arch/x86/Makefile_32.cpu | 5 +- arch/x86/include/asm/vermagic.h | 4 -- drivers/misc/mei/Kconfig | 2 +- 5 files changed, 18 insertions(+), 104 deletions(-) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 42e6a40876ea..8fcb8ccee44b 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 # Put here option for CPU selection and depending optimization choice - prompt "Processor family" - default M686 if X86_32 - default GENERIC_CPU if X86_64 + prompt "x86-32 Processor family" + depends on X86_32 + default M686 help This is the processor type of your CPU. This information is used for optimizing purposes. In order to compile a kernel @@ -31,7 +31,6 @@ choice - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). - - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs. - "Crusoe" for the Transmeta Crusoe series. - "Efficeon" for the Transmeta Efficeon series. - "Winchip-C6" for original IDT Winchip. @@ -42,13 +41,10 @@ choice - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). - "VIA C7" for VIA C7. - - "Intel P4" for the Pentium 4/Netburst microarchitecture. - - "Core 2/newer Xeon" for all core2 and newer Intel CPUs. - "Intel Atom" for the Atom-microarchitecture CPUs. - - "Generic-x86-64" for a kernel which runs on any x86-64 CPU. =20 See each option's help text for additional details. If you don't know - what to do, choose "486". + what to do, choose "Pentium-Pro". =20 config M486SX bool "486SX" @@ -114,11 +110,11 @@ config MPENTIUMIII extensions. =20 config MPENTIUMM - bool "Pentium M" + bool "Pentium M/Pentium Dual Core/Core Solo/Core Duo" depends on X86_32 help Select this for Intel Pentium M (not Pentium-4 M) - notebook chips. + "Merom" Core Solo/Duo notebook chips =20 config MPENTIUM4 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" @@ -139,22 +135,10 @@ config MPENTIUM4 -Mobile Pentium 4 -Mobile Pentium 4 M -Extreme Edition (Gallatin) - -Prescott - -Prescott 2M - -Cedar Mill - -Presler - -Smithfiled Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: -Foster -Prestonia -Gallatin - -Nocona - -Irwindale - -Cranford - -Potomac - -Paxville - -Dempsey - =20 config MK6 bool "K6/K6-II/K6-III" @@ -172,13 +156,6 @@ config MK7 some extended instructions, and passes appropriate optimization flags to GCC. =20 -config MK8 - bool "Opteron/Athlon64/Hammer/K8" - help - Select this for an AMD Opteron or Athlon64 Hammer-family processor. - Enables use of some extended instructions, and passes appropriate - optimization flags to GCC. - config MCRUSOE bool "Crusoe" depends on X86_32 @@ -258,42 +235,14 @@ config MVIAC7 Select this for a VIA C7. Selecting this uses the correct cache shift and tells gcc to treat the CPU as a 686. =20 -config MPSC - bool "Intel P4 / older Netburst based Xeon" - depends on X86_64 - help - Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey - Xeon CPUs with Intel 64bit which is compatible with x86-64. - Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the - Netburst core and shouldn't use this option. You can distinguish them - using the cpu family field - in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. - -config MCORE2 - bool "Core 2/newer Xeon" - help - - Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and - 53xx) CPUs. You can distinguish newer from older Xeons by the CPU - family in /proc/cpuinfo. Newer ones have 6 and older ones 15 - (not a typo) - config MATOM bool "Intel Atom" help - Select this for the Intel Atom platform. Intel Atom CPUs have an in-order pipelining architecture and thus can benefit from accordingly optimized code. Use a recent GCC with specific Atom support in order to fully benefit from selecting this option. =20 -config GENERIC_CPU - bool "Generic-x86-64" - depends on X86_64 - help - Generic x86-64 CPU. - Run equally well on all x86-64 CPUs. - endchoice =20 config X86_GENERIC @@ -317,8 +266,8 @@ config X86_INTERNODE_CACHE_SHIFT =20 config X86_L1_CACHE_SHIFT int - default "7" if MPENTIUM4 || MPSC - default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X8= 6_GENERIC || GENERIC_CPU + default "7" if MPENTIUM4 + default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_= 64 default "4" if MELAN || M486SX || M486 || MGEODEGX1 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIX= III || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M5= 86 || MVIAC3_2 || MGEODE_LX =20 @@ -336,35 +285,19 @@ config X86_ALIGNMENT_16 =20 config X86_INTEL_USERCOPY def_bool y - depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX= || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 + depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX= || X86_GENERIC || MK7 || MEFFICEON =20 config X86_USE_PPRO_CHECKSUM def_bool y - depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIU= M4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || = MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM - -# -# P6_NOPs are a relatively minor optimization that require a family >=3D -# 6 processor, except that it is broken on certain VIA chips. -# Furthermore, AMD chips prefer a totally different sequence of NOPs -# (which work on all CPUs). In addition, it looks like Virtual PC -# does not understand them. -# -# As a result, disallow these if we're not compiling for X86_64 (these -# NOPs do work on all x86-64 capable chips); the list of processors in -# the right-hand clause are the cores that benefit from this optimization. -# -config X86_P6_NOP - def_bool y - depends on X86_64 - depends on (MCORE2 || MPENTIUM4 || MPSC) + depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIU= M4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 = || MEFFICEON || MGEODE_LX || MATOM =20 config X86_TSC def_bool y - depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6= || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX = || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2= || MATOM) || X86_64 + depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6= || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX = || M586TSC || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MATOM) || X86= _64 =20 config X86_HAVE_PAE def_bool y - depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC7 || MCORE2 || MATOM || X= 86_64 + depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64 =20 config X86_CMPXCHG64 def_bool y @@ -374,12 +307,12 @@ config X86_CMPXCHG64 # generates cmov. config X86_CMOV def_bool y - depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII= || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86= _64 || MATOM || MGEODE_LX) + depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII ||= M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX |= | X86_64) =20 config X86_MINIMUM_CPU_FAMILY int default "64" if X86_64 - default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTI= UMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 |= | MK8) + default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTI= UMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MK7) default "5" if X86_32 && X86_CMPXCHG64 default "4" =20 diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 5af3172fd51c..8120085b00a4 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -178,20 +178,8 @@ else # Use -mskip-rax-setup if supported. KBUILD_CFLAGS +=3D $(call cc-option,-mskip-rax-setup) =20 - # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) - cflags-$(CONFIG_MK8) +=3D -march=3Dk8 - cflags-$(CONFIG_MPSC) +=3D -march=3Dnocona - cflags-$(CONFIG_MCORE2) +=3D -march=3Dcore2 - cflags-$(CONFIG_MATOM) +=3D -march=3Datom - cflags-$(CONFIG_GENERIC_CPU) +=3D -march=3Dx86-64 -mtune=3Dgeneric - KBUILD_CFLAGS +=3D $(cflags-y) - - rustflags-$(CONFIG_MK8) +=3D -Ctarget-cpu=3Dk8 - rustflags-$(CONFIG_MPSC) +=3D -Ctarget-cpu=3Dnocona - rustflags-$(CONFIG_MCORE2) +=3D -Ctarget-cpu=3Dcore2 - rustflags-$(CONFIG_MATOM) +=3D -Ctarget-cpu=3Datom - rustflags-$(CONFIG_GENERIC_CPU) +=3D -Ctarget-cpu=3Dx86-64 -Ztune-= cpu=3Dgeneric - KBUILD_RUSTFLAGS +=3D $(rustflags-y) + KBUILD_CFLAGS +=3D -march=3Dx86-64 -mtune=3Dgeneric + KBUILD_RUSTFLAGS +=3D -Ctarget-cpu=3Dx86-64 -Ztune-cpu=3Dgeneric =20 KBUILD_CFLAGS +=3D -mno-red-zone KBUILD_CFLAGS +=3D -mcmodel=3Dkernel diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu index 94834c4b5e5e..af7de9a42752 100644 --- a/arch/x86/Makefile_32.cpu +++ b/arch/x86/Makefile_32.cpu @@ -24,7 +24,6 @@ cflags-$(CONFIG_MK6) +=3D -march=3Dk6 # Please note, that patches that add -march=3Dathlon-xp and friends are po= intless. # They make zero difference whatsosever to performance at this time. cflags-$(CONFIG_MK7) +=3D -march=3Dathlon -cflags-$(CONFIG_MK8) +=3D $(call cc-option,-march=3Dk8,-march=3Dathlon) cflags-$(CONFIG_MCRUSOE) +=3D -march=3Di686 $(align) cflags-$(CONFIG_MEFFICEON) +=3D -march=3Di686 $(call tune,pentium3) $(alig= n) cflags-$(CONFIG_MWINCHIPC6) +=3D $(call cc-option,-march=3Dwinchip-c6,-mar= ch=3Di586) @@ -32,9 +31,7 @@ cflags-$(CONFIG_MWINCHIP3D) +=3D $(call cc-option,-march= =3Dwinchip2,-march=3Di586) cflags-$(CONFIG_MCYRIXIII) +=3D $(call cc-option,-march=3Dc3,-march=3Di486= ) $(align) cflags-$(CONFIG_MVIAC3_2) +=3D $(call cc-option,-march=3Dc3-2,-march=3Di68= 6) cflags-$(CONFIG_MVIAC7) +=3D -march=3Di686 -cflags-$(CONFIG_MCORE2) +=3D -march=3Di686 $(call tune,core2) -cflags-$(CONFIG_MATOM) +=3D $(call cc-option,-march=3Datom,$(call cc-opti= on,-march=3Dcore2,-march=3Di686)) \ - $(call cc-option,-mtune=3Datom,$(call cc-option,-mtune=3Dgeneric)) +cflags-$(CONFIG_MATOM) +=3D -march=3Datom =20 # AMD Elan support cflags-$(CONFIG_MELAN) +=3D -march=3Di486 diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagi= c.h index 75884d2cdec3..5d471253c755 100644 --- a/arch/x86/include/asm/vermagic.h +++ b/arch/x86/include/asm/vermagic.h @@ -15,8 +15,6 @@ #define MODULE_PROC_FAMILY "586TSC " #elif defined CONFIG_M586MMX #define MODULE_PROC_FAMILY "586MMX " -#elif defined CONFIG_MCORE2 -#define MODULE_PROC_FAMILY "CORE2 " #elif defined CONFIG_MATOM #define MODULE_PROC_FAMILY "ATOM " #elif defined CONFIG_M686 @@ -33,8 +31,6 @@ #define MODULE_PROC_FAMILY "K6 " #elif defined CONFIG_MK7 #define MODULE_PROC_FAMILY "K7 " -#elif defined CONFIG_MK8 -#define MODULE_PROC_FAMILY "K8 " #elif defined CONFIG_MELAN #define MODULE_PROC_FAMILY "ELAN " #elif defined CONFIG_MCRUSOE diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 67d9391f1855..7575fee96cc6 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -3,7 +3,7 @@ config INTEL_MEI tristate "Intel Management Engine Interface" depends on X86 && PCI - default GENERIC_CPU || MCORE2 || MATOM || X86_GENERIC + default X86_64 || MATOM help The Intel Management Engine (Intel ME) provides Manageability, Security and Media services for system containing Intel chipsets. --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6EA91BE86A for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GZujiaCE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED0BAC4CEDE; Tue, 10 Dec 2024 14:50:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842209; bh=hRlH4NBVNwGhJ1JpNPALCjGk3CXpM7yv7jTBCNwOqX4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GZujiaCEMkCIsTyMDSjPEg9/x3UV3riCwi9DlqVmH2yWvCHcW3+ks+7jw15JcstKo Kyh9OaufWOE+DhWbUKiYUV2pOtrzbyoJPBXHqGCm6JkiPiku/1BOwCVSuSfNnVlLI1 AwU3DYpss7wqr8h2VCynpaS1d1ZGJaqyf3N4h5AacfOy3No8t5knnFyzm4sEL5iQjF KSQ7p4mNdG+I5JYxVWgB1BQc2IJ/y+DD3otaQTXF0H/Y5V/zlcGR3jCEpeYGpOUEQP yvruMzJvEKcAYuBWZMjHPtrKi2tcAemNkCb99bPHVrQOO9BUk776TfxxStF/yqqgnP Sm1Z5+W+DcMog== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option Date: Tue, 10 Dec 2024 15:49:39 +0100 Message-Id: <20241210144945.2325330-6-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann As a replacement for the obsole MK8/MPSC/MCORE2 configuration options, allow building a specialized kernel for the local CPU, which is useful for users building their own kernels, and does not require maintaining a list of possible CPU options. Between -march=3Dnative and -mtune=3Dnative, I pick the former in order to give the best performance through the use of extra instructions, but at the cost of not being able to run on older CPUs at all. This creates a small risk of running into illegal instruction faults when the resulting binary ends up being run on a machine other than the one it was built on. Link: https://lore.kernel.org/lkml/CAHk-=3Dwji1sV93yKbc=3D=3DZ7OSSHBiDE=3DL= AdG_d5Y-zPBrnSs0k2A@mail.gmail.com/ Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig.cpu | 14 ++++++++++++++ arch/x86/Makefile | 5 +++++ 2 files changed, 19 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 8fcb8ccee44b..d634b163e913 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -257,6 +257,20 @@ config X86_GENERIC This is really intended for distributors who need more generic optimizations. =20 +config X86_64_NATIVE + bool "Build with -march=3Dnative optimization" + depends on X86_64 + help + Make it possible to have a slightly better optimized kernel for + the machine it is built on, by passing -march=3Dnative instead + the more generic -march=3Dx86-64 option. This lets compilers + use extensions to the x86-64 instruction set that were not + present in the original AMD Opteron and Intel Pentium4 CPUs, + and schedule instructions for the pipeline model. + + Select this option only when building a kernel to run locally, + as it may be incompatible with any other processor. + # # Define implied options from the CPU selection here config X86_INTERNODE_CACHE_SHIFT diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 8120085b00a4..bf45b84c138f 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -178,8 +178,13 @@ else # Use -mskip-rax-setup if supported. KBUILD_CFLAGS +=3D $(call cc-option,-mskip-rax-setup) =20 +ifdef CONFIG_X86_64_NATIVE + KBUILD_CFLAGS +=3D -march=3Dnative + KBUILD_RUSTFLAGS +=3D -Ctarget-cpu=3Dnative +else KBUILD_CFLAGS +=3D -march=3Dx86-64 -mtune=3Dgeneric KBUILD_RUSTFLAGS +=3D -Ctarget-cpu=3Dx86-64 -Ztune-cpu=3Dgeneric +endif =20 KBUILD_CFLAGS +=3D -mno-red-zone KBUILD_CFLAGS +=3D -mcmodel=3Dkernel --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B00011C07D8 for ; Tue, 10 Dec 2024 14:50:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842212; cv=none; b=SCzPAjw2XGGAjNdd7G3oS0QT/0reMw+iBoILlCkrGrOGpcXFA+ewkLk2l+6Jn5dmPGWB6j5nXq/ayqP9j/FLbvp49yC0GTwqhg43T24/T3zJU1GRMyE7GV68fX1GZOWPk2ImXUfq7BCe0P0LXv4My44Phq/HDALOnretaAqV4S4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842212; c=relaxed/simple; bh=bA380iQhHgz8R6aVv9J8t3S9BKJOjC/mxtAeEnuhehM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ELoGpPo0Ux7Wk8SYLXag97F4Z/OoOPYiWZytz2yIItYg5rYTnB02i285PNjHzeDmfT3pm27yRKjLTnWrGZS8gx+QzFwlsyP/VOHgJsuv0tO7mAlVDKOUqKUFtRJChPhYVz9xlSBORz17hbsOTAqXqhK5FbVldOKPjnyam+Upo10= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TYVZwvsn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TYVZwvsn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CFB8AC4CED6; Tue, 10 Dec 2024 14:50:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842212; bh=bA380iQhHgz8R6aVv9J8t3S9BKJOjC/mxtAeEnuhehM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TYVZwvsncwbJHJei23pw/Nc9Wnwk5Ndk4nHauupXYi2Piw7MgXhq40CtgHk98ctPz YfBmZA+BT/iODJ98k31YtPaID+JZ+C32mMVzcXWsvsKdj5quu40rJEx5DVsrxG90e4 SyxjKDzl1hXr81Ca5rDD2yq6pQ9XpVoM0u2WE2H1EndTu8EV5/V0wEm6d8sACOS6cF sVD6HQGh69/pmwqSEsTvzkh9OOA4Q40J+BQqrWjixxpsagAyi6ceYaJlOhK/bxno1e lHqh6LOj26922jrCCZWQEgyJb+jOoPX2+PRSyrIHbpo6xZfsDJL+XSPYuvYHceuLdA lUL9yrUykoiMw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 06/11] x86: remove HIGHMEM64G support Date: Tue, 10 Dec 2024 15:49:40 +0100 Message-Id: <20241210144945.2325330-7-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The HIGHMEM64G support was added in linux-2.3.25 to support (then) high-end Pentium Pro and Pentium III Xeon servers with more than 4GB of addressing, NUMA and PCI-X slots started appearing. I have found no evidence of this ever being used in regular dual-socket servers or consumer devices, all the users seem obsolete these days, even by i386 standards: - Support for NUMA servers (NUMA-Q, IBM x440, unisys) was already removed ten years ago. - 4+ socket non-NUMA servers based on Intel 450GX/450NX, HP F8 and ServerWorks ServerSet/GrandChampion could theoretically still work with 8GB, but these were exceptionally rare even 20 years ago and would have usually been equipped with than the maximum amount of RAM. - Some SKUs of the Celeron D from 2004 had 64-bit mode fused off but could still work in a Socket 775 mainboard designed for the later Core 2 Duo and 8GB. Apparently most BIOSes at the time only allowed 64-bit CPUs. - In the early days of x86-64 hardware, there was sometimes the need to run a 32-bit kernel to work around bugs in the hardware drivers, or in the syscall emulation for 32-bit userspace. This likely still works but there should never be a need for this any more. PAE mode is still required to get access to the 'NX' bit on Atom 'Pentium M' and 'Core Duo' CPUs. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- Documentation/admin-guide/kdump/kdump.rst | 4 -- Documentation/arch/x86/usb-legacy-support.rst | 11 +---- arch/x86/Kconfig | 46 +++---------------- arch/x86/configs/xen.config | 2 - arch/x86/include/asm/page_32_types.h | 4 +- arch/x86/mm/init_32.c | 9 +--- 6 files changed, 11 insertions(+), 65 deletions(-) diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admi= n-guide/kdump/kdump.rst index 5376890adbeb..1f7f14c6e184 100644 --- a/Documentation/admin-guide/kdump/kdump.rst +++ b/Documentation/admin-guide/kdump/kdump.rst @@ -180,10 +180,6 @@ Dump-capture kernel config options (Arch Dependent, i3= 86 and x86_64) 1) On i386, enable high memory support under "Processor type and features":: =20 - CONFIG_HIGHMEM64G=3Dy - - or:: - CONFIG_HIGHMEM4G =20 2) With CONFIG_SMP=3Dy, usually nr_cpus=3D1 need specified on the kernel diff --git a/Documentation/arch/x86/usb-legacy-support.rst b/Documentation/= arch/x86/usb-legacy-support.rst index e01c08b7c981..b17bf122270a 100644 --- a/Documentation/arch/x86/usb-legacy-support.rst +++ b/Documentation/arch/x86/usb-legacy-support.rst @@ -20,11 +20,7 @@ It has several drawbacks, though: features (wheel, extra buttons, touchpad mode) of the real PS/2 mouse m= ay not be available. =20 -2) If CONFIG_HIGHMEM64G is enabled, the PS/2 mouse emulation can cause - system crashes, because the SMM BIOS is not expecting to be in PAE mode. - The Intel E7505 is a typical machine where this happens. - -3) If AMD64 64-bit mode is enabled, again system crashes often happen, +2) If AMD64 64-bit mode is enabled, again system crashes often happen, because the SMM BIOS isn't expecting the CPU to be in 64-bit mode. The BIOS manufacturers only test with Windows, and Windows doesn't do 64-bit yet. @@ -38,11 +34,6 @@ Problem 1) compiled-in, too. =20 Problem 2) - can currently only be solved by either disabling HIGHMEM64G - in the kernel config or USB Legacy support in the BIOS. A BIOS update - could help, but so far no such update exists. - -Problem 3) is usually fixed by a BIOS update. Check the board manufacturers web site. If an update is not available, disable USB Legacy support in the BIOS. If this alone doesn't help, try also adding diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 42494739344d..b373db8a8176 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1383,15 +1383,11 @@ config X86_CPUID with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to /dev/cpu/31/cpuid. =20 -choice - prompt "High Memory Support" - default HIGHMEM4G +config HIGHMEM4G + bool "High Memory Support" depends on X86_32 - -config NOHIGHMEM - bool "off" help - Linux can use up to 64 Gigabytes of physical memory on x86 systems. + Linux can use up to 4 Gigabytes of physical memory on x86 systems. However, the address space of 32-bit x86 processors is only 4 Gigabytes large. That means that, if you have a large amount of physical memory, not all of it can be "permanently mapped" by the @@ -1407,38 +1403,9 @@ config NOHIGHMEM possible. =20 If the machine has between 1 and 4 Gigabytes physical RAM, then - answer "4GB" here. + answer "Y" here. =20 - If more than 4 Gigabytes is used then answer "64GB" here. This - selection turns Intel PAE (Physical Address Extension) mode on. - PAE implements 3-level paging on IA32 processors. PAE is fully - supported by Linux, PAE mode is implemented on all recent Intel - processors (Pentium Pro and better). NOTE: If you say "64GB" here, - then the kernel will not boot on CPUs that don't support PAE! - - The actual amount of total physical memory will either be - auto detected or can be forced by using a kernel command line option - such as "mem=3D256M". (Try "man bootparam" or see the documentation of - your boot loader (lilo or loadlin) about how to pass options to the - kernel at boot time.) - - If unsure, say "off". - -config HIGHMEM4G - bool "4GB" - help - Select this if you have a 32-bit processor and between 1 and 4 - gigabytes of physical RAM. - -config HIGHMEM64G - bool "64GB" - depends on X86_HAVE_PAE - select X86_PAE - help - Select this if you have a 32-bit processor and more than 4 - gigabytes of physical RAM. - -endchoice + If unsure, say N. =20 choice prompt "Memory split" if EXPERT @@ -1484,8 +1451,7 @@ config PAGE_OFFSET depends on X86_32 =20 config HIGHMEM - def_bool y - depends on X86_32 && (HIGHMEM64G || HIGHMEM4G) + def_bool HIGHMEM4G =20 config X86_PAE bool "PAE (Physical Address Extension) Support" diff --git a/arch/x86/configs/xen.config b/arch/x86/configs/xen.config index 581296255b39..d5d091e03bd3 100644 --- a/arch/x86/configs/xen.config +++ b/arch/x86/configs/xen.config @@ -1,6 +1,4 @@ # global x86 required specific stuff -# On 32-bit HIGHMEM4G is not allowed -CONFIG_HIGHMEM64G=3Dy CONFIG_64BIT=3Dy =20 # These enable us to allow some of the diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/pa= ge_32_types.h index faf9cc1c14bb..25c32652f404 100644 --- a/arch/x86/include/asm/page_32_types.h +++ b/arch/x86/include/asm/page_32_types.h @@ -11,8 +11,8 @@ * a virtual address space of one gigabyte, which limits the * amount of physical memory you can use to about 950MB. * - * If you want more physical memory than this then see the CONFIG_HIGHMEM4G - * and CONFIG_HIGHMEM64G options in the kernel configuration. + * If you want more physical memory than this then see the CONFIG_VMSPLIT_= 2G + * and CONFIG_HIGHMEM4G options in the kernel configuration. */ #define __PAGE_OFFSET_BASE _AC(CONFIG_PAGE_OFFSET, UL) #define __PAGE_OFFSET __PAGE_OFFSET_BASE diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index ac41b1e0940d..f288aad8dc74 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -582,7 +582,7 @@ static void __init lowmem_pfn_init(void) "only %luMB highmem pages available, ignoring highmem size of %luMB!\n" =20 #define MSG_HIGHMEM_TRIMMED \ - "Warning: only 4GB will be used. Use a HIGHMEM64G enabled kernel!\n" + "Warning: only 4GB will be used. Support for for CONFIG_HIGHMEM64G was re= moved!\n" /* * We have more RAM than fits into lowmem - we try to put it into * highmem, also taking the highmem=3Dx boot parameter into account: @@ -606,18 +606,13 @@ static void __init highmem_pfn_init(void) #ifndef CONFIG_HIGHMEM /* Maximum memory usable is what is directly addressable */ printk(KERN_WARNING "Warning only %ldMB will be used.\n", MAXMEM>>20); - if (max_pfn > MAX_NONPAE_PFN) - printk(KERN_WARNING "Use a HIGHMEM64G enabled kernel.\n"); - else - printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n"); + printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n"); max_pfn =3D MAXMEM_PFN; #else /* !CONFIG_HIGHMEM */ -#ifndef CONFIG_HIGHMEM64G if (max_pfn > MAX_NONPAE_PFN) { max_pfn =3D MAX_NONPAE_PFN; printk(KERN_WARNING MSG_HIGHMEM_TRIMMED); } -#endif /* !CONFIG_HIGHMEM64G */ #endif /* !CONFIG_HIGHMEM */ } =20 --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DFA61B2190 for ; Tue, 10 Dec 2024 14:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842215; cv=none; b=cD1oyxx5/wo6nb0AH+t1zWTilTTDqVGC/LRaIOeQoEMKYkKc31P68xi6ixEEvkgDBwt8pMv5dveJl4QCnL4PUgVBDhGUuTsVaJSgWSZtxnQ4kjhKRTPpinSIMEtzxfCjNfSqDHqcbk8/VwD9A+CYpM5BndDOJJc0jrhojj1eQfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842215; c=relaxed/simple; bh=mSDYe3/14oT8+6+Q/fUZOhctfsyXb85zYziAFN+aro0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=irGmeh/iMK+YZHrN51kZj3A6TwDemC8/ii9JbV5uX8nbQPGaE9NP2cmwDeaJd5wpmlV65ph1CiP0/hEIOIIqXGIcb/zdDJZdsyVArOvqwsILkTqdC9wWQHWnuzJLgAb2cW+Hq3cTv210bUX3QkRg4/4Vjzolwz36uUilQ+JZjeo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KUNhEXNz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KUNhEXNz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2EB4C4CEDE; Tue, 10 Dec 2024 14:50:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842215; bh=mSDYe3/14oT8+6+Q/fUZOhctfsyXb85zYziAFN+aro0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KUNhEXNzRItzOf7iLFdJoFQ9ZK6ngWKC/R0qyrZEixwhSuN2uLJkBDkQlXpv7UWLz 553xgOtzcLJrNmZQ2SY2t7YX3lrqUpg4qh5dVbjBn4BIPuWid2WiEbiuRtwEuVuArN BTrLqJGiVYkpA9kC16t4q0oC3LkE4DLjrMvHT5on9n2i82Xn7baI8NWh26bcR2gQWr zZKZgs8ShX3TUgK7RDePIKDd4FsrKBNkrtnhuIikzHpUJAl0xCz4O87JQWStAL+p8X P20wzoKJQ4/jdAjkGSBLkbu5Tl1VPzrXl4yp9hxggo1JxRqkuSlxljwXQr0xJNvmjJ l4pnhc1xnSt+Q== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE Date: Tue, 10 Dec 2024 15:49:41 +0100 Message-Id: <20241210144945.2325330-8-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann Since kernels with and without CONFIG_X86_PAE are now limited to the low 4GB of physical address space, there is no need to use either swiotlb or 64-bit phys_addr_t any more, so stop selecting these and fix up the build warnings from that. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig | 2 -- arch/x86/mm/pgtable.c | 5 +++-- include/linux/mm.h | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b373db8a8176..d0d055f6f56e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1456,8 +1456,6 @@ config HIGHMEM config X86_PAE bool "PAE (Physical Address Extension) Support" depends on X86_32 && X86_HAVE_PAE - select PHYS_ADDR_T_64BIT - select SWIOTLB help PAE is required for NX support, and furthermore enables larger swapspace support for non-overcommit purposes. It diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 5745a354a241..b8f9e69b25c1 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -765,11 +765,12 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot= _t prot) int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) { u8 uniform; + struct resource res =3D DEFINE_RES_MEM(addr, PMD_SIZE); =20 mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); if (!uniform) { - pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-pag= e mapping due to MTRR override.\n", - __func__, addr, addr + PMD_SIZE); + pr_warn_once("%s: Cannot satisfy %pR with a huge-page mapping due to MTR= R override.\n", + __func__, &res); return 0; } =20 diff --git a/include/linux/mm.h b/include/linux/mm.h index c39c4945946c..7725e9e46e90 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -99,7 +99,7 @@ extern int mmap_rnd_compat_bits __read_mostly; =20 #ifndef DIRECT_MAP_PHYSMEM_END # ifdef MAX_PHYSMEM_BITS -# define DIRECT_MAP_PHYSMEM_END ((1ULL << MAX_PHYSMEM_BITS) - 1) +# define DIRECT_MAP_PHYSMEM_END (phys_addr_t)((1ULL << MAX_PHYSMEM_BITS) -= 1) # else # define DIRECT_MAP_PHYSMEM_END (((phys_addr_t)-1)&~(1ULL<<63)) # endif --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 769401AAE25 for ; Tue, 10 Dec 2024 14:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842219; cv=none; b=hKrU3HSk1DZfnVJWqSCDeOsL+XBVEIcK8gEHWSuZC8yrVZSbg5RuheVnmEyk7DqLpRVWO2sPxdzmVCgF6A/UJgiZ998skT6p3usJFsMh6TZJAwybrHtACqdtgKEhsBr8gMsjQEht+vQV4JrSXtXK/FiECZtz50JoX/l3m+Z5eh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842219; c=relaxed/simple; bh=GRqjA+rpBHOuSjrsnumnoiqHxjJy3xN3vZ5oljrS+jM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CDsLNyZSGF94EK2SVJpfRdpZloomffjLKHxSVQarSLB+sRC/G4szoKLG6Dx68Cura3rAf32CF8w4wzOthyYTK6Roz4d1NVyPDfB9tKJv+zbuSg8D2407wozfkEoeYCGkWIm4Ovwgwe4mFqcoxWTJarwr+fNZm4vsQUTYtjEnR80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c0ah19co; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c0ah19co" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91B7BC4CED6; Tue, 10 Dec 2024 14:50:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842218; bh=GRqjA+rpBHOuSjrsnumnoiqHxjJy3xN3vZ5oljrS+jM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c0ah19coPDOz8KHkIoNiQI90fZNo2HYPDoX4iUF92AxvldBLQA5G4x+2DwMZCTwFb z+sUTtDgtKpwXtmO/5YrrBi3wUjEb6gcGLh3cpHBeMlZR0QY1ZN5uZoevIzDU0uez4 qP15rPuUu4OO0CD4wfyXCbKrWf0ZLB2QguP28qp41VCjWopL9c+s0ry539OWfV6Ti7 wWSVMImmikNQTwyQtnC9SA0YCiGR7QH7RIjV57XP9wxp7KGzSSmPqx3/ejlP5lA0sd CK36lvo+ygKj++p16ZRtdMlAz67oMFItJfWyfvrzE9eOdVZR7kmPZWCr7LsrR2xkxN kXRRYdr+c6XQw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 08/11] x86: drop support for CONFIG_HIGHPTE Date: Tue, 10 Dec 2024 15:49:42 +0100 Message-Id: <20241210144945.2325330-9-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann With the maximum amount of RAM now 4GB, there is very little point to still have PTE pages in highmem. Drop this for simplification. The only other architecture supporting HIGHPTE is 32-bit arm, and once that feature is removed as well, the highpte logic can be dropped from common code as well. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- .../admin-guide/kernel-parameters.txt | 7 ----- arch/x86/Kconfig | 9 ------- arch/x86/include/asm/pgalloc.h | 5 ---- arch/x86/mm/pgtable.c | 27 +------------------ 4 files changed, 1 insertion(+), 47 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index eca370e99844..cf25853a5c4a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -7341,13 +7341,6 @@ 16 - SIGBUS faults Example: user_debug=3D31 =20 - userpte=3D - [X86,EARLY] Flags controlling user PTE allocations. - - nohigh =3D do not allocate PTE pages in - HIGHMEM regardless of setting - of CONFIG_HIGHPTE. - vdso=3D [X86,SH,SPARC] On X86_32, this is an alias for vdso32=3D. Otherwise: =20 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d0d055f6f56e..d8a8bf9ea9b9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1621,15 +1621,6 @@ config X86_PMEM_LEGACY =20 Say Y if unsure. =20 -config HIGHPTE - bool "Allocate 3rd-level pagetables from highmem" - depends on HIGHMEM - help - The VM uses one page table entry for each page of physical memory. - For systems with a lot of RAM, this can be wasteful of precious - low memory. Setting this option will put user-space page table - entries in high memory. - config X86_CHECK_BIOS_CORRUPTION bool "Check for low memory corruption" help diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h index dcd836b59beb..582cf5b7ec8c 100644 --- a/arch/x86/include/asm/pgalloc.h +++ b/arch/x86/include/asm/pgalloc.h @@ -29,11 +29,6 @@ static inline void paravirt_release_pud(unsigned long pf= n) {} static inline void paravirt_release_p4d(unsigned long pfn) {} #endif =20 -/* - * Flags to use when allocating a user page table page. - */ -extern gfp_t __userpte_alloc_gfp; - #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION /* * Instead of one PGD, we acquire two PGDs. Being order-1, it is diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index b8f9e69b25c1..3d7072aec486 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -12,12 +12,6 @@ phys_addr_t physical_mask __ro_after_init =3D (1ULL << _= _PHYSICAL_MASK_SHIFT) - 1; EXPORT_SYMBOL(physical_mask); #endif =20 -#ifdef CONFIG_HIGHPTE -#define PGTABLE_HIGHMEM __GFP_HIGHMEM -#else -#define PGTABLE_HIGHMEM 0 -#endif - #ifndef CONFIG_PARAVIRT static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) @@ -26,29 +20,10 @@ void paravirt_tlb_remove_table(struct mmu_gather *tlb, = void *table) } #endif =20 -gfp_t __userpte_alloc_gfp =3D GFP_PGTABLE_USER | PGTABLE_HIGHMEM; - pgtable_t pte_alloc_one(struct mm_struct *mm) { - return __pte_alloc_one(mm, __userpte_alloc_gfp); -} - -static int __init setup_userpte(char *arg) -{ - if (!arg) - return -EINVAL; - - /* - * "userpte=3Dnohigh" disables allocation of user pagetables in - * high memory. - */ - if (strcmp(arg, "nohigh") =3D=3D 0) - __userpte_alloc_gfp &=3D ~__GFP_HIGHMEM; - else - return -EINVAL; - return 0; + return __pte_alloc_one(mm, GFP_PGTABLE_USER); } -early_param("userpte", setup_userpte); =20 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) { --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7162E1B85F8 for ; Tue, 10 Dec 2024 14:50:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842221; cv=none; b=bTg3lOVbfKrZiPuI+66gOGHInyqDPaebds8mEYMz/ZBG6PY2uoSVIrwMB8bSjqw9SLVWbqo4s1NhcVg2hfzdUyXiVm4h41RHwW2HT/Rw9/H9g8qIgKXwJySAhWRSYTB6vU411pE5urDoNlvilx2kI3Z6MZb+fgeqAEnVpGVXdNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842221; c=relaxed/simple; bh=3SqhlieE4vNx9JonADEtTYk2B8rHIAfs7BIKa0g6a4w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kH2eKQJHMce1uaRfGjcYs6HO7jhFyzeBqkBDRcWZJ3O6eTG0XOy/kDV+IfZtzJ4BnKg69o0Kt9JbLgKMXlo7ESckprGHhvbCwZjuSTsWZXbocsoa6NoEVHTS898XXLmuSyZwzYCHqqn9yxFcXMjRatI12dbZR1GwgHjqgW0YFTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FOCukELC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FOCukELC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71F06C4CEE4; Tue, 10 Dec 2024 14:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842221; bh=3SqhlieE4vNx9JonADEtTYk2B8rHIAfs7BIKa0g6a4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FOCukELCMhDoJgoByOw2y2+84jzqroeGXEeIDgU3lDAq42msXuUItmlbZKAIRWpTf 1TMw/nrav0ErdnR+uNNIQYNbvY9I1tHI2us9KL+0SV/7hmKue/o/kRXYQwwidIXayf 9FqOdeNHYKCu3/1J9XgbTPH5PxhmnIInKArSVvlN/te6V9XbVZ4hryaTY8L92JfO1R hrzkfOiQNjvRxtIaGL7OnqzkyuDNVTtz4MHZEK5xvGyr61mCwJXCyW+jA67WsgH840 oJWcIfOV6xbvHUlLar0wm+ujI2GCXE+xYhZNsl3F2RfqwQrLbSNbfpMlonaLMOfYdu nn+hIWc0l+U7Q== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox , Ferry Toth Subject: [PATCH v2 09/11] x86: document X86_INTEL_MID as 64-bit-only Date: Tue, 10 Dec 2024 15:49:43 +0100 Message-Id: <20241210144945.2325330-10-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The X86_INTEL_MID code was originally introduced for the 32-bit Moorestown/Medfield/Clovertrail platform, later the 64-bit Merrifield/Moorefield variants were added, but the final Morganfield 14nm platform was canceled before it hit the market. To help users understand what the option actually refers to, update the help text, and add a dependency on 64-bit kernels. Ferry confirmed that all the hardware can run 64-bit kernels these days, but is still testing 32-bit kernels on the Intel Edison board, so this remains possible, but is guarded by a CONFIG_EXPERT dependency now, to gently push remaining users towards using CONFIG_64BIT. Cc: Ferry Toth Link: https://lore.kernel.org/lkml/d890eecc-97de-4abf-8e0e-b881d5db5c1d@gma= il.com/ Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig | 50 ++++++++++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d8a8bf9ea9b9..5ca8049004cb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -544,12 +544,12 @@ config X86_EXTENDED_PLATFORM RDC R-321x SoC SGI 320/540 (Visual Workstation) STA2X11-based (e.g. Northville) - Moorestown MID devices =20 64-bit platforms (CONFIG_64BIT=3Dy): Numascale NumaChip ScaleMP vSMP SGI Ultraviolet + Merrifield/Moorefield MID devices =20 If you have one of these systems, or if you want to build a generic distribution kernel, say Y here - otherwise say N. @@ -594,8 +594,31 @@ config X86_UV This option is needed in order to support SGI Ultraviolet systems. If you don't have one of these, you should say N here. =20 -# Following is an alphabetically sorted list of 32 bit extended platforms -# Please maintain the alphabetic order if and when there are additions +config X86_INTEL_MID + bool "Intel Z34xx/Z35xx MID platform support" + depends on X86_EXTENDED_PLATFORM + depends on X86_PLATFORM_DEVICES + depends on PCI + depends on X86_64 || (EXPERT && PCI_GOANY) + depends on X86_IO_APIC + select I2C + select DW_APB_TIMER + select INTEL_SCU_PCI + help + Select to build a kernel capable of supporting 64-bit Intel MID + (Mobile Internet Device) platform systems which do not have + the PCI legacy interfaces. + + The only supported devices are the 22nm Merrified (Z34xx) + and Moorefield (Z35xx) SoC used in the Intel Edison board and + a small number of Android devices such as the Asus Zenfone 2, + Asus FonePad 8 and Dell Venue 7. + + If you are building for a PC class system or non-MID tablet + SoCs like Bay Trail (Z36xx/Z37xx), say N here. + + Intel MID platforms are based on an Intel processor and chipset which + consume less power than most of the x86 derivatives. =20 config X86_GOLDFISH bool "Goldfish (Virtual Platform)" @@ -605,6 +628,9 @@ config X86_GOLDFISH for Android development. Unless you are building for the Android Goldfish emulator say N here. =20 +# Following is an alphabetically sorted list of 32 bit extended platforms +# Please maintain the alphabetic order if and when there are additions + config X86_INTEL_CE bool "CE4100 TV platform" depends on PCI @@ -620,24 +646,6 @@ config X86_INTEL_CE This option compiles in support for the CE4100 SOC for settop boxes and media devices. =20 -config X86_INTEL_MID - bool "Intel MID platform support" - depends on X86_EXTENDED_PLATFORM - depends on X86_PLATFORM_DEVICES - depends on PCI - depends on X86_64 || (PCI_GOANY && X86_32) - depends on X86_IO_APIC - select I2C - select DW_APB_TIMER - select INTEL_SCU_PCI - help - Select to build a kernel capable of supporting Intel MID (Mobile - Internet Device) platform systems which do not have the PCI legacy - interfaces. If you are building for a PC class system say N here. - - Intel MID platforms are based on an Intel processor and chipset which - consume less power than most of the x86 derivatives. - config X86_INTEL_QUARK bool "Intel Quark platform support" depends on X86_32 --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A2C51C1F1D for ; Tue, 10 Dec 2024 14:50:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842224; cv=none; b=Nk89AW9XwQ+A5mmYg/8PkJ/LdcZ2fZ7onBrOURB6fqkap8SzH12c96OIGFxO+rWGWG0r5c7tOGgzID3b8Y5D0mTTkpCZcuWLONAPDp+UuxlM6cU2X++kn07ZgJic4u5SzAmpMGh96Dh4zhSvYLaeBae6AsbNcpGwmoj/Z3G/eRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733842224; c=relaxed/simple; bh=e6YfyMWJTwN46qdqt6AO+dNK2VFS7DI5WEfAeiAktpg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GuqkZYuaUtobnKwr1Ver8+PLhQdrixM12Qq1cIzj97/DSLTVO6k3UIeVNH+J8DhauHeX9WcoldfcTlQfVrlUGFjutXGxm2jG22WUXSWgOLz4c4nniLshjoIn0zt06p0YXL6D3Rchd/V7xzQiHQvYZXNEwKIkB7Ud3QiXMqhW6i8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G0gbg8J2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G0gbg8J2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D11EC4CED6; Tue, 10 Dec 2024 14:50:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842223; bh=e6YfyMWJTwN46qdqt6AO+dNK2VFS7DI5WEfAeiAktpg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G0gbg8J2awYlWyBzeM4/MnL8WWghIVfoqzB0rbxc0Vx/mILWfRStI0EyD5aUv2L0o G11DdXxf40TFoT8Spm+GYc+pI1+mrENGiu/HK9VwIFXdGtl9dEW11bFsgvSYGMVtXj GKpPNFRNGV+Ky3RsyKE6QlPhYGyKxHOGIwoPQJUbzA1ZKu6S9VHr/DHgOn2ON2irIr C477FrjVACncA4SLL6bWqS5RA9GjD3h8+jGErQybbJBejAvXt35ooGc8ZPeADJFs+r bjnA0D/GFUhBwAx8YfQ/QPYMZhg1aPc4S8QOUdDhcAhTpjxVzu1KaDJi60CGiGf9Kg 6Uf2B1BP5Togw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 10/11] x86: remove old STA2x11 support Date: Tue, 10 Dec 2024 15:49:44 +0100 Message-Id: <20241210144945.2325330-11-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann ST ConneXt STA2x11 was an interface chip for Atom E6xx processors, using a number of components usually found on Arm SoCs. Most of this was merged upstream, but it was never complete enough to actually work and has been abandoned for many years. We already had an agreement on removing it in 2022, but nobody ever submitted the patch to do it. Without STA2x11, the CONFIG_X86_32_NON_STANDARD no longer has any use. Link: https://lore.kernel.org/lkml/Yw3DKCuDoPkCaqxE@arcana.i.gnudd.com/ Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig | 32 +---- arch/x86/include/asm/sta2x11.h | 13 -- arch/x86/pci/Makefile | 2 - arch/x86/pci/sta2x11-fixup.c | 233 --------------------------------- 4 files changed, 3 insertions(+), 277 deletions(-) delete mode 100644 arch/x86/include/asm/sta2x11.h delete mode 100644 arch/x86/pci/sta2x11-fixup.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5ca8049004cb..fb071548bc1e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -543,7 +543,6 @@ config X86_EXTENDED_PLATFORM AMD Elan RDC R-321x SoC SGI 320/540 (Visual Workstation) - STA2X11-based (e.g. Northville) =20 64-bit platforms (CONFIG_64BIT=3Dy): Numascale NumaChip @@ -727,18 +726,6 @@ config X86_RDC321X as R-8610-(G). If you don't have one of these chips, you should say N here. =20 -config X86_32_NON_STANDARD - bool "Support non-standard 32-bit SMP architectures" - depends on X86_32 && SMP - depends on X86_EXTENDED_PLATFORM - help - This option compiles in the STA2X11 default - subarchitecture. It is intended for a generic binary - kernel. If you select them all, kernel will probe it one by - one and will fallback to default. - -# Alphabetically sorted list of Non standard 32 bit platforms - config X86_SUPPORTS_MEMORY_FAILURE def_bool y # MCE code calls memory_failure(): @@ -748,19 +735,6 @@ config X86_SUPPORTS_MEMORY_FAILURE depends on X86_64 || !SPARSEMEM select ARCH_SUPPORTS_MEMORY_FAILURE =20 -config STA2X11 - bool "STA2X11 Companion Chip Support" - depends on X86_32_NON_STANDARD && PCI - select SWIOTLB - select MFD_STA2X11 - select GPIOLIB - help - This adds support for boards based on the STA2X11 IO-Hub, - a.k.a. "ConneXt". The chip is used in place of the standard - PC chipset, so all "standard" peripherals are missing. If this - option is selected the kernel will still be able to boot on - standard PC machines. - config X86_32_IRIS tristate "Eurobraille/Iris poweroff module" depends on X86_32 @@ -1098,7 +1072,7 @@ config UP_LATE_INIT config X86_UP_APIC bool "Local APIC support on uniprocessors" if !PCI_MSI default PCI_MSI - depends on X86_32 && !SMP && !X86_32_NON_STANDARD + depends on X86_32 && !SMP help A local APIC (Advanced Programmable Interrupt Controller) is an integrated interrupt controller in the CPU. If you have a single-CPU @@ -1123,7 +1097,7 @@ config X86_UP_IOAPIC =20 config X86_LOCAL_APIC def_bool y - depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI + depends on X86_64 || SMP || X86_UP_APIC || PCI_MSI select IRQ_DOMAIN_HIERARCHY =20 config ACPI_MADT_WAKEUP @@ -1583,7 +1557,7 @@ config ARCH_FLATMEM_ENABLE =20 config ARCH_SPARSEMEM_ENABLE def_bool y - depends on X86_64 || NUMA || X86_32 || X86_32_NON_STANDARD + depends on X86_64 || NUMA || X86_32 select SPARSEMEM_STATIC if X86_32 select SPARSEMEM_VMEMMAP_ENABLE if X86_64 =20 diff --git a/arch/x86/include/asm/sta2x11.h b/arch/x86/include/asm/sta2x11.h deleted file mode 100644 index e0975e9c4f47..000000000000 --- a/arch/x86/include/asm/sta2x11.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Header file for STMicroelectronics ConneXt (STA2X11) IOHub - */ -#ifndef __ASM_STA2X11_H -#define __ASM_STA2X11_H - -#include - -/* This needs to be called from the MFD to configure its sub-devices */ -struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev); - -#endif /* __ASM_STA2X11_H */ diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile index 48bcada5cabe..4933fb337983 100644 --- a/arch/x86/pci/Makefile +++ b/arch/x86/pci/Makefile @@ -12,8 +12,6 @@ obj-$(CONFIG_X86_INTEL_CE) +=3D ce4100.o obj-$(CONFIG_ACPI) +=3D acpi.o obj-y +=3D legacy.o irq.o =20 -obj-$(CONFIG_STA2X11) +=3D sta2x11-fixup.o - obj-$(CONFIG_X86_NUMACHIP) +=3D numachip.o =20 obj-$(CONFIG_X86_INTEL_MID) +=3D intel_mid_pci.o diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c deleted file mode 100644 index 8c8ddc4dcc08..000000000000 --- a/arch/x86/pci/sta2x11-fixup.c +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * DMA translation between STA2x11 AMBA memory mapping and the x86 memory = mapping - * - * ST Microelectronics ConneXt (STA2X11/STA2X10) - * - * Copyright (c) 2010-2011 Wind River Systems, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define STA2X11_SWIOTLB_SIZE (4*1024*1024) - -/* - * We build a list of bus numbers that are under the ConneXt. The - * main bridge hosts 4 busses, which are the 4 endpoints, in order. - */ -#define STA2X11_NR_EP 4 /* 0..3 included */ -#define STA2X11_NR_FUNCS 8 /* 0..7 included */ -#define STA2X11_AMBA_SIZE (512 << 20) - -struct sta2x11_ahb_regs { /* saved during suspend */ - u32 base, pexlbase, pexhbase, crw; -}; - -struct sta2x11_mapping { - int is_suspended; - struct sta2x11_ahb_regs regs[STA2X11_NR_FUNCS]; -}; - -struct sta2x11_instance { - struct list_head list; - int bus0; - struct sta2x11_mapping map[STA2X11_NR_EP]; -}; - -static LIST_HEAD(sta2x11_instance_list); - -/* At probe time, record new instances of this bridge (likely one only) */ -static void sta2x11_new_instance(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance; - - instance =3D kzalloc(sizeof(*instance), GFP_ATOMIC); - if (!instance) - return; - /* This has a subordinate bridge, with 4 more-subordinate ones */ - instance->bus0 =3D pdev->subordinate->number + 1; - - if (list_empty(&sta2x11_instance_list)) { - int size =3D STA2X11_SWIOTLB_SIZE; - /* First instance: register your own swiotlb area */ - dev_info(&pdev->dev, "Using SWIOTLB (size %i)\n", size); - if (swiotlb_init_late(size, GFP_DMA, NULL)) - dev_emerg(&pdev->dev, "init swiotlb failed\n"); - } - list_add(&instance->list, &sta2x11_instance_list); -} -DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, 0xcc17, sta2x11_new_instan= ce); - -/* - * Utility functions used in this file from below - */ -static struct sta2x11_instance *sta2x11_pdev_to_instance(struct pci_dev *p= dev) -{ - struct sta2x11_instance *instance; - int ep; - - list_for_each_entry(instance, &sta2x11_instance_list, list) { - ep =3D pdev->bus->number - instance->bus0; - if (ep >=3D 0 && ep < STA2X11_NR_EP) - return instance; - } - return NULL; -} - -static int sta2x11_pdev_to_ep(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance; - - instance =3D sta2x11_pdev_to_instance(pdev); - if (!instance) - return -1; - - return pdev->bus->number - instance->bus0; -} - -/* This is exported, as some devices need to access the MFD registers */ -struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev) -{ - return sta2x11_pdev_to_instance(pdev); -} -EXPORT_SYMBOL(sta2x11_get_instance); - -/* At setup time, we use our own ops if the device is a ConneXt one */ -static void sta2x11_setup_pdev(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance =3D sta2x11_pdev_to_instance(pdev); - - if (!instance) /* either a sta2x11 bridge or another ST device */ - return; - - /* We must enable all devices as master, for audio DMA to work */ - pci_set_master(pdev); -} -DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_setup_= pdev); - -/* - * At boot we must set up the mappings for the pcie-to-amba bridge. - * It involves device access, and the same happens at suspend/resume time - */ - -#define AHB_MAPB 0xCA4 -#define AHB_CRW(i) (AHB_MAPB + 0 + (i) * 0x10) -#define AHB_CRW_SZMASK 0xfffffc00UL -#define AHB_CRW_ENABLE (1 << 0) -#define AHB_CRW_WTYPE_MEM (2 << 1) -#define AHB_CRW_ROE (1UL << 3) /* Relax Order Ena */ -#define AHB_CRW_NSE (1UL << 4) /* No Snoop Enable */ -#define AHB_BASE(i) (AHB_MAPB + 4 + (i) * 0x10) -#define AHB_PEXLBASE(i) (AHB_MAPB + 8 + (i) * 0x10) -#define AHB_PEXHBASE(i) (AHB_MAPB + 12 + (i) * 0x10) - -/* At probe time, enable mapping for each endpoint, using the pdev */ -static void sta2x11_map_ep(struct pci_dev *pdev) -{ - struct sta2x11_instance *instance =3D sta2x11_pdev_to_instance(pdev); - struct device *dev =3D &pdev->dev; - u32 amba_base, max_amba_addr; - int i, ret; - - if (!instance) - return; - - pci_read_config_dword(pdev, AHB_BASE(0), &amba_base); - max_amba_addr =3D amba_base + STA2X11_AMBA_SIZE - 1; - - ret =3D dma_direct_set_offset(dev, 0, amba_base, STA2X11_AMBA_SIZE); - if (ret) - dev_err(dev, "sta2x11: could not set DMA offset\n"); - - dev->bus_dma_limit =3D max_amba_addr; - dma_set_mask_and_coherent(&pdev->dev, max_amba_addr); - - /* Configure AHB mapping */ - pci_write_config_dword(pdev, AHB_PEXLBASE(0), 0); - pci_write_config_dword(pdev, AHB_PEXHBASE(0), 0); - pci_write_config_dword(pdev, AHB_CRW(0), STA2X11_AMBA_SIZE | - AHB_CRW_WTYPE_MEM | AHB_CRW_ENABLE); - - /* Disable all the other windows */ - for (i =3D 1; i < STA2X11_NR_FUNCS; i++) - pci_write_config_dword(pdev, AHB_CRW(i), 0); - - dev_info(&pdev->dev, - "sta2x11: Map EP %i: AMBA address %#8x-%#8x\n", - sta2x11_pdev_to_ep(pdev), amba_base, max_amba_addr); -} -DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_map_ep= ); - -#ifdef CONFIG_PM /* Some register values must be saved and restored */ - -static struct sta2x11_mapping *sta2x11_pdev_to_mapping(struct pci_dev *pde= v) -{ - struct sta2x11_instance *instance; - int ep; - - instance =3D sta2x11_pdev_to_instance(pdev); - if (!instance) - return NULL; - ep =3D sta2x11_pdev_to_ep(pdev); - return instance->map + ep; -} - -static void suspend_mapping(struct pci_dev *pdev) -{ - struct sta2x11_mapping *map =3D sta2x11_pdev_to_mapping(pdev); - int i; - - if (!map) - return; - - if (map->is_suspended) - return; - map->is_suspended =3D 1; - - /* Save all window configs */ - for (i =3D 0; i < STA2X11_NR_FUNCS; i++) { - struct sta2x11_ahb_regs *regs =3D map->regs + i; - - pci_read_config_dword(pdev, AHB_BASE(i), ®s->base); - pci_read_config_dword(pdev, AHB_PEXLBASE(i), ®s->pexlbase); - pci_read_config_dword(pdev, AHB_PEXHBASE(i), ®s->pexhbase); - pci_read_config_dword(pdev, AHB_CRW(i), ®s->crw); - } -} -DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, suspend_mappi= ng); - -static void resume_mapping(struct pci_dev *pdev) -{ - struct sta2x11_mapping *map =3D sta2x11_pdev_to_mapping(pdev); - int i; - - if (!map) - return; - - - if (!map->is_suspended) - goto out; - map->is_suspended =3D 0; - - /* Restore all window configs */ - for (i =3D 0; i < STA2X11_NR_FUNCS; i++) { - struct sta2x11_ahb_regs *regs =3D map->regs + i; - - pci_write_config_dword(pdev, AHB_BASE(i), regs->base); - pci_write_config_dword(pdev, AHB_PEXLBASE(i), regs->pexlbase); - pci_write_config_dword(pdev, AHB_PEXHBASE(i), regs->pexhbase); - pci_write_config_dword(pdev, AHB_CRW(i), regs->crw); - } -out: - pci_set_master(pdev); /* Like at boot, enable master on all devices */ -} -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, resume_mapping= ); - -#endif /* CONFIG_PM */ --=20 2.39.5 From nobody Wed Dec 17 12:44:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68A401C1F25 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GFJ2wEdd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B042C4CEDF; Tue, 10 Dec 2024 14:50:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733842226; bh=00nw3SlffvP/c1d9ovm9ZcoFK1ptqaK8lm0cPmWJ9jU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GFJ2wEddeluEfYA4qnI9ZlK3eIF6l4mBzT4SboBFnFfiDEerO3kC63NJHVVJtVqWq A7ERBw24/92rHCk2KRoTmj7+YREK+RPt245yDIP/FDOtFHC24JRUcJM2PDMZ+oLlhz Jl+zW0if9IU2tLlr389pUuXjyIY/cVvkUg+MykygxqenfeH+6MdMV+4sza104XO6OZ QRc7SMeALmqN4Zp5Fpszoi1V4mMmlKjCIzYVCVxAyJJ7bAz3kzdOPXQORbVQJmlrrz kl7ktticwrC/j62rXSPvq+0Tiqj2LZOkV0gOW1EqC4AyRtxkNvKN1xHeA8x+vg7xYJ i3f1J/0M1wENw== From: Arnd Bergmann To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Andy Shevchenko , Matthew Wilcox Subject: [PATCH v2 11/11] x86: Move platforms to Kconfig.platforms Date: Tue, 10 Dec 2024 15:49:45 +0100 Message-Id: <20241210144945.2325330-12-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241210144945.2325330-1-arnd@kernel.org> References: <20241210144945.2325330-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann The x86 platform options in Kconfig are rather confusing, as they are a mix of options that just control visibility of drivers and those that are fundamental to the operation, with some of the code in arch/x86/platforms and other code in drivers/platform/x86, and the options listed in various places in arch/x86/Kconfig. Make this a little more consistent by moving all options that control a platform from arch/x86/Kconfig to arch/x86/Kconfig.platforms and put them into a submenu. Signed-off-by: Arnd Bergmann Acked-by: Andy Shevchenko --- arch/x86/Kconfig | 363 +------------------------------------ arch/x86/Kconfig.platforms | 361 ++++++++++++++++++++++++++++++++++++ 2 files changed, 363 insertions(+), 361 deletions(-) create mode 100644 arch/x86/Kconfig.platforms diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fb071548bc1e..98530ce14eab 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -526,205 +526,7 @@ config X86_FRED ring transitions and exception/interrupt handling if the system supports it. =20 -config X86_EXTENDED_PLATFORM - bool "Support for extended (non-PC) x86 platforms" - default y - help - If you disable this option then the kernel will only support - standard PC platforms. (which covers the vast majority of - systems out there.) - - If you enable this option then you'll be able to select support - for the following non-PC x86 platforms, depending on the value of - CONFIG_64BIT. - - 32-bit platforms (CONFIG_64BIT=3Dn): - Goldfish (Android emulator) - AMD Elan - RDC R-321x SoC - SGI 320/540 (Visual Workstation) - - 64-bit platforms (CONFIG_64BIT=3Dy): - Numascale NumaChip - ScaleMP vSMP - SGI Ultraviolet - Merrifield/Moorefield MID devices - - If you have one of these systems, or if you want to build a - generic distribution kernel, say Y here - otherwise say N. - -# This is an alphabetically sorted list of 64 bit extended platforms -# Please maintain the alphabetic order if and when there are additions -config X86_NUMACHIP - bool "Numascale NumaChip" - depends on X86_64 - depends on X86_EXTENDED_PLATFORM - depends on NUMA - depends on SMP - depends on X86_X2APIC - depends on PCI_MMCONFIG - help - Adds support for Numascale NumaChip large-SMP systems. Needed to - enable more than ~168 cores. - If you don't have one of these, you should say N here. - -config X86_VSMP - bool "ScaleMP vSMP" - select HYPERVISOR_GUEST - select PARAVIRT - depends on X86_64 && PCI - depends on X86_EXTENDED_PLATFORM - depends on SMP - help - Support for ScaleMP vSMP systems. Say 'Y' here if this kernel is - supposed to run on these EM64T-based machines. Only choose this option - if you have one of these machines. - -config X86_UV - bool "SGI Ultraviolet" - depends on X86_64 - depends on X86_EXTENDED_PLATFORM - depends on NUMA - depends on EFI - depends on KEXEC_CORE - depends on X86_X2APIC - depends on PCI - help - This option is needed in order to support SGI Ultraviolet systems. - If you don't have one of these, you should say N here. - -config X86_INTEL_MID - bool "Intel Z34xx/Z35xx MID platform support" - depends on X86_EXTENDED_PLATFORM - depends on X86_PLATFORM_DEVICES - depends on PCI - depends on X86_64 || (EXPERT && PCI_GOANY) - depends on X86_IO_APIC - select I2C - select DW_APB_TIMER - select INTEL_SCU_PCI - help - Select to build a kernel capable of supporting 64-bit Intel MID - (Mobile Internet Device) platform systems which do not have - the PCI legacy interfaces. - - The only supported devices are the 22nm Merrified (Z34xx) - and Moorefield (Z35xx) SoC used in the Intel Edison board and - a small number of Android devices such as the Asus Zenfone 2, - Asus FonePad 8 and Dell Venue 7. - - If you are building for a PC class system or non-MID tablet - SoCs like Bay Trail (Z36xx/Z37xx), say N here. - - Intel MID platforms are based on an Intel processor and chipset which - consume less power than most of the x86 derivatives. - -config X86_GOLDFISH - bool "Goldfish (Virtual Platform)" - depends on X86_EXTENDED_PLATFORM - help - Enable support for the Goldfish virtual platform used primarily - for Android development. Unless you are building for the Android - Goldfish emulator say N here. - -# Following is an alphabetically sorted list of 32 bit extended platforms -# Please maintain the alphabetic order if and when there are additions - -config X86_INTEL_CE - bool "CE4100 TV platform" - depends on PCI - depends on PCI_GODIRECT - depends on X86_IO_APIC - depends on X86_32 - depends on X86_EXTENDED_PLATFORM - select X86_REBOOTFIXUPS - select OF - select OF_EARLY_FLATTREE - help - Select for the Intel CE media processor (CE4100) SOC. - This option compiles in support for the CE4100 SOC for settop - boxes and media devices. - -config X86_INTEL_QUARK - bool "Intel Quark platform support" - depends on X86_32 - depends on X86_EXTENDED_PLATFORM - depends on X86_PLATFORM_DEVICES - depends on X86_TSC - depends on PCI - depends on PCI_GOANY - depends on X86_IO_APIC - select IOSF_MBI - select INTEL_IMR - select COMMON_CLK - help - Select to include support for Quark X1000 SoC. - Say Y here if you have a Quark based system such as the Arduino - compatible Intel Galileo. - -config X86_INTEL_LPSS - bool "Intel Low Power Subsystem Support" - depends on X86 && ACPI && PCI - select COMMON_CLK - select PINCTRL - select IOSF_MBI - help - Select to build support for Intel Low Power Subsystem such as - found on Intel Lynxpoint PCH. Selecting this option enables - things like clock tree (common clock framework) and pincontrol - which are needed by the LPSS peripheral drivers. - -config X86_AMD_PLATFORM_DEVICE - bool "AMD ACPI2Platform devices support" - depends on ACPI - select COMMON_CLK - select PINCTRL - help - Select to interpret AMD specific ACPI device to platform device - such as I2C, UART, GPIO found on AMD Carrizo and later chipsets. - I2C and UART depend on COMMON_CLK to set clock. GPIO driver is - implemented under PINCTRL subsystem. - -config IOSF_MBI - tristate "Intel SoC IOSF Sideband support for SoC platforms" - depends on PCI - help - This option enables sideband register access support for Intel SoC - platforms. On these platforms the IOSF sideband is used in lieu of - MSR's for some register accesses, mostly but not limited to thermal - and power. Drivers may query the availability of this device to - determine if they need the sideband in order to work on these - platforms. The sideband is available on the following SoC products. - This list is not meant to be exclusive. - - BayTrail - - Braswell - - Quark - - You should say Y if you are running a kernel on one of these SoC's. - -config IOSF_MBI_DEBUG - bool "Enable IOSF sideband access through debugfs" - depends on IOSF_MBI && DEBUG_FS - help - Select this option to expose the IOSF sideband access registers (MCR, - MDR, MCRX) through debugfs to write and read register information from - different units on the SoC. This is most useful for obtaining device - state information for debug and analysis. As this is a general access - mechanism, users of this option would have specific knowledge of the - device they want to access. - - If you don't require the option or are in doubt, say N. - -config X86_RDC321X - bool "RDC R-321x SoC" - depends on X86_32 - depends on X86_EXTENDED_PLATFORM - select M486 - select X86_REBOOTFIXUPS - help - This option is needed for RDC R-321x system-on-chip, also known - as R-8610-(G). - If you don't have one of these chips, you should say N here. +source "arch/x86/Kconfig.platforms" =20 config X86_SUPPORTS_MEMORY_FAILURE def_bool y @@ -735,19 +537,6 @@ config X86_SUPPORTS_MEMORY_FAILURE depends on X86_64 || !SPARSEMEM select ARCH_SUPPORTS_MEMORY_FAILURE =20 -config X86_32_IRIS - tristate "Eurobraille/Iris poweroff module" - depends on X86_32 - help - The Iris machines from EuroBraille do not have APM or ACPI support - to shut themselves down properly. A special I/O sequence is - needed to do so, which is what this module does at - kernel shutdown. - - This is only for Iris machines from EuroBraille. - - If unused, say N. - config SCHED_OMIT_FRAME_POINTER def_bool y prompt "Single-depth WCHAN output" @@ -1275,39 +1064,6 @@ config X86_IOPL_IOPERM ability to disable interrupts from user space which would be granted if the hardware IOPL mechanism would be used. =20 -config TOSHIBA - tristate "Toshiba Laptop support" - depends on X86_32 - help - This adds a driver to safely access the System Management Mode of - the CPU on Toshiba portables with a genuine Toshiba BIOS. It does - not work on models with a Phoenix BIOS. The System Management Mode - is used to set the BIOS and power saving options on Toshiba portables. - - For information on utilities to make use of this driver see the - Toshiba Linux utilities web site at: - . - - Say Y if you intend to run this kernel on a Toshiba portable. - Say N otherwise. - -config X86_REBOOTFIXUPS - bool "Enable X86 board specific fixups for reboot" - depends on X86_32 - help - This enables chipset and/or board specific fixups to be done - in order to get reboot to work correctly. This is only needed on - some combinations of hardware and BIOS. The symptom, for which - this config is intended, is when reboot ends with a stalled/hung - system. - - Currently, the only fixup is for the Geode machines using - CS5530A and CS5536 chipsets and the RDC R-321x SoC. - - Say Y if you want to enable the fixup. Currently, it's safe to - enable this option even if you don't need it. - Say N otherwise. - config MICROCODE def_bool y depends on CPU_SUP_AMD || CPU_SUP_INTEL @@ -2927,10 +2683,9 @@ config ISA_DMA_API Enables ISA-style DMA support for devices requiring such controllers. If unsure, say Y. =20 -if X86_32 - config ISA bool "ISA support" + depends on X86_32 help Find out whether you have ISA slots on your motherboard. ISA is the name of a bus system, i.e. the way the CPU talks to the other stuff @@ -2938,120 +2693,6 @@ config ISA (MCA) or VESA. ISA is an older system, now being displaced by PCI; newer boards don't support it. If you have ISA, say Y, otherwise N. =20 -config SCx200 - tristate "NatSemi SCx200 support" - help - This provides basic support for National Semiconductor's - (now AMD's) Geode processors. The driver probes for the - PCI-IDs of several on-chip devices, so its a good dependency - for other scx200_* drivers. - - If compiled as a module, the driver is named scx200. - -config SCx200HR_TIMER - tristate "NatSemi SCx200 27MHz High-Resolution Timer Support" - depends on SCx200 - default y - help - This driver provides a clocksource built upon the on-chip - 27MHz high-resolution timer. Its also a workaround for - NSC Geode SC-1100's buggy TSC, which loses time when the - processor goes idle (as is done by the scheduler). The - other workaround is idle=3Dpoll boot option. - -config OLPC - bool "One Laptop Per Child support" - depends on !X86_PAE - select GPIOLIB - select OF - select OF_PROMTREE - select IRQ_DOMAIN - select OLPC_EC - help - Add support for detecting the unique features of the OLPC - XO hardware. - -config OLPC_XO1_PM - bool "OLPC XO-1 Power Management" - depends on OLPC && MFD_CS5535=3Dy && PM_SLEEP - help - Add support for poweroff and suspend of the OLPC XO-1 laptop. - -config OLPC_XO1_RTC - bool "OLPC XO-1 Real Time Clock" - depends on OLPC_XO1_PM && RTC_DRV_CMOS - help - Add support for the XO-1 real time clock, which can be used as a - programmable wakeup source. - -config OLPC_XO1_SCI - bool "OLPC XO-1 SCI extras" - depends on OLPC && OLPC_XO1_PM && GPIO_CS5535=3Dy - depends on INPUT=3Dy - select POWER_SUPPLY - help - Add support for SCI-based features of the OLPC XO-1 laptop: - - EC-driven system wakeups - - Power button - - Ebook switch - - Lid switch - - AC adapter status updates - - Battery status updates - -config OLPC_XO15_SCI - bool "OLPC XO-1.5 SCI extras" - depends on OLPC && ACPI - select POWER_SUPPLY - help - Add support for SCI-based features of the OLPC XO-1.5 laptop: - - EC-driven system wakeups - - AC adapter status updates - - Battery status updates - -config GEODE_COMMON - bool - -config ALIX - bool "PCEngines ALIX System Support (LED setup)" - select GPIOLIB - select GEODE_COMMON - help - This option enables system support for the PCEngines ALIX. - At present this just sets up LEDs for GPIO control on - ALIX2/3/6 boards. However, other system specific setup should - get added here. - - Note: You must still enable the drivers for GPIO and LED support - (GPIO_CS5535 & LEDS_GPIO) to actually use the LEDs - - Note: You have to set alix.force=3D1 for boards with Award BIOS. - -config NET5501 - bool "Soekris Engineering net5501 System Support (LEDS, GPIO, etc)" - select GPIOLIB - select GEODE_COMMON - help - This option enables system support for the Soekris Engineering net5501. - -config GEOS - bool "Traverse Technologies GEOS System Support (LEDS, GPIO, etc)" - select GPIOLIB - select GEODE_COMMON - depends on DMI - help - This option enables system support for the Traverse Technologies GEOS. - -config TS5500 - bool "Technologic Systems TS-5500 platform support" - depends on MELAN - select CHECK_SIGNATURE - select NEW_LEDS - select LEDS_CLASS - help - This option enables system support for the Technologic Systems TS-5500. - -endif # X86_32 - config AMD_NB def_bool y depends on CPU_SUP_AMD && PCI diff --git a/arch/x86/Kconfig.platforms b/arch/x86/Kconfig.platforms new file mode 100644 index 000000000000..cac6753bacea --- /dev/null +++ b/arch/x86/Kconfig.platforms @@ -0,0 +1,361 @@ +menu "Platform selection" + +config X86_EXTENDED_PLATFORM + bool "Support for extended (non-PC) x86 platforms" + default y + help + If you disable this option then the kernel will only support + standard PC platforms. (which covers the vast majority of + systems out there.) + + If you enable this option then you'll be able to select support + for the following non-PC x86 platforms, depending on the value of + CONFIG_64BIT. + + 32-bit platforms (CONFIG_64BIT=3Dn): + Intel CE4100 + Intel Quark + AMD Geode + AMD Elan + RDC R-321x + + 64-bit platforms (CONFIG_64BIT=3Dy): + Numascale NumaChip + ScaleMP vSMP + SGI Ultraviolet + Merrifield/Moorefield MID devices + Goldfish (Android emulator) + + If you have one of these systems, or if you want to build a + generic distribution kernel, say Y here - otherwise say N. + +# This is an alphabetically sorted list of 64 bit extended platforms +# Please maintain the alphabetic order if and when there are additions +config X86_NUMACHIP + bool "Numascale NumaChip" + depends on X86_64 + depends on X86_EXTENDED_PLATFORM + depends on NUMA + depends on SMP + depends on X86_X2APIC + depends on PCI_MMCONFIG + help + Adds support for Numascale NumaChip large-SMP systems. Needed to + enable more than ~168 cores. + If you don't have one of these, you should say N here. + +config X86_VSMP + bool "ScaleMP vSMP" + select HYPERVISOR_GUEST + select PARAVIRT + depends on X86_64 && PCI + depends on X86_EXTENDED_PLATFORM + depends on SMP + help + Support for ScaleMP vSMP systems. Say 'Y' here if this kernel is + supposed to run on these EM64T-based machines. Only choose this option + if you have one of these machines. + +config X86_UV + bool "SGI Ultraviolet" + depends on X86_64 + depends on X86_EXTENDED_PLATFORM + depends on NUMA + depends on EFI + depends on KEXEC_CORE + depends on X86_X2APIC + depends on PCI + help + This option is needed in order to support SGI Ultraviolet systems. + If you don't have one of these, you should say N here. + +config X86_INTEL_MID + bool "Intel Z34xx/Z35xx MID platform support" + depends on X86_EXTENDED_PLATFORM + depends on X86_PLATFORM_DEVICES + depends on PCI + depends on X86_64 || (EXPERT && PCI_GOANY) + depends on X86_IO_APIC + select I2C + select DW_APB_TIMER + select INTEL_SCU_PCI + help + Select to build a kernel capable of supporting 64-bit Intel MID + (Mobile Internet Device) platform systems which do not have + the PCI legacy interfaces. + + The only supported devices are the 22nm Merrified (Z34xx) + and Moorefield (Z35xx) SoC used in the Intel Edison board and + a small number of Android devices such as the Asus Zenfone 2, + Asus FonePad 8 and Dell Venue 7. + + If you are building for a PC class system or non-MID tablet + SoCs like Bay Trail (Z36xx/Z37xx), say N here. + + Intel MID platforms are based on an Intel processor and chipset which + consume less power than most of the x86 derivatives. + +config X86_GOLDFISH + bool "Goldfish (Virtual Platform)" + depends on X86_EXTENDED_PLATFORM + help + Enable support for the Goldfish virtual platform used primarily + for Android development. Unless you are building for the Android + Goldfish emulator say N here. + +# Following is an alphabetically sorted list of 32 bit extended platforms +# Please maintain the alphabetic order if and when there are additions + +if X86_32 && X86_EXTENDED_PLATFORM + +config X86_INTEL_CE + bool "CE4100 TV platform" + depends on PCI + depends on PCI_GODIRECT + depends on X86_IO_APIC + select X86_REBOOTFIXUPS + select OF + select OF_EARLY_FLATTREE + help + Select for the Intel CE media processor (CE4100) SOC. + This option compiles in support for the CE4100 SOC for settop + boxes and media devices. + +config X86_INTEL_QUARK + bool "Intel Quark platform support" + depends on X86_PLATFORM_DEVICES + depends on X86_TSC + depends on PCI + depends on PCI_GOANY + depends on X86_IO_APIC + select IOSF_MBI + select INTEL_IMR + select COMMON_CLK + help + Select to include support for Quark X1000 SoC. + Say Y here if you have a Quark based system such as the Arduino + compatible Intel Galileo. + +config SCx200 + tristate "NatSemi SCx200 support" + help + This provides basic support for National Semiconductor's + (now AMD's) Geode processors. The driver probes for the + PCI-IDs of several on-chip devices, so its a good dependency + for other scx200_* drivers. + + If compiled as a module, the driver is named scx200. + +config SCx200HR_TIMER + tristate "NatSemi SCx200 27MHz High-Resolution Timer Support" + depends on SCx200 + default y + help + This driver provides a clocksource built upon the on-chip + 27MHz high-resolution timer. Its also a workaround for + NSC Geode SC-1100's buggy TSC, which loses time when the + processor goes idle (as is done by the scheduler). The + other workaround is idle=3Dpoll boot option. + +config OLPC + bool "One Laptop Per Child support" + depends on !X86_PAE + select GPIOLIB + select OF + select OF_PROMTREE + select IRQ_DOMAIN + select OLPC_EC + help + Add support for detecting the unique features of the OLPC + XO hardware. + +config OLPC_XO1_PM + bool "OLPC XO-1 Power Management" + depends on OLPC && MFD_CS5535=3Dy && PM_SLEEP + help + Add support for poweroff and suspend of the OLPC XO-1 laptop. + +config OLPC_XO1_RTC + bool "OLPC XO-1 Real Time Clock" + depends on OLPC_XO1_PM && RTC_DRV_CMOS + help + Add support for the XO-1 real time clock, which can be used as a + programmable wakeup source. + +config OLPC_XO1_SCI + bool "OLPC XO-1 SCI extras" + depends on OLPC && OLPC_XO1_PM && GPIO_CS5535=3Dy + depends on INPUT=3Dy + select POWER_SUPPLY + help + Add support for SCI-based features of the OLPC XO-1 laptop: + - EC-driven system wakeups + - Power button + - Ebook switch + - Lid switch + - AC adapter status updates + - Battery status updates + +config OLPC_XO15_SCI + bool "OLPC XO-1.5 SCI extras" + depends on OLPC && ACPI + select POWER_SUPPLY + help + Add support for SCI-based features of the OLPC XO-1.5 laptop: + - EC-driven system wakeups + - AC adapter status updates + - Battery status updates + +config GEODE_COMMON + bool + +config ALIX + bool "PCEngines ALIX System Support (LED setup)" + select GPIOLIB + select GEODE_COMMON + help + This option enables system support for the PCEngines ALIX. + At present this just sets up LEDs for GPIO control on + ALIX2/3/6 boards. However, other system specific setup should + get added here. + + Note: You must still enable the drivers for GPIO and LED support + (GPIO_CS5535 & LEDS_GPIO) to actually use the LEDs + + Note: You have to set alix.force=3D1 for boards with Award BIOS. + +config NET5501 + bool "Soekris Engineering net5501 System Support (LEDS, GPIO, etc)" + select GPIOLIB + select GEODE_COMMON + help + This option enables system support for the Soekris Engineering net5501. + +config GEOS + bool "Traverse Technologies GEOS System Support (LEDS, GPIO, etc)" + select GPIOLIB + select GEODE_COMMON + depends on DMI + help + This option enables system support for the Traverse Technologies GEOS. + +config TS5500 + bool "Technologic Systems TS-5500 platform support" + depends on MELAN + select CHECK_SIGNATURE + select NEW_LEDS + select LEDS_CLASS + help + This option enables system support for the Technologic Systems TS-5500. + +config X86_RDC321X + bool "RDC R-321x SoC" + select M486 + select X86_REBOOTFIXUPS + help + This option is needed for RDC R-321x system-on-chip, also known + as R-8610-(G). + If you don't have one of these chips, you should say N here. + +config X86_REBOOTFIXUPS + bool "Enable X86 board specific fixups for reboot" + depends on X86_32 + help + This enables chipset and/or board specific fixups to be done + in order to get reboot to work correctly. This is only needed on + some combinations of hardware and BIOS. The symptom, for which + this config is intended, is when reboot ends with a stalled/hung + system. + + Currently, the only fixup is for the Geode machines using + CS5530A and CS5536 chipsets and the RDC R-321x SoC. + + Say Y if you want to enable the fixup. Currently, it's safe to + enable this option even if you don't need it. + Say N otherwise. + +endif # X86_32 extended platform + +config TOSHIBA + tristate "Toshiba Laptop support" + depends on X86_32 + help + This adds a driver to safely access the System Management Mode of + the CPU on Toshiba portables with a genuine Toshiba BIOS. It does + not work on models with a Phoenix BIOS. The System Management Mode + is used to set the BIOS and power saving options on Toshiba portables. + + For information on utilities to make use of this driver see the + Toshiba Linux utilities web site at: + . + + Say Y if you intend to run this kernel on a Toshiba portable. + Say N otherwise. + +config X86_32_IRIS + tristate "Eurobraille/Iris poweroff module" + depends on X86_32 + help + The Iris machines from EuroBraille do not have APM or ACPI support + to shut themselves down properly. A special I/O sequence is + needed to do so, which is what this module does at + kernel shutdown. + + This is only for Iris machines from EuroBraille. + + If unused, say N. + +config X86_INTEL_LPSS + bool "Intel Low Power Subsystem Support" + depends on X86 && ACPI && PCI + select COMMON_CLK + select PINCTRL + select IOSF_MBI + help + Select to build support for Intel Low Power Subsystem such as + found on Intel Lynxpoint PCH. Selecting this option enables + things like clock tree (common clock framework) and pincontrol + which are needed by the LPSS peripheral drivers. + +config X86_AMD_PLATFORM_DEVICE + bool "AMD ACPI2Platform devices support" + depends on ACPI + select COMMON_CLK + select PINCTRL + help + Select to interpret AMD specific ACPI device to platform device + such as I2C, UART, GPIO found on AMD Carrizo and later chipsets. + I2C and UART depend on COMMON_CLK to set clock. GPIO driver is + implemented under PINCTRL subsystem. + +config IOSF_MBI + tristate "Intel SoC IOSF Sideband support for SoC platforms" + depends on PCI + help + This option enables sideband register access support for Intel SoC + platforms. On these platforms the IOSF sideband is used in lieu of + MSR's for some register accesses, mostly but not limited to thermal + and power. Drivers may query the availability of this device to + determine if they need the sideband in order to work on these + platforms. The sideband is available on the following SoC products. + This list is not meant to be exclusive. + - BayTrail + - Braswell + - Quark + + You should say Y if you are running a kernel on one of these SoC's. + +config IOSF_MBI_DEBUG + bool "Enable IOSF sideband access through debugfs" + depends on IOSF_MBI && DEBUG_FS + help + Select this option to expose the IOSF sideband access registers (MCR, + MDR, MCRX) through debugfs to write and read register information from + different units on the SoC. This is most useful for obtaining device + state information for debug and analysis. As this is a general access + mechanism, users of this option would have specific knowledge of the + device they want to access. + + If you don't require the option or are in doubt, say N. + +endmenu --=20 2.39.5