From nobody Sun Dec 14 13:41:11 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 775D423DEB9 for ; Tue, 10 Dec 2024 10:34:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826859; cv=none; b=dmxrM2iSs6rNTtWp9ot2mF02wEfISU88buRuAtNNY4cPVf8C9vYbuQHlQDKfW3nb+md8sd8AWhP4ZrGY+Qtiyl5pWP1zVcBz3t8WU77wioHsnRsi6WdD0WYBCVTnLEQN3tdreMSi569mFu4Xphugurb0IWgBs1p+YOdMRsgt5pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826859; c=relaxed/simple; bh=o60wCU2VnZ8PuDwGNWj2BCybBVp81F0WORBYw7xeBpA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=UdgQ/bRTBfEKBCyvInEaWzxmpB5PBh5dGGHac6X2YRijAYbzi0TJU5ibsrqj46N6LtPrGlwyJ9v1PxjY+zfLKuNTSYrvENkyFxdEeO44/HwscHn1amQl3sv4ElXxJ3VhhFDfRobm4nr9GG/Na70C5u0ptM0mOZPi5ZZb/X9FTPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=pYsadv+9; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+VZCTW49; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="pYsadv+9"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+VZCTW49" Message-ID: <20241210103335.373392568@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733826851; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0GBO+kXAiZqSYt9BqbnxtGix5vHwVBHq9zW5m+OuaGk=; b=pYsadv+9OFHFUr+wRyxUWeLR6mck8wFJshU5OIlBrbLCcICpw8N8VaPcY/YzOPpWnpbugU BoDo6klEIJcwDl1VJh0JRHXYoWkNFlMSlSVbOrxRs2sH4uMI041jr+11Bx7tAQpdYl2pNK BJrUJm7TqbUfesKmP+/5ORmYlEEqEUGKyLyashDG2EaQdx9mBQ0en7nqn8m8Mri48c5JVR dlCUCjLfChSFOHrcq5AWJNZtwrGDsnqptb2W9FM4M8QkdY/dff6G9EaDzgX/eAEMs4bAAe lsmDLRDBMjz1DYmdrN26P5M5nrlwP3DbgQ/I3B7kypYucgEnh///peW3qEz4DQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733826851; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0GBO+kXAiZqSYt9BqbnxtGix5vHwVBHq9zW5m+OuaGk=; b=+VZCTW49ETrI57GT7tJ4x9pE+mqtMUM/Jb/uNS28y8lJoN/rOUoQvtflcLr7l4bUEaOnYd cFxzAKJuk9oe6qDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Anup Patel , Vineet Gupta , Brian Cain , Wei Liu , Steve Wahl , Joerg Roedel , Lu Baolu , Juergen Gross Subject: [patch 1/5] ARC: Remove GENERIC_PENDING_IRQ References: <20241210102148.760383417@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 10 Dec 2024 11:34:10 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nothing uses the actual functionality and the MCIP controller sets the flags which disables the deferred affinity change. The other interrupt controller does not support affinity setting at all. Signed-off-by: Thomas Gleixner Cc: Vineet Gupta Acked-by: Vineet Gupta =C2=A0=C2=A0 # arch/arc/ --- arch/arc/Kconfig | 1 - arch/arc/kernel/mcip.c | 2 -- kernel/irq/debugfs.c | 1 + 3 files changed, 1 insertion(+), 3 deletions(-) --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -24,7 +24,6 @@ config ARC # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP - select GENERIC_PENDING_IRQ if SMP select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD select GENERIC_IOREMAP --- a/arch/arc/kernel/mcip.c +++ b/arch/arc/kernel/mcip.c @@ -357,8 +357,6 @@ static void idu_cascade_isr(struct irq_d static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_num= ber_t hwirq) { irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); - irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); - return 0; } =20 --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c @@ -53,6 +53,7 @@ static const struct irq_bit_descr irqchi BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI), BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND), BIT_MASK_DESCR(IRQCHIP_IMMUTABLE), + BIT_MASK_DESCR(IRQCHIP_MOVE_DEFERRED), }; =20 static void From nobody Sun Dec 14 13:41:11 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CB8A2080D5 for ; Tue, 10 Dec 2024 10:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826861; cv=none; b=I1knexBfJrq4gvr4HCpyTH4bWCjN8Ppe/lGdcCbl829KiiRslcstt45cygDTBVz3Vi/ktzXd5D8GmYxhZ1q0+s/7EZlGzoydsTZZM8KWPJxh6k/NMvBh2zimmjS5jTiFLJ4yvoljM8tk1j5db6P2d4M+S2ijFi3U1/ximou3pe8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826861; c=relaxed/simple; bh=KRTeLC5ZJhLeAcNruUPzCpQvyrEU2oMR+PrDzurcda4=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=A4nvqqKc6kHaLgBwDTATThl4JaMC4NFkwsN2yVuwns0Ek3tuOoh9bO3na20ONBqOCmdTXJge/wIV8bfq448e/80oe13NOtKC4oWWpWZAVFaEkK7yyh978F+rWKBV/QoGrelRgU2gXIeS+CI9LMS8HIpdoahjjrhLxa3iiMhcZbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Dzc69xfQ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jYD5flwe; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Dzc69xfQ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jYD5flwe" Message-ID: <20241210103335.437630614@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733826853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VKJDVibaFNX2XMzoNIdJWCjP6hyGiA9FSsEH64oOzvg=; b=Dzc69xfQiiM3L6gFeMxYsA6dfuK5Ww9qmF564w0JvM5pgbpif1mtFuhaISqdH01YjfqpIO nXBtTawxxZweTx9ej5YM0ZQpRYcBi3VsQ3Rb2ZXtUjA/vJDxIcOC4upyHtDije2PVhHRFU oHH491gmq1mUm7oBDMrJ9OrULt5pb/epvY3LXTvXFSdTQJM9v0E5i17L2AxLjr0H6d/IMB WzaIJggILIdjIHXFYY+2QU68b33mW4efAKOZ7fYlaUuFUzFb+v720Gpo5CpnchtUF22+L1 9nf9vC0ChAjY5hX3eXnspYwK3rys/NYcMCqn/MMa26w7NIExu1kDHxKJ/Pp/yg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733826853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VKJDVibaFNX2XMzoNIdJWCjP6hyGiA9FSsEH64oOzvg=; b=jYD5flweEkD8yOGSA4OE7SMxBnPGXq4A+SPeyWCBkPl6I8j+Pyckal5jM8R6eslAnYd+R+ zuvg7Qtze7RlnsDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Anup Patel , Brian Cain , Vineet Gupta , Wei Liu , Steve Wahl , Joerg Roedel , Lu Baolu , Juergen Gross Subject: [patch 2/5] hexagon: Remove GENERIC_PENDING_IRQ leftover References: <20241210102148.760383417@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 10 Dec 2024 11:34:12 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commented out since 2011.... Signed-off-by: Thomas Gleixner Cc: Brian Cain --- arch/hexagon/Kconfig | 1 - 1 file changed, 1 deletion(-) --- a/arch/hexagon/Kconfig +++ b/arch/hexagon/Kconfig @@ -20,7 +20,6 @@ config HEXAGON # select ARCH_HAS_CPU_IDLE_WAIT # select GPIOLIB # select HAVE_CLK - # select GENERIC_PENDING_IRQ if SMP select GENERIC_ATOMIC64 select HAVE_PERF_EVENTS # GENERIC_ALLOCATOR is used by dma_alloc_coherent() From nobody Sun Dec 14 13:41:11 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B1F8210F54 for ; Tue, 10 Dec 2024 10:34:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826864; cv=none; b=DU+FoT8E3kkHto1OCyivzKwxqlTwxrDG97hjlQuxmrarUILvA0zqqOMU0AAh1Th52+cIIV+WnIS6/9x7PP6RRAEreCXk/2yTsBvHOaIKGkn0AuLUXNWCbtN0HSLvrKIbr0MjBDIafl5JnBktBAbgbYw1bASV60lmPwp0OCqajWk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826864; c=relaxed/simple; bh=J/6HxjJew/LGYhubznOX5TMU1BpkqtPtYkZJmW0nVGw=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=V/1CwR2t2Uc/ZvArrqnua1i3mhystSyIYxWfvsIRCRxvTsgKZRbvkWL17X5y8Yb01qTwbk6b8LiaUdih3Xucbr2eIp+frbq5LuToi9Ezgy1FqzWLzvDhEI/OGe0b3/Y1LgVu/JH/5G6QFpvGKOpYNBlGAkrSofbBCRG52QxEcoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WHaoYXCR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=UqBdfxwZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WHaoYXCR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="UqBdfxwZ" Message-ID: <20241210103335.500314436@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733826854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=sn6OR2UAKgql9hXOpQOx0ZOiWncZqBg4HOFQtaeau8U=; b=WHaoYXCRfDMtYB0zI2TucVkKC38k7sRjJCe23k4P/JVwIEGw47THqSVSQNjvT7QHgnucHS OvE+uhv6cFq0QoXRAYdGckr51I3wLnaQJQm3Xx4i3YEV3Rj7YPE5wrgdx1ajw8QlplyAWS Zoz1QBJ6OS7P5QnS2bnVTu6rxHH6KU31mKRKQ+Lg8u4n9ZFLqmGFmSe6Ubq9qt2fUorWUa 6qZPnJ0xRPYxEJhK5UA2VHJZivH3ssnqBeAGLGm1VS5Mi+oaxTVlaYmU2W3tyToSJikwBT RId3L7cJvO5zz/Ia3y+Lqvd1qtBIheJOvscNCsoDqTWXcWDH394I0uAHKmlkXw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733826854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=sn6OR2UAKgql9hXOpQOx0ZOiWncZqBg4HOFQtaeau8U=; b=UqBdfxwZ6wHefk7qF/uYXbZaBATqK5+rjGpXwSUAu1Skl+qinbO+TgIbwfmU36XrwW/XmV /Z8KLMtsnp2xoNCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Anup Patel , Vineet Gupta , Brian Cain , Wei Liu , Steve Wahl , Joerg Roedel , Lu Baolu , Juergen Gross Subject: [patch 3/5] genirq: Provide IRQCHIP_MOVE_DEFERRED References: <20241210102148.760383417@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 10 Dec 2024 11:34:14 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The logic of GENERIC_PENDING_IRQ is backwards for historical reasons. Most interrupt controllers allow to move the interrupt from arbitrary contexts. If GENERIC_PENDING_IRQ is enabled by an architecture to support a chip, which requires the affinity change to happen in interrupt context, all other chips have to be marked with IRQF_MOVE_PCNTXT. That's tedious and there is no real good reason for the extra flags in the irq descriptor and the irq data status fields. In fact the decision whether interrupts can be moved in arbitrary context or not is a property of the interrupt chip. To simplify adoption for RISC-V provide a new mechanism which is enabled via a config switch and allows to add a flag to irq_chip::flags to request that interrupt affinity changes are deferred. Setting the top level chip of an interrupt evaluates the flag and maps it into the existing logic. The config switch and the various PCNTXT flags are temporary until x86 is converted over to this scheme. This intermediate step also allows trivial backporting of the mechanism to plug the affinity change race of various RISC-V interrupt controllers. Signed-off-by: Thomas Gleixner --- include/linux/irq.h | 2 ++ kernel/irq/Kconfig | 4 ++++ kernel/irq/chip.c | 18 +++++++++++++++--- 3 files changed, 21 insertions(+), 3 deletions(-) --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -567,6 +567,7 @@ struct irq_chip { * in the suspend path if they are in d= isabled state * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before start= up * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip + * IRQCHIP_MOVE_DEFERRED: Move the interrupt in actual interrupt con= text */ enum { IRQCHIP_SET_TYPE_MASKED =3D (1 << 0), @@ -581,6 +582,7 @@ enum { IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND =3D (1 << 9), IRQCHIP_AFFINITY_PRE_STARTUP =3D (1 << 10), IRQCHIP_IMMUTABLE =3D (1 << 11), + IRQCHIP_MOVE_DEFERRED =3D (1 << 12), }; =20 #include --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -31,6 +31,10 @@ config GENERIC_IRQ_EFFECTIVE_AFF_MASK config GENERIC_PENDING_IRQ bool =20 +# Deduce delayed migration from top-level interrupt chip flags +config GENERIC_PENDING_IRQ_CHIPFLAGS + bool + # Support for generic irq migrating off cpu before the cpu is offline. config GENERIC_IRQ_MIGRATION bool --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -47,6 +47,13 @@ int irq_set_chip(unsigned int irq, const return -EINVAL; =20 desc->irq_data.chip =3D (struct irq_chip *)(chip ?: &no_irq_chip); + + if (IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS) && chip) { + if (chip->flags & IRQCHIP_MOVE_DEFERRED) + irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT); + else + irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); + } irq_put_desc_unlock(desc, flags); /* * For !CONFIG_SPARSE_IRQ make the irq show up in @@ -1114,16 +1121,21 @@ void irq_modify_status(unsigned int irq, trigger =3D irqd_get_trigger_type(&desc->irq_data); =20 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | - IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); + IRQD_TRIGGER_MASK | IRQD_LEVEL); if (irq_settings_has_no_balance_set(desc)) irqd_set(&desc->irq_data, IRQD_NO_BALANCING); if (irq_settings_is_per_cpu(desc)) irqd_set(&desc->irq_data, IRQD_PER_CPU); - if (irq_settings_can_move_pcntxt(desc)) - irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); if (irq_settings_is_level(desc)) irqd_set(&desc->irq_data, IRQD_LEVEL); =20 + /* Keep this around until x86 is converted over */ + if (!IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS)) { + irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT); + if (irq_settings_can_move_pcntxt(desc)) + irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); + } + tmp =3D irq_settings_get_trigger_mask(desc); if (tmp !=3D IRQ_TYPE_NONE) trigger =3D tmp; From nobody Sun Dec 14 13:41:11 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE02823DEAC for ; Tue, 10 Dec 2024 10:34:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826859; cv=none; b=W5L8B90FqVRA3ydcES4phb01JEDKUzcnelruV3fuhxgUkhfGd3t5JIeQk6oCx+zuNxSyOShwfg/U8azdRY60nqOsexeZEH/uK2RbWA34QvdkiDqktzFPm7c9FFJQGUbfPGU7TiGVtTWk2RoHsCex6Tj2MXI5Ink29cVdP6me1Cs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826859; c=relaxed/simple; bh=50hjnL6/kwp+wasxvFJmUdYywUs9rRLs0MrZrePqjZQ=; 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a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733826856; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FUc3H37fA9rOswJxSZX3b2bKHt1EFh0JW7lQda1YR7Y=; b=yeN6a27/ykOS9NxJw6WhnWX6bgPgSiVwj8BQ8aibleAXN5epMjrU5ubhW1f0cHuNpxdCio Syjc8vdmb7/7wWTz0QX7aaXdBhPkz5u+rteDALPnZck7jQc0hSno4uNJu5xXRgmxQBcEWW c/YI1B1czTcMCTZic5AF1cLbUA7A3apL7fj6lLmaSvhkn9yI+s8y6eBmlfKeuLkmweBsB2 QJdnV9y7nUaDLqpWiB6/qhYyesikIjUq2PDnCJzV14Chs8qsbmjAdQJoG4Jo4K/kjO8TZI cHlk9lzMhidjLwy+cVBOfNc2h9huIpv+SAUSJIPF63oLSKxa2zmXUKcDZmRt1w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733826856; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FUc3H37fA9rOswJxSZX3b2bKHt1EFh0JW7lQda1YR7Y=; b=s94ZxbjHH9Ey2QqMNp2lD3tKXK2HY11BAXqnAsaPCMFi0zHmD/yNLUUQ5PVYhorz1awOSC Oo/UWnNZ/GuvWrCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Anup Patel , Wei Liu , Steve Wahl , Joerg Roedel , Lu Baolu , Juergen Gross , Vineet Gupta , Brian Cain Subject: [patch 4/5] x86/apic: Convert to IRQCHIP_MOVE_DEFERRED References: <20241210102148.760383417@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 10 Dec 2024 11:34:15 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of marking individual interrupts as safe to be migrated in arbitrary contexts, mark the interrupt chips, which require the interrupt to be moved in actual interrupt context, with the new IRQCHIP_MOVE_DEFERRED flag. This makes more sense because this is a per interrupt chip property and not restricted to individual interrupts. That flips the logic from the historical opt-out to a opt-in model. This is simpler to handle for other architectures, which default to unrestricted affinity setting. It also allows to cleanup the redundant core logic significantly. All interrupt chips, which belong to a top-level domain sitting directly on top of the x86 vector domain are marked accordingly, unless the related setup code marks the interrupts with IRQ_MOVE_PCNTXT, i.e. XEN. No functional change intended. Signed-off-by: Thomas Gleixner Cc: Wei Liu Cc: Steve Wahl Cc: Joerg Roedel Cc: Lu Baolu Cc: Juergen Gross Acked-by: Wei Liu Reviewed-by: Steve Wahl --- arch/x86/Kconfig | 1 + arch/x86/hyperv/irqdomain.c | 2 +- arch/x86/kernel/apic/io_apic.c | 2 +- arch/x86/kernel/apic/msi.c | 3 ++- arch/x86/kernel/hpet.c | 8 -------- arch/x86/platform/uv/uv_irq.c | 2 -- drivers/iommu/amd/init.c | 2 +- drivers/iommu/amd/iommu.c | 1 - drivers/iommu/intel/irq_remapping.c | 1 - drivers/pci/controller/pci-hyperv.c | 1 + drivers/xen/events/events_base.c | 6 ------ 11 files changed, 7 insertions(+), 22 deletions(-) --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -173,6 +173,7 @@ config X86 select GENERIC_IRQ_RESERVATION_MODE select GENERIC_IRQ_SHOW select GENERIC_PENDING_IRQ if SMP + select GENERIC_PENDING_IRQ_CHIPFLAGS if SMP select GENERIC_PTDUMP select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL --- a/arch/x86/hyperv/irqdomain.c +++ b/arch/x86/hyperv/irqdomain.c @@ -304,7 +304,7 @@ static struct irq_chip hv_pci_msi_contro .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_compose_msi_msg =3D hv_irq_compose_msi_msg, .irq_set_affinity =3D msi_domain_set_affinity, - .flags =3D IRQCHIP_SKIP_SET_WAKE, + .flags =3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MOVE_DEFERRED, }; =20 static struct msi_domain_ops pci_msi_domain_ops =3D { --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1861,7 +1861,7 @@ static struct irq_chip ioapic_chip __rea .irq_set_affinity =3D ioapic_set_affinity, .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_get_irqchip_state =3D ioapic_irq_get_chip_state, - .flags =3D IRQCHIP_SKIP_SET_WAKE | + .flags =3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MOVE_DEFERRED | IRQCHIP_AFFINITY_PRE_STARTUP, }; =20 --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -214,6 +214,7 @@ static bool x86_init_dev_msi_info(struct if (WARN_ON_ONCE(domain !=3D real_parent)) return false; info->chip->irq_set_affinity =3D msi_set_affinity; + info->chip->flags |=3D IRQCHIP_MOVE_DEFERRED; break; case DOMAIN_BUS_DMAR: case DOMAIN_BUS_AMDVI: @@ -315,7 +316,7 @@ static struct irq_chip dmar_msi_controll .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_compose_msi_msg =3D dmar_msi_compose_msg, .irq_write_msi_msg =3D dmar_msi_write_msg, - .flags =3D IRQCHIP_SKIP_SET_WAKE | + .flags =3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MOVE_DEFERRED | IRQCHIP_AFFINITY_PRE_STARTUP, }; =20 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -516,22 +516,14 @@ static int hpet_msi_init(struct irq_doma struct msi_domain_info *info, unsigned int virq, irq_hw_number_t hwirq, msi_alloc_info_t *arg) { - irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL, handle_edge_irq, arg->data, "edge"); =20 return 0; } =20 -static void hpet_msi_free(struct irq_domain *domain, - struct msi_domain_info *info, unsigned int virq) -{ - irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); -} - static struct msi_domain_ops hpet_msi_domain_ops =3D { .msi_init =3D hpet_msi_init, - .msi_free =3D hpet_msi_free, }; =20 static struct msi_domain_info hpet_msi_domain_info =3D { --- a/arch/x86/platform/uv/uv_irq.c +++ b/arch/x86/platform/uv/uv_irq.c @@ -92,8 +92,6 @@ static int uv_domain_alloc(struct irq_do if (ret >=3D 0) { if (info->uv.limit =3D=3D UV_AFFINITY_CPU) irq_set_status_flags(virq, IRQ_NO_BALANCING); - else - irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); =20 chip_data->pnode =3D uv_blade_to_pnode(info->uv.blade); chip_data->offset =3D info->uv.offset; --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2332,7 +2332,7 @@ static struct irq_chip intcapxt_controll .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_set_affinity =3D intcapxt_set_affinity, .irq_set_wake =3D intcapxt_set_wake, - .flags =3D IRQCHIP_MASK_ON_SUSPEND, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_MOVE_DEFERRED, }; =20 static const struct irq_domain_ops intcapxt_domain_ops =3D { --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3532,7 +3532,6 @@ static int irq_remapping_alloc(struct ir irq_data->chip_data =3D data; irq_data->chip =3D &amd_ir_chip; irq_remapping_prepare_irte(data, cfg, info, devid, index, i); - irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); } =20 return 0; --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1463,7 +1463,6 @@ static int intel_irq_remapping_alloc(str else irq_data->chip =3D &intel_ir_chip; intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i); - irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); } return 0; =20 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -2053,6 +2053,7 @@ static struct irq_chip hv_msi_irq_chip =3D .irq_set_affinity =3D irq_chip_set_affinity_parent, #ifdef CONFIG_X86 .irq_ack =3D irq_chip_ack_parent, + .flags =3D IRQCHIP_MOVE_DEFERRED, #elif defined(CONFIG_ARM64) .irq_eoi =3D irq_chip_eoi_parent, #endif --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -722,12 +722,6 @@ static struct irq_info *xen_irq_init(uns INIT_RCU_WORK(&info->rwork, delayed_free_irq); =20 set_info_for_irq(irq, info); - /* - * Interrupt affinity setting can be immediate. No point - * in delaying it until an interrupt is handled. - */ - irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); - INIT_LIST_HEAD(&info->eoi_list); list_add_tail(&info->list, &xen_irq_list_head); } From nobody Sun Dec 14 13:41:11 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 915C32080D7 for ; Tue, 10 Dec 2024 10:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826862; cv=none; b=NP7jNXddNVh3b65WkYV65HUSfMA2IqNM1G1quhCmT71gvDaWnxY0uXKB49TR7dJbP0uPmHpZxN7JiASlZ7pM5SO2DwRIJBRuuGEb96xqGknhUbpR5d+huorgAx67SdROEywHgGcpuj+evX6Kd/MRdHg2MEkQt/xgTsTh9l8lHAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733826862; c=relaxed/simple; bh=kkUkaSLB+A3b5oNaOfn6H7NWYF11wNPQSI4Rqw4dE0Y=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=H8DFwbOWZmFPzJgwpVeVeWvVafj5WA6RGjm0x1vBdTqFLDUqEC36C3pQsuKyVxhMao24lK7LeKFAe6hgu1rXIxqpmGtwR+HeaCOrjBe4ICaGFTkfGJLJscAHLCJknr4wumzBqWH5Ln79bnyuTFe4FWCJIyMNORfg3iP8PcXoxAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fFfNGOVF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jJH3lJ5j; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fFfNGOVF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jJH3lJ5j" Message-ID: <20241210103335.626707225@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733826858; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5aTYhXT8OhSS4alOlqf6d0ntHhzH/LyWqanpwxxQXlo=; b=fFfNGOVFub+E8J2AZOf7i2O/TH5FehToC3RaXPsZTxncbXmNZZyhOtZj4pwNQQ5RRIBT4k AEqnJzX3PoXYhdTgl2v8mRKfGY6AHst4Poni8iN5Ghd06tZFYRrvJLW+261TAzKLCxp3sZ qVrjmXvb3TuJtCe2NgxQPpJQa06s3kMmZqJu4NqNjhPEPNt6zTOVYFTA+5XlmnCcWPxsjE XpbTjKWtpF88WePR0wMHlk9at5abEKqn4a5Cn2VRbuiadBXZYZM9/Qz1id2l1pv7q60qXq WaNJmzEPUv1bF848xdnjbYzSZEWZDWdJO0z6t9Q8muQabC6QasV6gg/a3YZMkg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733826858; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5aTYhXT8OhSS4alOlqf6d0ntHhzH/LyWqanpwxxQXlo=; b=jJH3lJ5jF2dS03ZzbAaTJQ09ze/Ay7KGkYcCQeq1UdDfz+/iz7RL7LhbQDdtj5bEgFjnl/ tfHBnqKPemHG/cAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Anup Patel , Vineet Gupta , Brian Cain , Wei Liu , Steve Wahl , Joerg Roedel , Lu Baolu , Juergen Gross Subject: [patch 5/5] genirq: Remove IRQ_MOVE_PCNTXT and related code References: <20241210102148.760383417@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 10 Dec 2024 11:34:17 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that x86 is converted over to use the IRQCHIP_MOVE_DEFERRED flags, remove IRQ*_MOVE_PCNTXT and related code. Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 1 - include/linux/irq.h | 12 +----------- kernel/irq/chip.c | 14 -------------- kernel/irq/debugfs.c | 1 - kernel/irq/internals.h | 2 +- kernel/irq/settings.h | 6 ------ 6 files changed, 2 insertions(+), 34 deletions(-) --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -173,7 +173,6 @@ config X86 select GENERIC_IRQ_RESERVATION_MODE select GENERIC_IRQ_SHOW select GENERIC_PENDING_IRQ if SMP - select GENERIC_PENDING_IRQ_CHIPFLAGS if SMP select GENERIC_PTDUMP select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -64,7 +64,6 @@ enum irqchip_irq_state; * IRQ_NOAUTOEN - Interrupt is not automatically enabled in * request/setup_irq() * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) - * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context * IRQ_NESTED_THREAD - Interrupt nests into another thread * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable * IRQ_IS_POLLED - Always polled by another interrupt. Exclude @@ -93,7 +92,6 @@ enum { IRQ_NOREQUEST =3D (1 << 11), IRQ_NOAUTOEN =3D (1 << 12), IRQ_NO_BALANCING =3D (1 << 13), - IRQ_MOVE_PCNTXT =3D (1 << 14), IRQ_NESTED_THREAD =3D (1 << 15), IRQ_NOTHREAD =3D (1 << 16), IRQ_PER_CPU_DEVID =3D (1 << 17), @@ -105,7 +103,7 @@ enum { =20 #define IRQF_MODIFY_MASK \ (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ - IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ + IRQ_NOAUTOEN | IRQ_LEVEL | IRQ_NO_BALANCING | \ IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) =20 @@ -201,8 +199,6 @@ struct irq_data { * IRQD_LEVEL - Interrupt is level triggered * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup * from suspend - * IRQD_MOVE_PCNTXT - Interrupt can be moved in process - * context * IRQD_IRQ_DISABLED - Disabled state of the interrupt * IRQD_IRQ_MASKED - Masked state of the interrupt * IRQD_IRQ_INPROGRESS - In progress state of the interrupt @@ -233,7 +229,6 @@ enum { IRQD_AFFINITY_SET =3D BIT(12), IRQD_LEVEL =3D BIT(13), IRQD_WAKEUP_STATE =3D BIT(14), - IRQD_MOVE_PCNTXT =3D BIT(15), IRQD_IRQ_DISABLED =3D BIT(16), IRQD_IRQ_MASKED =3D BIT(17), IRQD_IRQ_INPROGRESS =3D BIT(18), @@ -338,11 +333,6 @@ static inline bool irqd_is_wakeup_set(st return __irqd_to_state(d) & IRQD_WAKEUP_STATE; } =20 -static inline bool irqd_can_move_in_process_context(struct irq_data *d) -{ - return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; -} - static inline bool irqd_irq_disabled(struct irq_data *d) { return __irqd_to_state(d) & IRQD_IRQ_DISABLED; --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -47,13 +47,6 @@ int irq_set_chip(unsigned int irq, const return -EINVAL; =20 desc->irq_data.chip =3D (struct irq_chip *)(chip ?: &no_irq_chip); - - if (IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS) && chip) { - if (chip->flags & IRQCHIP_MOVE_DEFERRED) - irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT); - else - irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); - } irq_put_desc_unlock(desc, flags); /* * For !CONFIG_SPARSE_IRQ make the irq show up in @@ -1129,13 +1122,6 @@ void irq_modify_status(unsigned int irq, if (irq_settings_is_level(desc)) irqd_set(&desc->irq_data, IRQD_LEVEL); =20 - /* Keep this around until x86 is converted over */ - if (!IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS)) { - irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT); - if (irq_settings_can_move_pcntxt(desc)) - irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); - } - tmp =3D irq_settings_get_trigger_mask(desc); if (tmp !=3D IRQ_TYPE_NONE) trigger =3D tmp; --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c @@ -109,7 +109,6 @@ static const struct irq_bit_descr irqdat BIT_MASK_DESCR(IRQD_NO_BALANCING), =20 BIT_MASK_DESCR(IRQD_SINGLE_TARGET), - BIT_MASK_DESCR(IRQD_MOVE_PCNTXT), BIT_MASK_DESCR(IRQD_AFFINITY_SET), BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING), BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED), --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -421,7 +421,7 @@ irq_init_generic_chip(struct irq_chip_ge #ifdef CONFIG_GENERIC_PENDING_IRQ static inline bool irq_can_move_pcntxt(struct irq_data *data) { - return irqd_can_move_in_process_context(data); + return !(data->chip->flags & IRQCHIP_MOVE_DEFERRED); } static inline bool irq_move_pending(struct irq_data *data) { --- a/kernel/irq/settings.h +++ b/kernel/irq/settings.h @@ -11,7 +11,6 @@ enum { _IRQ_NOREQUEST =3D IRQ_NOREQUEST, _IRQ_NOTHREAD =3D IRQ_NOTHREAD, _IRQ_NOAUTOEN =3D IRQ_NOAUTOEN, - _IRQ_MOVE_PCNTXT =3D IRQ_MOVE_PCNTXT, _IRQ_NO_BALANCING =3D IRQ_NO_BALANCING, _IRQ_NESTED_THREAD =3D IRQ_NESTED_THREAD, _IRQ_PER_CPU_DEVID =3D IRQ_PER_CPU_DEVID, @@ -142,11 +141,6 @@ static inline void irq_settings_set_nopr desc->status_use_accessors |=3D _IRQ_NOPROBE; } =20 -static inline bool irq_settings_can_move_pcntxt(struct irq_desc *desc) -{ - return desc->status_use_accessors & _IRQ_MOVE_PCNTXT; -} - static inline bool irq_settings_can_autoenable(struct irq_desc *desc) { return !(desc->status_use_accessors & _IRQ_NOAUTOEN);