From nobody Sun Feb 8 17:52:44 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25E9C1DC9B9 for ; Tue, 10 Dec 2024 09:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733823397; cv=none; b=GGRRRhcsxpYAM8bYKn74N9c3apYydOQBdUH4WgItdmw/iXR1HlMuS2cbaH66m7d0aBR5mjiHo6fvF1nQPVTg5YbvbJxK9bhszvj+nygXj680AS274365nq6jDQ6PjelED8bCErOTZ7PDfFGq/APU+lv4vwbAu2IDN+zJDCVDxTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733823397; c=relaxed/simple; bh=10LZqXVa0XlZajs7yy4vLLl+ywHGqExXm3/iP5F5wdw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LDEMsZWsFj3ogtwvaW2NuA8ipZ8U5Ze+UGqRSyJtVSRDbIt82abTWcKTS10ilr6uFn79H2if/YKWnVP2lyLh0Y1TvGBw8bEZPJLny74z0VCLydV/JpbjgQqzNl7C6kvInlXq7s0Z+cAIWudFIsuAbxVQ8P4+qtjDkGrrGUyvOeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=DidLOGN1; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="DidLOGN1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1733823393; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LLFrnYQ41CCOjuPl6f8oeYH5LOqoEfmgCGYQJHMDPKs=; b=DidLOGN19P0IWMLVePVmqrKRrx32llkPOld/Mab7XOKZt015qLKUfhIEmedT4UjYNdqBYZ crnz+ir80km/VBBAVVnzwsaTKaSAZJcdabXxko+49hb7iKme7CHd5OzB5U2OdnQ+I7QZjX bjeoOUfdzAPzQ3FuruxmwQDxJywPvnw= Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-647-fCaUkOwjM366NjmNrt3Mwg-1; Tue, 10 Dec 2024 04:36:29 -0500 X-MC-Unique: fCaUkOwjM366NjmNrt3Mwg-1 X-Mimecast-MFC-AGG-ID: fCaUkOwjM366NjmNrt3Mwg Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id EF1251955DB9; Tue, 10 Dec 2024 09:36:27 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.193.39]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A31BF195608A; Tue, 10 Dec 2024 09:36:24 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v3 1/6] drm/i915/fbdev: Add intel_fbdev_get_vaddr() Date: Tue, 10 Dec 2024 10:28:41 +0100 Message-ID: <20241210093505.589893-2-jfalempe@redhat.com> In-Reply-To: <20241210093505.589893-1-jfalempe@redhat.com> References: <20241210093505.589893-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" The vaddr of the fbdev framebuffer is private to the struct intel_fbdev, so this function is needed to access it for drm_panic. Also the struct i915_vma is different between i915 and xe, so it requires a few functions to access fbdev->vma->iomap. Signed-off-by: Jocelyn Falempe --- v2: * Add intel_fb_get_vaddr() and i915_vma_get_iomap() to build with Xe drive= r. drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fb_pin.h | 1 + drivers/gpu/drm/i915/display/intel_fbdev.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fbdev.h | 6 ++++++ drivers/gpu/drm/i915/i915_vma.h | 5 +++++ drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++++ 6 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/= i915/display/intel_fb_pin.c index d3a86f9c6bc86..c44019c7ab56b 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -327,3 +327,8 @@ void intel_plane_unpin_fb(struct intel_plane_state *old= _plane_state) intel_dpt_unpin_from_ggtt(fb->dpt_vm); } } + +void *intel_fb_get_vaddr(struct i915_vma *vma) +{ + return i915_vma_get_iomap(vma); +} diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/= i915/display/intel_fb_pin.h index ac0319b53af08..0141f5f2b1c7a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -25,5 +25,6 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned lo= ng flags); =20 int intel_plane_pin_fb(struct intel_plane_state *plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); +void *intel_fb_get_vaddr(struct i915_vma *vma); =20 #endif diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i= 915/display/intel_fbdev.c index 00852ff5b2470..1d12d1c047d02 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -695,3 +695,8 @@ struct intel_framebuffer *intel_fbdev_framebuffer(struc= t intel_fbdev *fbdev) =20 return to_intel_framebuffer(fbdev->helper.fb); } + +void *intel_fbdev_get_vaddr(struct intel_fbdev *fbdev) +{ + return intel_fb_get_vaddr(fbdev->vma); +} diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i= 915/display/intel_fbdev.h index 08de2d5b34338..f033d4f1efe96 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -17,6 +17,7 @@ struct intel_framebuffer; void intel_fbdev_setup(struct drm_i915_private *dev_priv); void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synch= ronous); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbde= v); +void *intel_fbdev_get_vaddr(struct intel_fbdev *fbdev); #else static inline void intel_fbdev_setup(struct drm_i915_private *dev_priv) { @@ -30,6 +31,11 @@ static inline struct intel_framebuffer *intel_fbdev_fram= ebuffer(struct intel_fbd { return NULL; } + +static inline void *intel_fbdev_get_vaddr(struct intel_fbdev *fbdev) +{ + return NULL; +} #endif =20 #endif /* __INTEL_FBDEV_H__ */ diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vm= a.h index 6a6be8048aa83..4ae610927fa77 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -353,6 +353,11 @@ static inline bool i915_node_color_differs(const struc= t drm_mm_node *node, return drm_mm_node_allocated(node) && node->color !=3D color; } =20 +static inline void __iomem *i915_vma_get_iomap(struct i915_vma *vma) +{ + return READ_ONCE(vma->iomap); +} + /** * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the apert= ure * @vma: VMA to iomap diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/di= splay/xe_fb_pin.c index 761510ae06904..576b1e98f39cd 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -421,3 +421,8 @@ u64 intel_dpt_offset(struct i915_vma *dpt_vma) { return 0; } + +void *intel_fb_get_vaddr(struct i915_vma *vma) +{ + return NULL; +} --=20 2.47.1 From nobody Sun Feb 8 17:52:44 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F23DE2080ED for ; Tue, 10 Dec 2024 09:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 10 Dec 2024 09:36:31 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.193.39]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8E4BB1956089; Tue, 10 Dec 2024 09:36:28 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v3 2/6] drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes Date: Tue, 10 Dec 2024 10:28:42 +0100 Message-ID: <20241210093505.589893-3-jfalempe@redhat.com> In-Reply-To: <20241210093505.589893-1-jfalempe@redhat.com> References: <20241210093505.589893-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. Signed-off-by: Jocelyn Falempe --- drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index 17a1e3801a85c..671d3914585bf 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -848,6 +848,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = =3D { .format_mod_supported =3D i8xx_plane_format_mod_supported, }; =20 +static void i9xx_disable_tiling(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv =3D to_i915(plane->base.dev); + enum i9xx_plane_id i9xx_plane =3D plane->i9xx_plane; + u32 dspcntr; + u32 reg; + + dspcntr =3D intel_de_read_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); + dspcntr &=3D ~DISP_TILED; + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + + if (DISPLAY_VER(dev_priv) >=3D 4) { + reg =3D intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane)); + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), reg); + + } else { + reg =3D intel_de_read_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane)); + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), reg); + } +} + struct intel_plane * intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pi= pe) { @@ -973,6 +994,8 @@ intel_primary_plane_create(struct drm_i915_private *dev= _priv, enum pipe pipe) plane->disable_flip_done =3D ilk_primary_disable_flip_done; } =20 + plane->disable_tiling =3D i9xx_disable_tiling; + modifiers =3D intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILI= NG_X); =20 if (DISPLAY_VER(dev_priv) >=3D 5 || IS_G4X(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index ff6eb93337e0a..31804fb99e168 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1482,6 +1482,8 @@ struct intel_plane { bool async_flip); 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charset="utf-8" drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. Signed-off-by: Jocelyn Falempe --- .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index 038ca2ec5d7a6..e2a54547a29d5 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2575,6 +2575,25 @@ static u8 skl_get_plane_caps(struct drm_i915_private= *i915, return caps; } =20 +static void skl_disable_tiling(struct intel_plane *plane) +{ + u32 plane_ctl; + struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); + struct drm_i915_private *dev_priv =3D to_i915(plane->base.dev); + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + + plane_ctl =3D intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane->id)); + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + + intel_de_write_fw(dev_priv, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); 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charset="utf-8" Prepare the work for drm_panic support. This is used to map the current framebuffer, so the CPU can overwrite it with the panic message. Signed-off-by: Jocelyn Falempe --- drivers/gpu/drm/i915/display/intel_bo.c | 10 +++++++++ drivers/gpu/drm/i915/display/intel_bo.h | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 25 ++++++++++++++++++++++ drivers/gpu/drm/xe/display/intel_bo.c | 11 ++++++++++ 5 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915= /display/intel_bo.c index fbd16d7b58d95..5eeb3ba827edf 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -22,6 +22,11 @@ bool intel_bo_is_shmem(struct drm_gem_object *obj) return i915_gem_object_is_shmem(to_intel_bo(obj)); } =20 +bool intel_bo_has_iomem(struct drm_gem_object *obj) +{ + return i915_gem_object_has_iomem(to_intel_bo(obj)); +} + bool intel_bo_is_protected(struct drm_gem_object *obj) { return i915_gem_object_is_protected(to_intel_bo(obj)); @@ -57,3 +62,8 @@ void intel_bo_describe(struct seq_file *m, struct drm_gem= _object *obj) { i915_debugfs_describe_obj(m, to_intel_bo(obj)); } + +void *intel_bo_panic_map(struct drm_gem_object *obj) +{ + return i915_gem_object_panic_map(to_intel_bo(obj)); +} diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915= /display/intel_bo.h index ea7a2253aaa57..0eb084955e9af 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -13,6 +13,7 @@ struct vm_area_struct; bool intel_bo_is_tiled(struct drm_gem_object *obj); bool intel_bo_is_userptr(struct drm_gem_object *obj); bool intel_bo_is_shmem(struct drm_gem_object *obj); +bool intel_bo_has_iomem(struct drm_gem_object *obj); bool intel_bo_is_protected(struct drm_gem_object *obj); void intel_bo_flush_if_display(struct drm_gem_object *obj); int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vm= a); @@ -23,5 +24,6 @@ struct intel_frontbuffer *intel_bo_set_frontbuffer(struct= drm_gem_object *obj, struct intel_frontbuffer *front); =20 void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj); +void *intel_bo_panic_map(struct drm_gem_object *obj); =20 #endif /* __INTEL_BO__ */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i= 915/gem/i915_gem_object.h index 3dc61cbd2e11f..f85326a98aefc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -694,6 +694,8 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object = *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj); int i915_gem_object_truncate(struct drm_i915_gem_object *obj); =20 +void *i915_gem_object_panic_map(struct drm_i915_gem_object *obj); + /** * i915_gem_object_pin_map - return a contiguous mapping of the entire obj= ect * @obj: the object to map into kernel address space diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 8780aa2431053..07c33169603c9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -355,6 +355,31 @@ static void *i915_gem_object_map_pfn(struct drm_i915_g= em_object *obj, return vaddr ?: ERR_PTR(-ENOMEM); } =20 +/* Map the current framebuffer for CPU access. Called from panic handler, = so no + * need to pin or cleanup. + */ +void *i915_gem_object_panic_map(struct drm_i915_gem_object *obj) +{ + enum i915_map_type has_type; + void *ptr; + + ptr =3D page_unpack_bits(obj->mm.mapping, &has_type); + + if (ptr) + return ptr; + + if (i915_gem_object_has_struct_page(obj)) + ptr =3D i915_gem_object_map_page(obj, I915_MAP_WB); + else + ptr =3D i915_gem_object_map_pfn(obj, I915_MAP_WB); + + if (IS_ERR(ptr)) + return NULL; + + obj->mm.mapping =3D page_pack_bits(ptr, I915_MAP_WB); + return ptr; +} + /* get, pin, and map the pages of the object into kernel space */ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, enum i915_map_type type) diff --git a/drivers/gpu/drm/xe/display/intel_bo.c b/drivers/gpu/drm/xe/dis= play/intel_bo.c index 9f54fad0f1c0c..c05feeeec3806 100644 --- a/drivers/gpu/drm/xe/display/intel_bo.c +++ b/drivers/gpu/drm/xe/display/intel_bo.c @@ -23,6 +23,11 @@ bool intel_bo_is_shmem(struct drm_gem_object *obj) return false; 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Tue, 10 Dec 2024 09:36:43 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.193.39]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E914B195608A; Tue, 10 Dec 2024 09:36:39 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v3 5/6] drm/i915: Add drm_panic support Date: Tue, 10 Dec 2024 10:28:45 +0100 Message-ID: <20241210093505.589893-6-jfalempe@redhat.com> In-Reply-To: <20241210093505.589893-1-jfalempe@redhat.com> References: <20241210093505.589893-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" This adds drm_panic support for a wide range of Intel GPU. I've tested it only on 2 laptops, Haswell (with 128MB of eDRAM), Cometlake. For hardware using DPT, it's not possible to disable tiling, as you will need to reconfigure the way the GPU is accessing the framebuffer. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 85 ++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index d89630b2d5c19..bafb1421f3b30 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -33,16 +33,20 @@ =20 #include #include +#include =20 #include #include +#include #include #include #include +#include =20 #include "i915_config.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" +#include "intel_bo.h" #include "intel_cdclk.h" #include "intel_cursor.h" #include "intel_display_rps.h" @@ -50,6 +54,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_fbdev.h" #include "skl_scaler.h" #include "skl_watermark.h" =20 @@ -1204,14 +1209,92 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +/* Only used by drm_panic get_scanout_buffer() and panic_flush(), so it is + * protected by the drm panic spinlock + */ +static struct iosys_map panic_map; + +static void intel_panic_flush(struct drm_plane *plane) +{ + struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct drm_i915_private *dev_priv =3D to_i915(plane->dev); + struct drm_framebuffer *fb =3D plane_state->hw.fb; + struct intel_plane *iplane =3D to_intel_plane(plane); + + /* Force a cache flush, otherwise the new pixels won't show up */ + drm_clflush_virt_range(panic_map.vaddr, fb->height * fb->pitches[0]); + + /* Don't disable tiling if it's the fbdev framebuffer.*/ + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(dev_priv->dis= play.fbdev.fbdev)) + return; + + if (fb->modifier && iplane->disable_tiling) + iplane->disable_tiling(iplane); +} + +static int intel_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct intel_plane_state *plane_state; + struct drm_gem_object *obj; + struct drm_framebuffer *fb; + struct drm_i915_private *dev_priv =3D to_i915(plane->dev); + void *ptr; + + if (!plane->state || !plane->state->fb || !plane->state->visible) + return -ENODEV; + + plane_state =3D to_intel_plane_state(plane->state); + fb =3D plane_state->hw.fb; + obj =3D intel_fb_bo(fb); + if (!obj) + return -ENODEV; + + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(dev_priv->dis= play.fbdev.fbdev)) { + ptr =3D intel_fbdev_get_vaddr(dev_priv->display.fbdev.fbdev); + } else { + /* Can't disable tiling if DPT is in use */ + if (intel_fb_uses_dpt(fb)) + return -EOPNOTSUPP; + + ptr =3D intel_bo_panic_map(obj); + } + + if (!ptr) + return -ENOMEM; + + if (intel_bo_has_iomem(obj)) + iosys_map_set_vaddr_iomem(&panic_map, ptr); + else + iosys_map_set_vaddr(&panic_map, ptr); + + sb->map[0] =3D panic_map; + sb->width =3D fb->width; + sb->height =3D fb->height; + sb->format =3D fb->format; + sb->pitch[0] =3D fb->pitches[0]; + + return 0; +} + static const struct drm_plane_helper_funcs intel_plane_helper_funcs =3D { .prepare_fb =3D intel_prepare_plane_fb, .cleanup_fb =3D intel_cleanup_plane_fb, }; =20 +static const struct drm_plane_helper_funcs intel_primary_plane_helper_func= s =3D { + .prepare_fb =3D intel_prepare_plane_fb, + .cleanup_fb =3D intel_cleanup_plane_fb, + .get_scanout_buffer =3D intel_get_scanout_buffer, + .panic_flush =3D intel_panic_flush, +}; + void intel_plane_helper_add(struct intel_plane *plane) { - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); + if (plane->base.type =3D=3D DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); + else + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } =20 void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_pla= ne_state, --=20 2.47.1 From nobody Sun Feb 8 17:52:44 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF82210F61 for ; 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Tue, 10 Dec 2024 04:36:48 -0500 X-MC-Unique: i-BSR-UAO2uk7Hp6W-yqxA-1 X-Mimecast-MFC-AGG-ID: i-BSR-UAO2uk7Hp6W-yqxA Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id CA4271956089; Tue, 10 Dec 2024 09:36:46 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.193.39]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A827E1956089; Tue, 10 Dec 2024 09:36:43 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v3 6/6] drm/i915: Add drm_panic support for Y-tiling with DPT Date: Tue, 10 Dec 2024 10:28:46 +0100 Message-ID: <20241210093505.589893-7-jfalempe@redhat.com> In-Reply-To: <20241210093505.589893-1-jfalempe@redhat.com> References: <20241210093505.589893-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" On Alderlake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements Y-Tiling support, to still be able to draw the panic screen. The Tile-4 support found in the latest Intel GPU will come later. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 70 +++++++++++++++++-- .../drm/i915/display/skl_universal_plane.c | 17 +++-- 2 files changed, 78 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index bafb1421f3b30..a88f09f6227f5 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1214,6 +1214,33 @@ intel_cleanup_plane_fb(struct drm_plane *plane, */ static struct iosys_map panic_map; =20 +/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is = easier) + * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32= x32 + * pixels for 32bits pixels. + */ +#define YTILE_WIDTH 32 +#define YTILE_HEIGHT 32 +#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4) + +static void intel_ytile_set_pixel(struct drm_scanout_buffer *sb, unsigned = int x, unsigned int y, + u32 color) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(sb->width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5); + offset +=3D swizzle * 4; + iosys_map_wr(&sb->map[0], offset, u32, color); +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1232,6 +1259,34 @@ static void intel_panic_flush(struct drm_plane *plan= e) iplane->disable_tiling(iplane); } =20 +static void (*intel_get_tiling_func(u64 fb_modifier))(struct drm_scanout_b= uffer *sb, unsigned int x, + unsigned int y, u32 color) +{ + switch (fb_modifier) { + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + return intel_ytile_set_pixel; + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Yf_TILED_CCS: + default: + /* Not supported yet */ + return NULL; + } +} + static int intel_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) { @@ -1254,9 +1309,13 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, ptr =3D intel_fbdev_get_vaddr(dev_priv->display.fbdev.fbdev); } else { /* Can't disable tiling if DPT is in use */ - if (intel_fb_uses_dpt(fb)) - return -EOPNOTSUPP; - + if (intel_fb_uses_dpt(fb)) { + if (fb->format->cpp[0] !=3D 4) + return -EOPNOTSUPP; + sb->set_pixel =3D intel_get_tiling_func(fb->modifier); + if (!sb->set_pixel) + return -EOPNOTSUPP; + } ptr =3D intel_bo_panic_map(obj); } =20 @@ -1271,7 +1330,10 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, sb->map[0] =3D panic_map; sb->width =3D fb->width; sb->height =3D fb->height; - sb->format =3D fb->format; + /* Use the generic linear format, because tiling, RC, CCS, CC + * will be disabled in disable_tiling() + */ + sb->format =3D drm_format_info(fb->format->format); sb->pitch[0] =3D fb->pitches[0]; =20 return 0; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index e2a54547a29d5..71e79b022c9ef 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2577,17 +2577,24 @@ static u8 skl_get_plane_caps(struct drm_i915_privat= e *i915, =20 static void skl_disable_tiling(struct intel_plane *plane) { - u32 plane_ctl; struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); struct drm_i915_private *dev_priv =3D to_i915(plane->base.dev); - u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + const struct drm_framebuffer *fb =3D state->hw.fb; + u32 plane_ctl; =20 plane_ctl =3D intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane->id)); - plane_ctl &=3D ~PLANE_CTL_TILED_MASK; =20 - intel_de_write_fw(dev_priv, PLANE_STRIDE(plane->pipe, plane->id), - PLANE_STRIDE_(stride)); + if (intel_fb_uses_dpt(fb)) { + /* if DPT is enabled, keep tiling, but disable compression */ + plane_ctl &=3D ~PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; + } else { + /* if DPT is not supported, disable tiling, and update stride */ + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; =20 + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + intel_de_write_fw(dev_priv, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + } intel_de_write_fw(dev_priv, PLANE_CTL(plane->pipe, plane->id), plane_ctl); =20 intel_de_write_fw(dev_priv, PLANE_SURF(plane->pipe, plane->id), --=20 2.47.1