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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2024 09:35:51.0972 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23933f46-d93a-4422-5631-08dd18fe0933 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8116 Content-Type: text/plain; charset="utf-8" 0x10 is the minimum sample period for IBS Fetch and 0x90 for IBS Op. Current IBS PMU driver uses 0x10 for both the PMUs, which is incorrect. Fix it by adding PMU specific minimum period values in struct perf_ibs. Also, bail out opening a 'sample period mode' event if the user requested sample period is less than PMU supported minimum value. For a 'freq mode' event, start calibrating sample period from PMU specific minimum period. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3e7ca1e2f25e..7b54b76d39f5 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -86,6 +86,7 @@ struct perf_ibs { u64 cnt_mask; u64 enable_mask; u64 valid_mask; + u16 min_period; u64 max_period; unsigned long offset_mask[1]; int offset_max; @@ -308,10 +309,14 @@ static int perf_ibs_init(struct perf_event *event) /* raw max_cnt may not be set */ return -EINVAL; =20 - /* Silently mask off lower nibble. IBS hw mandates it. */ - hwc->sample_period &=3D ~0x0FULL; - if (!hwc->sample_period) - hwc->sample_period =3D 0x10; + if (event->attr.freq) { + hwc->sample_period =3D perf_ibs->min_period; + } else { + /* Silently mask off lower nibble. IBS hw mandates it. */ + hwc->sample_period &=3D ~0x0FULL; + if (hwc->sample_period < perf_ibs->min_period) + return -EINVAL; + } } else { u64 period =3D 0; =20 @@ -329,10 +334,10 @@ static int perf_ibs_init(struct perf_event *event) config &=3D ~perf_ibs->cnt_mask; event->attr.sample_period =3D period; hwc->sample_period =3D period; - } =20 - if (!hwc->sample_period) - return -EINVAL; + if (hwc->sample_period < perf_ibs->min_period) + return -EINVAL; + } =20 /* * If we modify hwc->sample_period, we also need to update @@ -353,7 +358,8 @@ static int perf_ibs_set_period(struct perf_ibs *perf_ib= s, int overflow; =20 /* ignore lower 4 bits in min count: */ - overflow =3D perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, perio= d); + overflow =3D perf_event_set_period(hwc, perf_ibs->min_period, + perf_ibs->max_period, period); local64_set(&hwc->prev_count, 0); =20 return overflow; @@ -696,6 +702,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, .valid_mask =3D IBS_FETCH_VAL, + .min_period =3D 0x10, .max_period =3D IBS_FETCH_MAX_CNT << 4, .offset_mask =3D { MSR_AMD64_IBSFETCH_REG_MASK }, .offset_max =3D MSR_AMD64_IBSFETCH_REG_COUNT, @@ -720,6 +727,7 @@ static struct perf_ibs perf_ibs_op =3D { IBS_OP_CUR_CNT_RAND, .enable_mask =3D IBS_OP_ENABLE, .valid_mask =3D IBS_OP_VAL, + .min_period =3D 0x90, .max_period =3D IBS_OP_MAX_CNT << 4, .offset_mask =3D { MSR_AMD64_IBSOP_REG_MASK }, .offset_max =3D MSR_AMD64_IBSOP_REG_COUNT, --=20 2.43.0