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charset="utf-8" On i.MX8QM, PCIe link can't be re-established again in dw_pcie_resume_noirq(), if the LTSSM_EN bit is not cleared properly in dw_pcie_suspend_noirq(). Add dw_pcie_stop_link() into dw_pcie_suspend_noirq() to fix this issue and keep symmetric in suspend/resume function since there is dw_pcie_start_link() in dw_pcie_resume_noirq(). Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume functional= ity") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index f882b11fd7b94..f56cb7b9e6f99 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1001,6 +1001,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) return ret; } =20 + dw_pcie_stop_link(pci); if (pci->pp.ops->deinit) pci->pp.ops->deinit(&pci->pp); =20 --=20 2.37.1 From nobody Fri Dec 27 13:47:10 2024 Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2070.outbound.protection.outlook.com [40.107.104.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C40FA23099F; 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charset="utf-8" Before sending PME_TURN_OFF, don't test the LTSSM state. Since it's safe to send PME_TURN_OFF message regardless of whether the link is up or down. So, there would be no need to test the LTSSM state before sending PME_TURN_OFF message. Only print the message when ltssm_stat is not in DETECT and POLL. In the other words, there isn't an error message when no endpoint is connected at all. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- .../pci/controller/dwc/pcie-designware-host.c | 27 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index f56cb7b9e6f99..bdb9c1ad6cdd5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -973,7 +973,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) { u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; - int ret =3D 0; + int ret; =20 /* * If L1SS is supported, then do not put the link into L2 as some @@ -982,25 +982,32 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM= _L1) return 0; =20 - if (dw_pcie_get_ltssm(pci) <=3D DW_PCIE_LTSSM_DETECT_ACT) - return 0; - - if (pci->pp.ops->pme_turn_off) + if (pci->pp.ops->pme_turn_off) { pci->pp.ops->pme_turn_off(&pci->pp); - else + } else { ret =3D dw_pcie_pme_turn_off(pci); + if (ret) + return ret; + } =20 - if (ret) - return ret; - - ret =3D read_poll_timeout(dw_pcie_get_ltssm, val, val =3D=3D DW_PCIE_LTSS= M_L2_IDLE, + ret =3D read_poll_timeout(dw_pcie_get_ltssm, val, + val =3D=3D DW_PCIE_LTSSM_L2_IDLE || + val <=3D DW_PCIE_LTSSM_DETECT_WAIT, PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US, false, pci); if (ret) { + /* Only dump message when ltssm_stat isn't in DETECT and POLL */ dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); return ret; } =20 + /* + * Refer to r6.0, sec 5.3.3.2.1, software should wait at least + * 100ns after L2/L3 Ready before turning off refclock and + * main power. It's harmless too when no endpoint connected. + */ + udelay(1); + dw_pcie_stop_link(pci); if (pci->pp.ops->deinit) pci->pp.ops->deinit(&pci->pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 5c14ed2cb91ed..7efcb4af66da3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -330,6 +330,7 @@ enum dw_pcie_ltssm { /* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */ DW_PCIE_LTSSM_DETECT_QUIET =3D 0x0, DW_PCIE_LTSSM_DETECT_ACT =3D 0x1, + DW_PCIE_LTSSM_DETECT_WAIT =3D 0x6, DW_PCIE_LTSSM_L0 =3D 0x11, DW_PCIE_LTSSM_L2_IDLE =3D 0x15, =20 --=20 2.37.1