From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2CD50227576 for ; Tue, 10 Dec 2024 05:53:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810010; cv=none; b=uTWThW15u6TwsnUse5lbWVY6le7DcoACSgRWOAXoCbVGzYIy/ll2wSSsx2A7K6txEBmns9bk5a+RyzJt4n2zotRiFKe89+U7jYUb/Y0Qir+C1y1TASNmF4sdqZHjfwzQdKpv9nBMRRZjHBENje9l/m6CJmm5cIjLzzcVNR3x4qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810010; c=relaxed/simple; bh=MSbLU1/0OzuEZ7Pc//TooBI5NPs3zWHPJshr6l+p4kw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=irA2+4UsD0eJmR76jfHTZ+j4zJBaY+E0DAJTBv7cUUZnX+pbKPJnsTV7/r0diHyRiaauh5oMJ9h4p4nAShsA4amYYX54I8x3xfjagrlw3LFqAERQDBCRQPYOC6WOS/+90HgIYbZJUpLIZldeKKXyjAJSs0MANZQfQr3zoj6KmWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6AE8B113E; Mon, 9 Dec 2024 21:53:56 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1CC0B3F58B; Mon, 9 Dec 2024 21:53:23 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 01/46] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 Date: Tue, 10 Dec 2024 11:22:26 +0530 Message-Id: <20241210055311.780688-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR0_EL1.FGT and ID_AA64MMFR0_EL1.PARANGE register fields as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b081b54d6d22..a6cbe0dcd63b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1591,6 +1591,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1652,6 +1653,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg =20 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 70518228367 for ; Tue, 10 Dec 2024 05:53:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810015; cv=none; b=iMY14TYuGmez7BDEaQ/lowN3nUIiB333G5ziOr4JFuSTP8ShRdIbC9DQK3q7vVto4bt5xNfsKIHw6OgEqTyNbl7aAUTV+fc8O5bvbdp6War7DIhwQ2K4GUBtleafr4Q6D62x7dyjWIhgHL7jhrewJheIAlHwFmgecKGsUKoW6Ns= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810015; c=relaxed/simple; bh=78MzFxfAh+jQPiDYCa7bJ4b6F6mZ9hWEu/lCNwjiTco=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Uri2+0wdz+IWRep4MuMFkivvUn/ia2vazcc3yG0JTaVSWMMka8VGA9lucHHj0orc3g/NYounXwkZ9VWJHY7ZS/HInVZX4tF/2lMxcMBbKYQhsnfzKAw6jK8ufWYl6MP15Ce6eNyo9xVzv2Yal7xxFdJNWnRhL2yvI3Z+VDmFZBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDC33113E; Mon, 9 Dec 2024 21:54:00 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 08E103F58B; Mon, 9 Dec 2024 21:53:28 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 02/46] arm64/sysreg: Update register fields for ID_AA64MMFR4_EL1 Date: Tue, 10 Dec 2024 11:22:27 +0530 Message-Id: <20241210055311.780688-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR4_EL1 register as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a6cbe0dcd63b..b5bda7c94689 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1872,12 +1872,21 @@ EndEnum EndSysreg =20 Sysreg ID_AA64MMFR4_EL1 3 0 0 7 4 -Res0 63:40 +Res0 63:48 +UnsignedEnum 47:44 SRMASK + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 43:40 UnsignedEnum 39:36 E3DSE 0b0000 NI 0b0001 IMP EndEnum -Res0 35:28 +Res0 35:32 +UnsignedEnum 31:28 RMEGDI + 0b0000 NI + 0b0001 IMP +EndEnum SignedEnum 27:24 E2H0 0b0000 IMP 0b1110 NI_NV1 @@ -1886,6 +1895,7 @@ EndEnum UnsignedEnum 23:20 NV_frac 0b0000 NV_NV2 0b0001 NV2_ONLY + 0b0010 SOFTWARE EndEnum UnsignedEnum 19:16 FGWTE3 0b0000 NI @@ -1905,7 +1915,10 @@ SignedEnum 7:4 EIESB 0b0010 ToELx 0b1111 ANY EndEnum -Res0 3:0 +UnsignedEnum 3:0 PoPS + 0b0000 NI + 0b0001 IMP +EndEnum EndSysreg =20 Sysreg SCTLR_EL1 3 0 1 0 0 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 168F3228383 for ; Tue, 10 Dec 2024 05:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810019; cv=none; b=TuTjHlQGD/KET6VUcSxk+nlNDtKn6MWDBW4zs+rydMCdol37CZ6SLS0YYqBDCpG1btLnl8ImqiR0xS3PuNKghETJU9aSX6ukTWk1o4OXXCMPRu8vI46xVNyhOqvw5GuisNjNkS3CV3UKPWdbVak9JETjVQhODvEE2SiX3yylyu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810019; c=relaxed/simple; bh=GkoVkkoNSjPJIC7i2Jqd3ADUfKdnchBUnmhHwRXgQk0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KLxND0sND5OJDpTpowcza33gZKEWJX0fITlkYKM/epryY5hdztpDoVpapzWmgQ2yfqrBQyDwpooSCHq+dc0+j3IVGK+lTve/VKixkCgUhLTSfZGlLl3s5m5oyb4WoAlxFQR7TA94oUQ4bbsxHdmD9GwqIPkWj/i+V4e6/AbIcZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84A7F113E; Mon, 9 Dec 2024 21:54:05 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6BD013F58B; Mon, 9 Dec 2024 21:53:33 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 03/46] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1 Date: Tue, 10 Dec 2024 11:22:28 +0530 Message-Id: <20241210055311.780688-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64PFR0_EL1.RAS and ID_AA64PFR0_EL1.RME register fields as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b5bda7c94689..59351931d907 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -873,6 +873,8 @@ EndEnum UnsignedEnum 55:52 RME 0b0000 NI 0b0001 IMP + 0b0010 GPC2 + 0b0011 GPC3 EndEnum UnsignedEnum 51:48 DIT 0b0000 NI @@ -899,6 +901,7 @@ UnsignedEnum 31:28 RAS 0b0000 NI 0b0001 IMP 0b0010 V1P1 + 0b0011 V2 EndEnum UnsignedEnum 27:24 GIC 0b0000 NI --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B667322757D for ; Tue, 10 Dec 2024 05:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810024; cv=none; b=FWMgCKfz5V6L5lIGKB4E0I323Xby3C1WBkUMobLVRyhIK38/3rEiGaxz0oWrhGSvNSqjpwRoN1a0tUcDPVEJXM9fG5Y6wSGsB9eo26LdDl1e1eR7+K4BUORMkNsUDNh6UshtB//DlXgZLvuPRln5zacwvNKQVeKppItLzZqoKec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810024; c=relaxed/simple; bh=ynHFhYOJaRn+pONLKmb/Lz4gw/YfaE3oLjKeTNMBY90=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dVEgWDrFjAvxUXICz1plgQ3/O0GjFsBA5uwZCN+NyHom8Zo2Wo4z/Mg057zJNQ1mpDE38CkJqVpzvpsoH3/bwyt/GtKYewF9O7yDf4EoE1Fv27uR0foJ1djC7Y7MybS50X3MOd1hgGGTFNL9+wAMCM7XcgUzx7vLrX+9LaZv5Hw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 400A0113E; Mon, 9 Dec 2024 21:54:10 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C1F93F58B; Mon, 9 Dec 2024 21:53:37 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 04/46] arm64/sysreg: Update register fields for TRBIDR_EL1 Date: Tue, 10 Dec 2024 11:22:29 +0530 Message-Id: <20241210055311.780688-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for TRBIDR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 59351931d907..10b1a0998d99 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3295,13 +3295,24 @@ Field 31:0 TRG EndSysreg =20 Sysreg TRBIDR_EL1 3 0 9 11 7 -Res0 63:12 +Res0 63:48 +Field 47:32 MaxBuffSize +Res0 31:16 +UnsignedEnum 15:12 MPAM + 0b0000 NI + 0b0001 PMG + 0b0010 IMP +EndEnum Enum 11:8 EA 0b0000 NON_DESC 0b0001 IGNORE 0b0010 SERROR EndEnum -Res0 7:6 +UnsignedEnum 7:6 AddrMode + 0b00 VIRT_PHYS + 0b01 VIRT_ONLY + 0b10 PHYS_ONLY +EndEnum Field 5 F Field 4 P Field 3:0 Align --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9536322758E for ; Tue, 10 Dec 2024 05:53:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810029; cv=none; b=A4y1iEhynchFVvuw9H20cFSWMIkUH49kkBbh2Gl4YqwM3+FZHcmLW9rNql78kSGsTIgmGFYf/WvS/YhZOD83kA86demp92gnHOtsVeDR0Dla1HrmkX0UnF3tWiOxGf/u1CCnPB6t8yxjI83hz/0RbNIDueDSxiAW1cJTvMgBrec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810029; c=relaxed/simple; bh=d54Km2spWR3Xq5kdhbrImrDhEYz1w1vSsqR0AxqWqNA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jGei8dS9Id5Cb9+O54d7wi02UWoCt/DR+XHgG8/7g5uxKfNal4uBnkg+u2xSr8UQGGy010F4h4Y7GU7U/dp+salW63DMgkJrpUycvD4NTgZACfj8tBs6kiJdpjVfwWUxBxnme287qqVldleeTBGdUjFyczgE48GGhGgS42mQHQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 445C5168F; Mon, 9 Dec 2024 21:54:15 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D219F3F58B; Mon, 9 Dec 2024 21:53:42 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 05/46] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Date: Tue, 10 Dec 2024 11:22:30 +0530 Message-Id: <20241210055311.780688-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 10b1a0998d99..a56f7384d0db 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2562,6 +2562,35 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 33E34226197 for ; Tue, 10 Dec 2024 05:53:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810034; cv=none; b=gHqusTMPoRgPuHsZdb1DoIyu/aLrEfKQg/AwI+vstcAfoSJeO4FIV7HHIY61koc028k7y9d8r3SPPXvebteDX/VaEz+dOLtuGzLgX3ZX6utyc1rHK4xtqr4ER+OMnRRXhwT3M93wP+5fuXdb7MuuhqtgkUqWRUV/uXLC6jhh+Ek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810034; c=relaxed/simple; bh=iPevydl4HWgrRdujEVm+wbQl3dVXjT+gryYCBhAsUwM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fCltFXDtVGuJz9hAW4I8DD7vltBcG670Lo0UzV844fTE7AyASLn1Q27EQ++UqSQPkJZEz3QWBzKCOo+W1SeDyM7mZ4GDYMiKnxEHd44u93Ah6wJM5m+8wE9pcRGP0FrotL9w6z55hvspz5bbynwId6HLdymrWv7NFt6TsuI4A/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A66FE113E; Mon, 9 Dec 2024 21:54:19 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D5B043F58B; Mon, 9 Dec 2024 21:53:47 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 06/46] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Date: Tue, 10 Dec 2024 11:22:31 +0530 Message-Id: <20241210055311.780688-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a56f7384d0db..1a7d8c03f844 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2591,6 +2591,34 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2C0D522758E for ; Tue, 10 Dec 2024 05:53:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810038; cv=none; b=QxeMW4P65HRK+laoAftmeXUxWK4jEqMFjw79FhZkR2jw9J9O91RKekpiujb0AQxFn3Shy29x8FtD3gx+zsu52mZkO0eU2L/ot20aFqkOopYD979JRujdRtdMBHS5IXob8cm/isaJavgzvvC2iReRjL6nevqWAFiU7C50SE+o10k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810038; c=relaxed/simple; bh=hPLz32OvtO/KijLkZtfQh5UzC+VMjoUGx3K3poz15ww=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=laj8jkikuo/KoPcs73J1Cyy/x/qNnNi575LWRT2Pjr7GklhO/APFrmcF5yOh16iNK3RR3SQ2xigmMkf3Eh53JT1hYNK+Av1MhBm9bJPAEHLWY/FMTRMT5AtIUAENJhLaGu9hZrQGgKFNQ+A6ziw+8sIewMWlVJnAanFU5aOrSNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A688D113E; Mon, 9 Dec 2024 21:54:24 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5CF593F58B; Mon, 9 Dec 2024 21:53:51 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 07/46] arm64/sysreg: Add register fields for HFGITR2_EL2 Date: Tue, 10 Dec 2024 11:22:32 +0530 Message-Id: <20241210055311.780688-8-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGITR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 1a7d8c03f844..9d339f735648 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2791,6 +2791,12 @@ Field 1 AMEVCNTR00_EL0 Field 0 AMCNTEN0 EndSysreg =20 +Sysreg HFGITR2_EL2 3 4 3 1 7 +Res0 63:2 +Field 1 nDCCIVAPS +Field 0 TSBCSYNC +EndSysreg + Sysreg ZCR_EL2 3 4 1 2 0 Fields ZCR_ELx EndSysreg --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AC948228368 for ; Tue, 10 Dec 2024 05:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810043; cv=none; b=onNxcaqPfglV7Xxz7CkM+3YuJ5wd+IfRiDDA5qIBiOJD5ox/QqD6wG9BktWyWH7+/KXJHsdeWzNBTE5YnD3YNWUiKR4UBhL+RV0W8Bb/7FnLII8xuzeg+4iepJNHYs4uTQTXsubjRvEL9H3hiOB+Q//GhZmpr4PURYtV62L1/Mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810043; c=relaxed/simple; bh=p0ouVU6R/JVBtQ1G6p/R0PjSR3058k0GObRcpH46BZE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aa8eZAOGbPz8dJxDn1B5cyAjKpbuFBKJassiEoxQmHf1pNcoL196+Mlgphb80mjlhzMVeMkfKc8jkfFS1ZEfApIVwawkd688sBgBnM87mhRqb/JmGTbqrCFjWPAbWvY3ujXvXpSDlIBDz7Xul3hxr6HnDTfMfmrs3itQRynG2bo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 48588113E; Mon, 9 Dec 2024 21:54:29 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2BCAA3F58B; Mon, 9 Dec 2024 21:53:56 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 08/46] arm64/sysreg: Add register fields for HFGRTR2_EL2 Date: Tue, 10 Dec 2024 11:22:33 +0530 Message-Id: <20241210055311.780688-9-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGRTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9d339f735648..9513ae05dc93 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2619,6 +2619,25 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HFGRTR2_EL2 3 4 3 1 2 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Field 1 nERXGSR_EL1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B0DA1D6DD1 for ; Tue, 10 Dec 2024 05:54:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810047; cv=none; b=Jd/GG+Hz5mwCimzvK/cuKMq1t7QgcrNiREKl97A6LrVWRPnTpSIxJvJyjRWLOu4rwzNs945V9OtstasFV22GsHazYzpjuvGHmczhVimAeUEuu1pfdQ4IZCzUHkPy8k7JkiSgiTsi7zuJBZ1dXSfaJ3X5QZ0cHtXLfK7DsS2RuHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810047; c=relaxed/simple; bh=RDLCQUMVhAh14mOgAunk8JK5tcWOHlOXVPkkMiA9+1c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kr+HT08H9khSNTp8nAZn13tohWujcj/XgtbkiquqYcL11Jk/O2NsNG1fMfbAANMOzWzEfOBmWaJUXpppyZ/svtwIL9koiEMHqvmzVYh9JDEP0XFUCj2mVndtHClLo/f45AsAg1ImFEP6xX09gyn/X6JrGyT77myMp8pk73pxii4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB3AE113E; Mon, 9 Dec 2024 21:54:33 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D08AC3F58B; Mon, 9 Dec 2024 21:54:01 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 09/46] arm64/sysreg: Add register fields for HFGWTR2_EL2 Date: Tue, 10 Dec 2024 11:22:34 +0530 Message-Id: <20241210055311.780688-10-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGWTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9513ae05dc93..30a0d3ee71a7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2638,6 +2638,25 @@ Field 1 nERXGSR_EL1 Field 0 nPFAR_EL1 EndSysreg =20 +Sysreg HFGWTR2_EL2 3 4 3 1 3 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Res0 1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DA1161D6DD1 for ; Tue, 10 Dec 2024 05:54:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810052; cv=none; b=OSSwSUDo9PUljtT/GrwB2WLmafgg9ucMjR/ZZqYh/VMYj/Bk812s4RqtaWOOyrvAdxpkA4BZOJbn8UZRexXsJ32BwJLiE0J5AipgGrGROs15Pufu1MR5BX5fBupfq35TcLJJv7CT7JxBdf9AXzjrGiT+dd1o1odis75BGcfRmcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810052; c=relaxed/simple; bh=3tuuAZr/udtO/FbCo+lGDid2Q9W0nfrVGqrHIgTRD4I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PXuKTrFHruYaKKpxlVnU9UlHbAQluBIM8buFzUA1VyZXWkvBHFaYza48/4fHCIDrsOUsPQ6VGKeoeSCpPAJ/dPVVDfJFdLytkZimvOlacIgq2V8LrJqPQNCh7/oigAuNSsaf/d/QzmK6hKyCNi6YmYlib9tdRSnlpNi1GlU+98Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 91DEB1570; Mon, 9 Dec 2024 21:54:38 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 80F013F58B; Mon, 9 Dec 2024 21:54:06 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 10/46] arm64/sysreg: Add register fields for MDSELR_EL1 Date: Tue, 10 Dec 2024 11:22:35 +0530 Message-Id: <20241210055311.780688-11-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSELR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 30a0d3ee71a7..be0091060350 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -93,6 +93,17 @@ Res0 63:32 Field 31:0 DTRTX EndSysreg =20 +Sysreg MDSELR_EL1 2 0 0 4 2 +Res0 63:6 +Enum 5:4 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +Res0 3:0 +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DC59522837E for ; Tue, 10 Dec 2024 05:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810058; cv=none; b=JlIBNsds/oHe8iqJc1izHmH/kakmkPGOI4RDZRsoHJFMHwlqs5KjFULmBOsfdZ+VCrX1JBV4yVUvB+onc3bY1kf8hJenhhfWGJyVIMR34gDoYNimUoBljQ/C0lr3qCWx4vISiKHuoT65ki7aZLPOqtLujyjpz4c0xR0WiNz/QF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810058; c=relaxed/simple; bh=u74eDUz9U7zGmB9ZLdR5o7RPuWyhMxFR47/2JvJEo30=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=stIbmq0UpYqKu1b8TBfEMB+GehjUD0M8L71Pa/R46bXc+kp1hrqfPejtv0DyJftCuzBAgMY8HJTa+KbSzAp7tfDPaKjzkfTSix8HlxtvVlOGMrj0vDz0aminRtSMqtCuqKMTKNvuUVrABRnuJJ5c0Li724t+iCvAlIlEhn7uZOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5669B113E; Mon, 9 Dec 2024 21:54:43 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1FBBE3F58B; Mon, 9 Dec 2024 21:54:10 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 11/46] arm64/sysreg: Add register fields for PMSIDR_EL1 Date: Tue, 10 Dec 2024 11:22:36 +0530 Message-Id: <20241210055311.780688-12-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSIDR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index be0091060350..a5e31e4c4474 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2172,7 +2172,16 @@ Field 15:0 MINLAT EndSysreg =20 Sysreg PMSIDR_EL1 3 0 9 9 7 -Res0 63:25 +Res0 63:33 +Field 32 SME +UnsignedEnum 31:28 ALTCLK + 0b0000 NI + 0b0001 IMP + 0b1111 IMP_DEF +EndEnum +Field 27 FPF +Field 26 EFT +Field 25 CRR Field 24 PBT Field 23:20 FORMAT Enum 19:16 COUNTSIZE @@ -2190,7 +2199,10 @@ Enum 11:8 INTERVAL 0b0111 3072 0b1000 4096 EndEnum -Res0 7 +UnsignedEnum 7 FDS + 0b0 NI + 0b1 IMP +EndEnum Field 6 FnE Field 5 ERND Field 4 LDS --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D580B227592 for ; Tue, 10 Dec 2024 05:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810063; cv=none; b=npo1hsoON2g7T2nXY7+WJtsadSNO22yISbFgzTZPbFXwdjW3od6gm3lHzFl5tT3udniJgZIt32059Ng9qr4TUGOXILoIkg92S6I38ATv8HpIChBByU763+KKDno1wOWWwewaEXp5DLlgmeaDo1skulhBKsCipZh+BwYHy1XtGE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810063; c=relaxed/simple; bh=1RlLYctFbW5Kwc1/mtCPA1pFyYkzRM/kpPE2QU96Saw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jHECFyBAM/OQ4ybd2XRRv9r3D0Mck0WM72bw3xawLHsgLtHtHQSlSsa5b/pj8F76TvyZlh6Qp+jVZkcPGLT+EEKDsxrEDp4Pxfk2Zhqfv/2QlCkptfnxHOfSns5QJ0ZR08d1ZsbHnTJWILt50lbKYDm3wuC++PDoSkvMcu5vbpA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 50C4D113E; Mon, 9 Dec 2024 21:54:48 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EB6373F58B; Mon, 9 Dec 2024 21:54:15 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 12/46] arm64/sysreg: Add register fields for TRBMPAM_EL1 Date: Tue, 10 Dec 2024 11:22:37 +0530 Message-Id: <20241210055311.780688-13-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for TRBMPAM_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a5e31e4c4474..78564b24b187 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3413,6 +3413,19 @@ EndEnum Field 7:0 Attr EndSysreg =20 +Sysreg TRBMPAM_EL1 3 0 9 11 5 +Res0 63:27 +Field 26 EN +UnsignedEnum 25:24 MPAM_SP + 0b00 SECURE_PARTID + 0b01 NON_SECURE_PARTID + 0b10 ROOT_PARTID + 0b11 REALM_PARTID +EndEnum +Field 23:16 PMG +Field 15:0 PARTID +EndSysreg + Sysreg TRBTRG_EL1 3 0 9 11 6 Res0 63:32 Field 31:0 TRG --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A65F227592 for ; Tue, 10 Dec 2024 05:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810067; cv=none; b=eRZuDJogdl7psnTgMhLzN6qvCTkhP4a1taOmyz4vMbT8D63KdmSldPrgxk/e9noiKVr4q//xOvv8HgTqKZtlDhUOghp/CyVlBWwz+TyUHVhWMKe1g3ZDW3Mc9Adg5zY7wXes3uCnj2Lk3jtcT918nhaQRIB+gVY1NeGYDmpn2F0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810067; c=relaxed/simple; bh=YnfXw8givv92N/Wmkzh0NUn61JJPufjGxBsMBPZ1kGo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nBOrPQMwDvu8wq0xlHHKjHEtrW+ORhU9si561PCsG7quHR3IpO6dgPrNhbv5O+8h/NtF2U0s/SkumMqSWvN+i12pptfTkW8eFqei/rkSqRZYGjIN+ygWMXh9YK797cvf5mRzmXyMXZKqWfGCmOCKS/mkjLSwOgclj4q0AKP9tUY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9DD3113E; Mon, 9 Dec 2024 21:54:52 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B346F3F58B; Mon, 9 Dec 2024 21:54:20 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 13/46] arm64/sysreg: Add register fields for PMSDSFR_EL1 Date: Tue, 10 Dec 2024 11:22:38 +0530 Message-Id: <20241210055311.780688-14-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSDSFR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 78564b24b187..fcb4ecd85d35 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2245,6 +2245,73 @@ Field 16 COLL Field 15:0 MSS EndSysreg =20 +Sysreg PMSDSFR_EL1 3 0 9 10 4 +Field 63 S63 +Field 62 S62 +Field 61 S61 +Field 60 S60 +Field 59 S59 +Field 58 S58 +Field 57 S57 +Field 56 S56 +Field 55 S55 +Field 54 S54 +Field 53 S53 +Field 52 S52 +Field 51 S51 +Field 50 S50 +Field 49 S49 +Field 48 S48 +Field 47 S47 +Field 46 S46 +Field 45 S45 +Field 44 S44 +Field 43 S43 +Field 42 S42 +Field 41 S41 +Field 40 S40 +Field 39 S39 +Field 38 S38 +Field 37 S37 +Field 36 S36 +Field 35 S35 +Field 34 S34 +Field 33 S33 +Field 32 S32 +Field 31 S31 +Field 30 S30 +Field 29 S29 +Field 28 S28 +Field 27 S27 +Field 26 S26 +Field 25 S25 +Field 24 S24 +Field 23 S23 +Field 22 S22 +Field 21 S21 +Field 20 S20 +Field 19 S19 +Field 18 S18 +Field 17 S17 +Field 16 S16 +Field 15 S15 +Field 14 S14 +Field 13 S13 +Field 12 S12 +Field 11 S11 +Field 10 S10 +Field 9 S9 +Field 8 S8 +Field 7 S7 +Field 6 S6 +Field 5 S5 +Field 4 S4 +Field 3 S3 +Field 2 S2 +Field 1 S1 +Field 0 S0 +EndSysreg + Sysreg PMBIDR_EL1 3 0 9 10 7 Res0 63:12 Enum 11:8 EA --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D1760227592 for ; Tue, 10 Dec 2024 05:54:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810071; cv=none; b=EJ7xRejqKBe9tAXynkZ+6aRsMIvdA9suaec6VyMYF/tDEhDmo/tCANbShMxsZ2WEpWVKR2bL+9Ndxamgltk+DcXr8BO0192HASkfdLVNTs+K/c6NCSrDPgTByIVf0z2gG1RrY9p7MD+ISF+L01MfOqJUucjcDZ3NE5J3lYmiqWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810071; c=relaxed/simple; bh=j1ybNRUTMBxdwGJO8XFVrc5i9puGNqFHgg0H+YKyb/w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ECHypJKDIc/FkHosoeIL0GpBaOrDKXZrK+5JPtmyWfGoRbRV/OTAmYtbXFkFVI+5MgjGqyeySmmxRW6ZqBt+Djwn3/WnPw4DP5jCjHo6Sap86R+ehRHWNVOZEy8pL4HG4eNB8gzra4Es347C3byuMdrvbHOwZRavyXD52CPKZ6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8DADE113E; Mon, 9 Dec 2024 21:54:57 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 563473F58B; Mon, 9 Dec 2024 21:54:25 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 14/46] arm64/sysreg: Add register fields for SPMDEVAFF_EL1 Date: Tue, 10 Dec 2024 11:22:39 +0530 Message-Id: <20241210055311.780688-15-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMDEVAFF_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index fcb4ecd85d35..18b814ff2c41 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,18 @@ Res0 63:1 Field 0 OSLK EndSysreg =20 +Sysreg SPMDEVAFF_EL1 2 0 9 13 6 +Res0 63:40 +Field 39:32 Aff3 +Field 31 F0V +Field 30 U +Res0 29:25 +Field 24 MT +Field 23:16 Aff2 +Field 15:8 Aff1 +Field 7:0 Aff0 +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 48FD8228399 for ; Tue, 10 Dec 2024 05:54:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810075; cv=none; b=K2fsxlVy1G4Ds0d1/5WfWleXu7qBejv6ubYsuxUYQfVcQFPDEX/WJ8sDVRXQsIJ1k2fFPuDfuzb978BND9w5LMsVVr8YogubtvJk2gqh/7ztQ/IJSCvDCxUEDCMCfgHO/jfg+sV1Q+KuvVV6NeZ/LY+kReQ07qtuyQd0zKYyg6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810075; c=relaxed/simple; bh=CkWuJ6ySX6r4bux7eNmSMQJssrIudgD9DBeGeA6Gu8o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jw8F8U3IDMUmrpc57cPLfx53XAUVI8ko9yS34c0YF+3uhEZm72dbB53Z3dJ87bGwdwAFM4ZNxyX5+D50xyM/JTcFLnjrfwNKoOHSSMvwAki3vShzZlchA2B9JJOX16H2KRvrIQ1v4SF9UtUOzqRaqz+PhUPxqZrMmOIigb1WK6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 02D54113E; Mon, 9 Dec 2024 21:55:02 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 28CC23F58B; Mon, 9 Dec 2024 21:54:29 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 15/46] arm64/sysreg: Add register fields for PFAR_EL1 Date: Tue, 10 Dec 2024 11:22:40 +0530 Message-Id: <20241210055311.780688-16-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PFAR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 18b814ff2c41..e33edb41721a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3533,3 +3533,10 @@ Field 5 F Field 4 P Field 3:0 Align EndSysreg + +Sysreg PFAR_EL1 3 0 6 0 5 +Field 63 NS +Field 62 NSE +Res0 61:56 +Field 55:0 PA +EndSysreg --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CD86822756D for ; Tue, 10 Dec 2024 05:54:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810080; cv=none; b=YtpDHwdoC5TNslNxRH7xT/8rXdje04oNnrsjM/USEYcAP69EeBJRednKXA3qrGDqGqfH9ASY0dIJHtn3P0XISFHZ6ezhbjB+nrF1qhLgcqLRULTdjWGcHBLXWqZ/iVQ7ck8um/g6pecVGjyxgZKOsZzzSiP4RK0f45WzokMZKLA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810080; c=relaxed/simple; bh=056v++sdxvI1lluKQYqwfbNLB95zop5UKVyPmUVpuMU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qFanhVk/bjHwD9DSIod3YzSTykkvqINf+wsc9WWvsBK4uwm9nIQHtQ1d7sKHk/5c8JyhiEr57Oer1Lj2j7ZQSrBmBcZ5euaCt49NlcNyy1yIa7sT6/obGrIYew2DkUYtoPaavzzyS14v1ix39szzVlqLljIesepZfcl0gv7k6CM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B531113E; Mon, 9 Dec 2024 21:55:06 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8BF973F58B; Mon, 9 Dec 2024 21:54:34 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 16/46] arm64/sysreg: Add register fields for PMIAR_EL1 Date: Tue, 10 Dec 2024 11:22:41 +0530 Message-Id: <20241210055311.780688-17-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMIAR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e33edb41721a..ff09da6c0b1e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2349,6 +2349,10 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMIAR_EL1 3 0 9 14 7 +Field 63:0 ADDRESS +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6CC0F22758D for ; Tue, 10 Dec 2024 05:54:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810084; cv=none; b=YBxdoNw61bZUg/8AGosQiEwxHkItKNrCLooqFpG1FPwjvU0vXqsmxYHFXfeCWyH/Ak4uvhhbbUS7E5TpXwAD8tIfoWfPadC8fMgCQ3BSBUShnAqE6ow/ACwWooVKUaYhjlY1f2nkEgSdh5isJYKL1iAVrMPvWtPBHTKxaCD2e9I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810084; c=relaxed/simple; bh=M4+ncPcwaTkqjCH19NoLaN/p8b3plUQAQ1c52P9IaMw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kdSyjkrWNUGdBl7Vm8IwsPUJORrbjQnyxqe3HvbOq3fNKhM2O/QCg6+CL/iKB15oJtaKUKEaScJsk+YOl58y237ajxCJ5LNqNFZBFvnI6iwfpqQzJhbfjmAKCdDTkRDcQ+611GbtvgQRg5taefylwww9svSvGd/On3ADmKBgvfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A550113E; Mon, 9 Dec 2024 21:55:11 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 126B03F58B; Mon, 9 Dec 2024 21:54:38 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 17/46] arm64/sysreg: Add register fields for PMECR_EL1 Date: Tue, 10 Dec 2024 11:22:42 +0530 Message-Id: <20241210055311.780688-18-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMECR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Eric Auger --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ff09da6c0b1e..214ad6da1dff 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2349,6 +2349,21 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMECR_EL1 3 0 9 14 5 +Res0 63:5 +UnsignedEnum 4:3 SSE + 0b00 DISABLED + 0b10 ENABLED_PROHIBITED + 0b11 ENABLED_ALLOWED +EndEnum +Field 2 KPME +UnsignedEnum 1:0 PMEE + 0b00 PMUIRQ_E_PMU_D + 0b10 PMUIRQ_D_PMU_D + 0b11 PMUIRQ_D_PMU_E +EndEnum +EndSysreg + Sysreg PMIAR_EL1 3 0 9 14 7 Field 63:0 ADDRESS EndSysreg --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 61CF9227BBA for ; Tue, 10 Dec 2024 05:54:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810089; cv=none; b=JE4GDgw3RWbr9xwjaRyd+utNOGwG0IFDtGsEBOoQrLrrsVQPJqMM0FNttt74aJ3Az1VYGBvEJQSpgNoc4FT4HGBRNyqlHYnMoOlCTz/qKD43FhylME4v12hIwPI129SOe/Q86YqlQ8oeK2N0eBVaSFGzQRhTIhOfILwVcjuYq3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810089; c=relaxed/simple; bh=0BHcnjE7VF47kw7PHL2Jk0TCllqkDuGxHwUZIk9mJqU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nex6EfzpMRpkSn2udaRlcpxBj5agfwlNn4wbaf58QSMVymoRwgfntxDPDOYkvA2uFYzPh2b8fH7BHX0asa9Oz0Od00TjVlHi0IBDb4KNZcIqMiaXNknUy5K88743GBQoy3TFz904CyKnBFIqK3dpQtBiIaVAkOM13CvktqD7JaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C8D6113E; Mon, 9 Dec 2024 21:55:16 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A6A113F58B; Mon, 9 Dec 2024 21:54:43 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 18/46] arm64/sysreg: Add register fields for PMUACR_EL1 Date: Tue, 10 Dec 2024 11:22:43 +0530 Message-Id: <20241210055311.780688-19-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMUACR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 214ad6da1dff..462adb8031ca 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2349,6 +2349,43 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMUACR_EL1 3 0 9 14 4 +Res0 63:33 +Field 32 FM +Field 31 C +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg PMECR_EL1 3 0 9 14 5 Res0 63:5 UnsignedEnum 4:3 SSE --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 57566227B9E for ; Tue, 10 Dec 2024 05:55:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810104; cv=none; b=Rqev7boeFEiu2N27Dis2wBffRDuU+qk99kxdPO5qpA4o0k+jx18W5HOL+nPg4tkc+h/dPkjt/1GZmZqDGc3rtFZYSKf4Cee5ajcwxuyarhPdNlWycyC+uC8hPdW8MXqryQoWGdfmmYZr2X3usB0ph7ysg6ll9+GCIUIJsK0uYXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810104; c=relaxed/simple; bh=m3r2PO9cMWyQ9T7yOEAXCcSKJ8L7QGI0YXi/iqus1yU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AQmpNG5562PcTXkdMZxw/Xb0vHMYScZLlLdkSyFIKRjIcqalXEh12ZcgbO4cyeJvrxqGK7+oOseNPGhhg7Uz5wXSngTISy6yQe+KoqtuZrlFXyn2k3XcXLRPKD+UDT5OPwJRKsROmNBNdWsmx0T2sedQbdips+rjhGldM7e1OOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1386A113E; Mon, 9 Dec 2024 21:55:29 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AF3303F58B; Mon, 9 Dec 2024 21:54:48 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 19/46] arm64/sysreg: Add register fields for PMCCNTSVR_EL1 Date: Tue, 10 Dec 2024 11:22:44 +0530 Message-Id: <20241210055311.780688-20-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMCCNTSVR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 462adb8031ca..00d0015d7df4 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -126,6 +126,10 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg PMCCNTSVR_EL1 2 0 14 11 7 +Field 63:0 CCNT +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6A1EC227578 for ; Tue, 10 Dec 2024 05:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810115; cv=none; b=gGLRgugOIK5AJNzpQ6f+mTUft+mWVqhNUxNZbRiUgEAkmxxIf4dynZLmfBRwYJ2Q9dMc/RqBc8x6J167ZJxBDIWIufny2Ua1G26vV6NNq1wIz4Nc7cJ8Y9Jb7ToFEyo8ip5wJ8IFuw4yrllH8iH4gPMbHz1KTj/qbGho+MtktXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810115; c=relaxed/simple; bh=xDvYe+54EMF2B2Y2JXi299olf8ukZjk3XFWVyAaTHQI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nRfEijJLURCMQHacrWmwF/BDJdLS2jtaDeWHPd3bySJ3pmJ/b4xg1Vs5gtVJAkXPsScyHpLaS1FBJWi1ZGZeipSrqTOCSBej8YUO9kocYR7FRdLJWuzR1g7G+rqqRbPZgoaeKYYoZTHvp7ENOMisYm/Ot6U1T/K3SNVg1+36MyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24B63113E; Mon, 9 Dec 2024 21:55:42 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AA6903F58B; Mon, 9 Dec 2024 21:55:02 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 20/46] arm64/sysreg: Add register fields for SPMSCR_EL1 Date: Tue, 10 Dec 2024 11:22:45 +0530 Message-Id: <20241210055311.780688-21-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMSCR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 00d0015d7df4..22d2ba231059 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -130,6 +130,15 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg =20 +Sysreg SPMSCR_EL1 2 7 9 14 7 +Field 63:32 IMP_DEF +Field 31 RAO +Res0 30:5 +Field 4 NAO +Res0 3:1 +Field 0 SO +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5968C22619B for ; Tue, 10 Dec 2024 05:55:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810122; cv=none; b=Se89xkSeqYeo8Eklm06E0SuYAFVlLm6eK0Lgex9HPYYbWW9vAv/G4K8uU32VktfXOMjLWiSizjuGape6zpuf0fw76ulCBE1Q2ukEl7v368fn0DFX6DHgk7zbcGsWFAXePLs6RcFzvqed+PHfG8je+pK9V5ruObpdR1AbMwuJWgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810122; c=relaxed/simple; bh=4V8AiB5qbO666DVHri+1axeGcTw5XaiQ0D2S/tTvk50=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZKWYzcaaHrR2DeV5nJCQXPRQ80/GkW//QzgYqfp5jwaHEsVTZ9GBlBdA9AkkqSe1MzUm+l9V8mN8D+ptb+umJkquXbaByU1l4h2Y32w69iJfe82L37+ig2qGFcYXTE/oZhMQv3g8J/3OS4w3SU12CEbx8V88dszIBJ9mnO/Md/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 173BB113E; Mon, 9 Dec 2024 21:55:49 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A2FF43F58B; Mon, 9 Dec 2024 21:55:14 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 21/46] arm64/sysreg: Add register fields for SPMACCESSR_EL1 Date: Tue, 10 Dec 2024 11:22:46 +0530 Message-Id: <20241210055311.780688-22-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMACCESSR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 22d2ba231059..ff833f6f7f6d 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,41 @@ Res0 63:1 Field 0 OSLK EndSysreg =20 +Sysreg SPMACCESSR_EL1 2 0 9 13 3 +Field 63:62 P31 +Field 61:60 P30 +Field 59:58 P29 +Field 57:56 P28 +Field 55:54 P27 +Field 53:52 P26 +Field 51:50 P25 +Field 49:48 P24 +Field 47:46 P23 +Field 45:44 P22 +Field 43:42 P21 +Field 41:40 P20 +Field 39:38 P19 +Field 37:36 P18 +Field 35:34 P17 +Field 33:32 P16 +Field 31:30 P15 +Field 29:28 P14 +Field 27:26 P13 +Field 25:24 P12 +Field 23:22 P11 +Field 21:20 P10 +Field 19:18 P9 +Field 17:16 P8 +Field 15:14 P7 +Field 13:12 P6 +Field 11:10 P5 +Field 9:8 P4 +Field 7:6 P3 +Field 5:4 P2 +Field 3:2 P1 +Field 1:0 P0 +EndSysreg + Sysreg SPMDEVAFF_EL1 2 0 9 13 6 Res0 63:40 Field 39:32 Aff3 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9C09722A1E8 for ; Tue, 10 Dec 2024 05:55:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810127; cv=none; b=d0ehWf2bilpalbtCoBfRwyfGh8Bgu5FTfHJdT8I+aH8gDUfPTW5zgWiRx9CIemPEUp85HIa4fiMbf98pADRC+XcVQlNpB9lA8R7k92UFzjCUKbA8xSjOVzf8Bb6X48f4IFLEwOvoFSAmTS/rGCFPay53BeWoqYkWU4n2RXbJqyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810127; c=relaxed/simple; bh=ct46qktxCS0PmlmR0EXxV9Ecqp/uPcDY+/UUEO564Vc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DG5Ts9bC3kVjDS5RX/hXUQjTK3i4LgSwAuxFdi/On+d4cT6VmmkX4sf83eU6MmVUMD9NgOgqx5neUuPs9nWpsHiwPlsAAJ++u8zcVxXT5/5OHthPR+YJu/u0ALKkTAcZHdGPouik7FPM7HO89Vi2fKzKnDNRtfnuqsbY2Dui9zk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47BF5113E; Mon, 9 Dec 2024 21:55:53 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A766D3F58B; Mon, 9 Dec 2024 21:55:21 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 22/46] arm64/sysreg: Add register fields for PMICNTR_EL0 Date: Tue, 10 Dec 2024 11:22:47 +0530 Message-Id: <20241210055311.780688-23-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMICNTR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ff833f6f7f6d..8baf57c06dbd 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2591,6 +2591,10 @@ UnsignedEnum 2:0 F8S1 EndEnum EndSysreg =20 +Sysreg PMICNTR_EL0 3 3 9 4 0 +Field 63:0 ICNT +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0C56C228367 for ; Tue, 10 Dec 2024 05:55:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810131; cv=none; b=uxsRjtgxxLFW13fcSWH0K6DFt3NxyuEOuGrbjjBKb4lcfg0zSHrza3kyLZqJTTNQtpzb1hGkfiKbnhtLzPea1KQGIWuiHdnlF1J++x31prS14dIpzfuUlyETI8O8mx9OzwD4Jywy9aRLqB1JqtJriHX7uBLqkTxya4J++P2cSsw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810131; c=relaxed/simple; bh=xSBEoCorZlY1lWDEC5qLIfdNP/wF1P/IJSrPeR2Cz4w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=urfkui5AXsZeqpU7ugpF/mB74ljflJKPYVyikqaoEJR4AxPyQaH5Q2FbVBs7DpvXML753q26Nzad2z6PSMbMyJgGKIuvwFRLK86FSbP1JykvKRupEOaXG+riyIM+8O4D5uVDaWDoHfb5v3/4UI1XRZbzBactORNse0SCLrrmWyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F5A1113E; Mon, 9 Dec 2024 21:55:57 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C04C53F58B; Mon, 9 Dec 2024 21:55:25 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 23/46] arm64/sysreg: Add register fields for PMICFILTR_EL0 Date: Tue, 10 Dec 2024 11:22:48 +0530 Message-Id: <20241210055311.780688-24-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMICFILTR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8baf57c06dbd..7db912a81bbd 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2595,6 +2595,27 @@ Sysreg PMICNTR_EL0 3 3 9 4 0 Field 63:0 ICNT EndSysreg =20 +Sysreg PMICFILTR_EL0 3 3 9 6 0 +Res0 63:59 +Field 58 SYNC +Field 57:56 VS +Res0 55:32 +Field 31 P +Field 30 U +Field 29 NSK +Field 28 NSU +Field 27 NSH +Field 26 M +Res0 25 +Field 24 SH +Field 23 T +Field 22 RLK +Field 21 RLU +Field 20 RLH +Res0 19:16 +Field 15:0 evtCount +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BEBB222A1FA for ; Tue, 10 Dec 2024 05:55:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810136; cv=none; b=KMle3eC3/4uRrw7uetlCKaQYdVO0dLp33vkT99Ru8Ag79d/TkmEz1NbNwo5fVkngbul1NHGKhvyeFeRwCdAk5PuNWFXlO7qPoyzIgdZxj/J4qso+235xrMkdzblwpLt53xxHsIF9g/9vWDbFWNV3jIukA5ucdrQJyoIAZ0OpgZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810136; c=relaxed/simple; bh=fdPLXwOC4Qscsjzzd1bFWPe7IIhpnKaQqFHfQsEz0iU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g9FSyLtRdrbRRvyxUBZHU3+I7sGTVTuPoU+e8uE/MLH8j4DCL81t+QtakgdsNNx7tK7yf8FbtXUGzZwGOotMo9y1U/nAWNK7/XWAuuS79yXobEYj9mnHO0Au7Rw2KN0RzVJoXWbiqtSk/AB19iMF9rtC4zowO6HmpSA+T3LHhvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7788E113E; Mon, 9 Dec 2024 21:56:01 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D76293F58B; Mon, 9 Dec 2024 21:55:29 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 24/46] arm64/sysreg: Add register fields for SPMCR_EL0 Date: Tue, 10 Dec 2024 11:22:49 +0530 Message-Id: <20241210055311.780688-25-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7db912a81bbd..34323fe73188 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -165,6 +165,19 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg =20 +Sysreg SPMCR_EL0 2 3 9 12 0 +Res0 63:12 +Field 11 TR0 +Field 10 HDBG +Field 9 FZ0 +Field 8 NA +Res0 7:5 +Field 4 EX +Res0 3:2 +Field 1 P +Field 0 E +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C09D822619A for ; Tue, 10 Dec 2024 05:55:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810140; cv=none; b=iYCOI/aZSa9g9QsMsgq/cCKUgqos0pk7RFLaR8I6sqK/AosKnwJjTEdgB89iPWhDqBbs2XIm+fsDcVEAnRz86fQz42DQyo8n84ETugp+Ru85TKWRMI1pjlI7mipaOlQI8rPRA51pvsgbIx1MGMq/SsRRpO4IhjubL7rqtXHRoKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810140; c=relaxed/simple; bh=GuqtVTO39TXRTCS66vt7c7IRbx52cb427Sflt83BtkY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dnvjh/onAO7VSS0kDLQR6scyU/VBh7X/smDj8A2jvTNo4qAH6F7sFfMfngm4H76H0tUBFMUEkvNkRwGov019mHPlgFfbiCNypxFsxE5+dbfryvTbBRmvaMAKHnfFHHGId/GL12xk2i3RKbZV1JFaLn8iJuov2GpE+JXqudVdAug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7DC20113E; Mon, 9 Dec 2024 21:56:06 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6DE5E3F58B; Mon, 9 Dec 2024 21:55:34 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 25/46] arm64/sysreg: Add register fields for SPMOVSCLR_EL0 Date: Tue, 10 Dec 2024 11:22:50 +0530 Message-Id: <20241210055311.780688-26-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMOVSCLR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 34323fe73188..40de71614af7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -178,6 +178,73 @@ Field 1 P Field 0 E EndSysreg =20 +Sysreg SPMOVSCLR_EL0 2 3 9 12 3 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1CA4B22617E for ; Tue, 10 Dec 2024 05:55:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810144; cv=none; b=D5TSuBNYQ5L884XgMbdHOFscReQ366qF6jb3GaRrSAekLbih6N6bUGqklZxxdVypQe1/80FhyFq8O3Tp4R+TsLeJIJpQjZLCLMjZ/Y0vNxbngB4K9/aaT6QO+H0/GuB7XkOdutIZlfRkhfSeQ6Xo5dWermuBc63OjCB56ICB48k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810144; c=relaxed/simple; bh=1BkLXAJD4mjMJrhhq3+BTjYGvwtwnfgwGPCbumUojlA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GPut4ANFAlLSMvh6Cz3rzHu7GQW464VxREKIXgvNgq03tsKSDVYQwGEhhW1b9RvzW6+/jEH+7D8SkSxXnIemESN7O5cLqBEotW4wo7DOgOdcg89n2TwdEN0aa20oaeDQzfA+Vq8m71WE+y/HF+pX3lF6ILOz+e6I47K2a4jaA2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF828113E; Mon, 9 Dec 2024 21:56:10 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 02C403F58B; Mon, 9 Dec 2024 21:55:38 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 26/46] arm64/sysreg: Add register fields for SPMOVSSET_EL0 Date: Tue, 10 Dec 2024 11:22:51 +0530 Message-Id: <20241210055311.780688-27-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMOVSSET_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 40de71614af7..c983c1360908 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -245,6 +245,73 @@ Field 1 P1 Field 0 P0 EndSysreg =20 +Sysreg SPMOVSSET_EL0 2 3 9 14 3 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 14CD122617E for ; Tue, 10 Dec 2024 05:55:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810148; cv=none; b=LwlawrNhilX4pRGTBZyErPY194V3DIrQG3BFyl1z//jUhZuq65Lh8OUxfieKRvytxQ19v9PhoSFEosXQqcOoftqNRj07842nK1drvPGW3K8ISNaFyTOaf2em3adOpwTF5vdlKXil4cDoCyUAibuaKYjCmF4WSXE6sTESl2fvmeU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810148; c=relaxed/simple; bh=GOI4zv2r+qXuMJlH8A9CzZH6xSTCV3QmFXNFey2sKUU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YJ+ji1u6oi0zR6ltAUuk+dY1UpEUVV9Rd22RTv1siKwCWFL/DkJ5R/PvjSP8fIZpjcdPApT84bTJoT/rMajwxG+7UjR+ZDcMR3o9XoH56MO9QhRjvTjlrogg0Zaf7BtmrzZb4lQUGf+caA0zXGBUrlxEwhgyVwLO+Miya31JqAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4F9E113E; Mon, 9 Dec 2024 21:56:14 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3375C3F58B; Mon, 9 Dec 2024 21:55:42 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 27/46] arm64/sysreg: Add register fields for SPMINTENCLR_EL1 Date: Tue, 10 Dec 2024 11:22:52 +0530 Message-Id: <20241210055311.780688-28-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMINTENCLR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c983c1360908..0942cd16a942 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -161,6 +161,73 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg SPMINTENCLR_EL1 2 0 9 14 2 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A549E22839D for ; Tue, 10 Dec 2024 05:55:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810153; cv=none; b=PH/vPMCDVxnVIXiarWhgUWAiUjzyy39HQdOXWN6EVIblEHUXJ90iFiHLBWW+yO0K+ub3AolU8gtxH9/9x+uZyHjrgLdhWSzCK2nZXpCDWjWTyj8HtHqOAM1qA775ituCPePn2kvBOS6t2blbVs5IusHW0Rdhh/hjUn0rGlM6CVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810153; c=relaxed/simple; bh=CoR5S5ejcyPmjrXq73cA5G/Gz2+gQEDnlVn3qLfw7zo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QNyxzlJJPIb8H9DJ7OqBPjQs6Ox67RDBBXT+JAGfZuty5TI2LZ8kqrxzFQbSDZvIYsykCSs3FNyBr8eQNUMPaYGE4JNqBxggGYH47VGwpmdwZ0p44tJjmxlHhHAgwSCwwJtbqAwNEyd5d0ngJSOS8tiwkas7ROV/+sDOw8TPoME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5785E113E; Mon, 9 Dec 2024 21:56:19 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4A8693F58B; Mon, 9 Dec 2024 21:55:47 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 28/46] arm64/sysreg: Add register fields for SPMINTENSET_EL1 Date: Tue, 10 Dec 2024 11:22:53 +0530 Message-Id: <20241210055311.780688-29-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMINTENSET_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0942cd16a942..82fe720472cc 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -161,6 +161,73 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg SPMINTENSET_EL1 2 0 9 14 1 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMINTENCLR_EL1 2 0 9 14 2 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CB453228C83 for ; Tue, 10 Dec 2024 05:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810158; cv=none; b=EcID1jgD3Urz+Fvtllz/5LNwSo726he91W6Bpbwgynx6hyXNjGfQpLsOkqZT4xGX4Gph2lb13vti7uOK/D4G3EqBKdytuNnoIeShmrk3cODfPOZTEFcZxh8x7mg039PhiZSgBWGVgJxCkMNh2tlLhObgZMUfmMrhrz2ctpz2Q+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810158; c=relaxed/simple; bh=Jp8BQRF9YBKuaWKeYPiq4B4xBdhrI+r4KnyrIJ+CHkE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nmh7lGiPutf64Vx5asI8iiCcCv9rDMy+sVDmRyYRNSBpf7aufNttMJap5STfRK0A1i3cL06WwoR0bp7Y7ScsXDJsA7K8q5hJxMOvK0zu5I+INVnoEU1rjamJvyfsl6/O7ZAWiBv/9nKyCBiZa+W9uxBEGF99gcbf367EsJcHfrQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E3D2113E; Mon, 9 Dec 2024 21:56:23 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D028F3F77D; Mon, 9 Dec 2024 21:55:51 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 29/46] arm64/sysreg: Add register fields for SPMCNTENCLR_EL0 Date: Tue, 10 Dec 2024 11:22:54 +0530 Message-Id: <20241210055311.780688-30-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCNTENCLR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 82fe720472cc..9f278055fe77 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -312,6 +312,73 @@ Field 1 P Field 0 E EndSysreg =20 +Sysreg SPMCNTENCLR_EL0 2 3 9 12 2 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMOVSCLR_EL0 2 3 9 12 3 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EEBC722F389 for ; Tue, 10 Dec 2024 05:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810161; cv=none; b=eAoyp7RuXcKIQve7Bgyndy3VTK0KvGJoIpEwekCXx2gUGURdOZsukHAyZImzujK5n4w/yoLKygPB665oRJq9fVn4Dr6yPcE7IeOaeitsXjo3l8rA4kMcGyLbPnuToudtxVUn7roiKwOCyAQsjJa6ZzyfGubyrj47/ozrmRMz9Uw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810161; c=relaxed/simple; bh=Odl+DwkueB9FnhSVH+MnqvDr8an4fLSyXPf3dn7lGtg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RzD5sYbaIxKgb2bNTvnfeDIiaGzUiNDWWhjyqnnt8J3CsGvL1+Wwb2Pdu67kIvyNdSrGbrCzfTvJKKmkhZwl9jCXiDcBCj6OEflwTb2h59uLPyDBkSzB8M7omQgNiT4sZQiLJBBtfhRHXqoBsDXM2ceJLwmXCbzg8W+mBuAVnq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A945A113E; Mon, 9 Dec 2024 21:56:27 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 032483F58B; Mon, 9 Dec 2024 21:55:55 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 30/46] arm64/sysreg: Add register fields for SPMCNTENSET_EL0 Date: Tue, 10 Dec 2024 11:22:55 +0530 Message-Id: <20241210055311.780688-31-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCNTENSET_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9f278055fe77..a7b8f5602163 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -312,6 +312,73 @@ Field 1 P Field 0 E EndSysreg =20 +Sysreg SPMCNTENSET_EL0 2 3 9 12 1 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMCNTENCLR_EL0 2 3 9 12 2 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1373722836E for ; Tue, 10 Dec 2024 05:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810165; cv=none; b=N6fXhT19nxkQZNynAXFW3iDRZtEInIaBpOupubChmn4tMGRzGl5u+ggIRLkKV+4UaRAc3O1xAm7HUgZElA/l9M25RganI7tS4LAW5akTDq4gYWjtRnyvwKfkZov3FwsUnumdb1FLqP/B/qFVTlfPrtme+iaslBpBpXrYQ+lyj1w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810165; c=relaxed/simple; bh=Kb2mAhQuDznJ/xq2ScWlltmk8IeJqrp5a+QMu+fQdRg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=InXHXtF5K35jcfV/dO+gaUnZGbT6Pt6O5gxIRIFzM5zK956KHf2jtfH7+R5lvfbs9fC1tLb+tkacgmVReMaGE8xl84emn7oA57GrCf2UoS3E2ecpbmwnVo3ZE5ggnQICL82hw1tMcIJ0//i5LZ75QXGEisVPwEB4cf6Rt9VVvzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C3928113E; Mon, 9 Dec 2024 21:56:31 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2DEB13F58B; Mon, 9 Dec 2024 21:55:59 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 31/46] arm64/sysreg: Add register fields for SPMSELR_EL0 Date: Tue, 10 Dec 2024 11:22:56 +0530 Message-Id: <20241210055311.780688-32-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMSELR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a7b8f5602163..e57973b27e9c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -513,6 +513,18 @@ Field 1 P1 Field 0 P0 EndSysreg =20 +Sysreg SPMSELR_EL0 2 3 9 12 5 +Res0 63:10 +Field 9:4 SYSPMUSEL +Res0 3:2 +UnsignedEnum 1:0 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +EndSysreg + Sysreg SPMOVSSET_EL0 2 3 9 14 3 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 554C922ACCF for ; Tue, 10 Dec 2024 05:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810169; cv=none; b=SXA93LA9BBjlhlc+gjEpTXfjportZ7ZizYifUUWFpSeASwZrf31pDIpGeqYgAyPgnj70Niez15cwRI9yetSVQv7U2I3edCk2hANVJcrE8J2kDS5v2iekUF9X2Pq4Rwv9HoAFQQk+RBKgDFh0kbDbD0FVmgav5anroYploIDAtzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810169; c=relaxed/simple; bh=AE+/fFhYLaYBfAQhQdnX/SGlJNHtelvUloGMBoZEqZc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qXmE28d/J2k2H0tDdzRPGqp+wKMXNJEkwLNnwWtB6qFfmLpeO1jsXaP9oYOr18LyDliRqva9tOQCJTr1xMUwyPnBhtilHU7gpk1t3NfQCQRMQ3iqw9mEma+YCBZvU3UUT0AEvp+lHdCQ4/tshtk0WLfw8Pdf7i+xS6A9Ac4Ez6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1250F113E; Mon, 9 Dec 2024 21:56:36 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 46F2A3F58B; Mon, 9 Dec 2024 21:56:04 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 32/46] arm64/sysreg: Add register fields for PMICNTSVR_EL1 Date: Tue, 10 Dec 2024 11:22:57 +0530 Message-Id: <20241210055311.780688-33-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMICNTSVR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e57973b27e9c..b19b8e594524 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -299,6 +299,10 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg =20 +Sysreg PMICNTSVR_EL1 2 0 14 12 0 +Field 63:0 ICNT +EndSysreg + Sysreg SPMCR_EL0 2 3 9 12 0 Res0 63:12 Field 11 TR0 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 85ED9230992 for ; Tue, 10 Dec 2024 05:56:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810173; cv=none; b=b/PuBuydv7uXiidhq7iwCddxr3D1y6u7XXzn4a+i9iFQELywCP/R6p2kOXf5GsZZRnBINo5l1tQsD3RH7uPKu5SMDxQrv/wpb9flZQX4DwR+PO1twVPoLGL3FcCfh8AI6pLmYio0812Fscxcz9DcUPcq8JYDy0cA5FKqCJMiXlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810173; c=relaxed/simple; bh=0HplCQVjtuZ3jzxu1QmoTxKUxzJ4K9fX8Yz0im3TuXc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XcvvhHtNeBWxfw4qJpwIVVi+aZY2rMxX3HyVzbyn2FCY5H6TIINF4TDMjd8B/NYhYROqGJsWYTjyuiU70fDMp8rJ67vcc9QS2yMYiYaxFY7fZsPioWPWaWwcAPfp9ASUZWRMcC5HlrQAAOSHtgcE8nDM9YsBJcOuOdiQYjE+BBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3FF59113E; Mon, 9 Dec 2024 21:56:40 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8B2563F58B; Mon, 9 Dec 2024 21:56:08 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 33/46] arm64/sysreg: Add register fields for SPMIIDR_EL1 Date: Tue, 10 Dec 2024 11:22:58 +0530 Message-Id: <20241210055311.780688-34-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMIIDR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b19b8e594524..3b217ce3fe28 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -149,6 +149,14 @@ Field 3:2 P1 Field 1:0 P0 EndSysreg =20 +Sysreg SPMIIDR_EL1 2 0 9 13 4 +Res0 63:32 +Field 31:20 ProductID +Field 19:16 Variant +Field 15:12 Revision +Field 11:0 Implementer +EndSysreg + Sysreg SPMDEVAFF_EL1 2 0 9 13 6 Res0 63:40 Field 39:32 Aff3 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36CFF22ACDE for ; Tue, 10 Dec 2024 05:56:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810178; cv=none; b=IsWUMWKEhTSODIkVTmNlFy3ceWk/9FxGh05pla36rJGrgSpb6p469TtnAy2L15ImHrdEIUcJcgeJcNjp31KwplinFYd3p4a2dHYEIsm1zzObT86oYL9L2upKXRW7FZSHxNmVxaEOFOD8QWXiRuSjLrfBg67wBUUvvRVXGgWpTqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810178; c=relaxed/simple; bh=fGnXF4mftoJWeweuF/nNp7ZdSgW/TlFsq9GN/9YpIVM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NAo+J+j+mNfNfkP4Cn4sAV3WxMl1B+VLPZaW1e+rJbQOyLCwhSBlFRuaK6Qmpoj0mW+nR1Vo502c5WuLj1diQI/K7jRxmZ4AGSwQBgd6AGPWkZ/9DV18EDBxlNFuZfHXycWOhEmmgN8PovStrN/ukyAVfy3YviQ6rZSIjQjLqx0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DFAD9113E; Mon, 9 Dec 2024 21:56:44 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B88A93F58B; Mon, 9 Dec 2024 21:56:12 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 34/46] arm64/sysreg: Add register fields for SPMDEVARCH_EL1 Date: Tue, 10 Dec 2024 11:22:59 +0530 Message-Id: <20241210055311.780688-35-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMDEVARCH_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 3b217ce3fe28..d423bb218a9f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -157,6 +157,15 @@ Field 15:12 Revision Field 11:0 Implementer EndSysreg =20 +Sysreg SPMDEVARCH_EL1 2 0 9 13 5 +Res0 63:32 +Field 31:21 ARCHITECT +Field 20 PRESENT +Field 19:16 REVISION +Field 15:12 ARCHVER +Field 11:0 ARCHPART +EndSysreg + Sysreg SPMDEVAFF_EL1 2 0 9 13 6 Res0 63:40 Field 39:32 Aff3 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 52BE822ACE6 for ; Tue, 10 Dec 2024 05:56:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810183; cv=none; b=cRVr+JLsNQOTVzVcuillre6bf1QRAmJtcU+gSeVznTTu0ONjQWs3Ju/AWk9aO5Kqt3xnGwEfREIPHlbn084JId4peSwj3QIgjQWABrBWxGZXB2CmhHRzONpIBLyMugqgCQQtfnkDcCKuGdnJAzXKkrFEeR1tswEDxIwSbIZJPNQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810183; c=relaxed/simple; bh=938nBJtBrRKWZT5HkfYq9eUO6nVS84CROf9Iurs+qgs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LDyTspHBaitv2AEkHu84tXOa+7mG31T9gahPAo8LsXdfrgnymSHSG9YvgchxNJZVd0I6ypStaE1MgA1/MNQRnwfqoMnlHKPy7L7WdCVfccT1WlWhO+l6N03rg3CrmkJXy6P8hGrhr5CyT/NhcMvZsTyfX0hL5nTCSojduDFQT+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F784113E; Mon, 9 Dec 2024 21:56:50 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D5FAA3F58B; Mon, 9 Dec 2024 21:56:17 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 35/46] arm64/sysreg: Add register fields for SPMCFGR_EL1 Date: Tue, 10 Dec 2024 11:23:00 +0530 Message-Id: <20241210055311.780688-36-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCFGR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index d423bb218a9f..f4f5d22948ad 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -178,6 +178,24 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg SPMCFGR_EL1 2 0 9 13 7 +Res0 63:32 +Field 31:28 NCG +Res0 27:25 +Field 24 HDBG +Field 23 TR0 +Field 22 SS +Field 21 FZ0 +Field 20 MSI +Field 19 RAO +Res0 18 +Field 17 NA +Field 16 EX +Field 15:14 RAZ +Field 13:8 SIZE +Field 7:0 N +EndSysreg + Sysreg SPMINTENSET_EL1 2 0 9 14 1 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8A460228C9F for ; Tue, 10 Dec 2024 05:56:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810187; cv=none; b=TIGgNMaXgsD3kDAhm0H9Nw2b4WMMDZV/CMoYeM2oywRB7WhIEkJpoJ9X1uRFqQQex+017OIs8fifCRrF1bppirLDJBacmGtgiwB5m3FClNkF5CXq+S9jkMGzgpPen5RdUvb7shix2YC7AVIyc8PQx0Aamr/hvNX/3bBGZbEEGgo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810187; c=relaxed/simple; bh=ZAHAQ9t0ZGyTq43bWFjvLalyvzkcA5AXsZw3M2eXa/w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZXok1Mi6MporBXM0XlxJc/9TsviIhIpJ2DEjoYGRSApkSWRC8SuSF5YVlH8ItWRUFWiJdwPRMwZ4ZOrpyk25lvP76JOGZ4sAqU2lSI826KHKzZAQ0n4MGAYBjLZL7BCz2dFlEfkllwQCGPf1Q6HmjavlsVTprxjrxhMRanir4Ao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47317113E; Mon, 9 Dec 2024 21:56:54 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 887D73F58B; Mon, 9 Dec 2024 21:56:22 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 36/46] arm64/sysreg: Add register fields for PMSSCR_EL1 Date: Tue, 10 Dec 2024 11:23:01 +0530 Message-Id: <20241210055311.780688-37-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSSCR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f4f5d22948ad..c87017e69be1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2863,6 +2863,13 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMSSCR_EL1 3 0 9 13 3 +Res0 63:33 +Field 32 NC +Res0 31:1 +Field 0 SS +EndSysreg + Sysreg PMUACR_EL1 3 0 9 14 4 Res0 63:33 Field 32 FM --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A91F8228C9F for ; Tue, 10 Dec 2024 05:56:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810192; cv=none; b=USKBNAtahiFYgZ2UF4ZhkbBd5mJcNUwIBy5FxZTgvmwJ8G2si1FYRJkqcMZlaK3G0WToYAJUzxsgpSzaGl0MfDl+XevaH1SV6Sn0vHLycrufQ9uZxvQwbhbWiDxKCfIvCnTn2aMwr/HivOo3On7gvPkf9h0asMbOQ0mDM0miPC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810192; c=relaxed/simple; bh=JPkYsaUVI40eMiHv8osLbngvLv99SphoxOxVyh3Yb90=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nWYyK5vLGNKQZNTDFqb4DN9kfjzpFoM9pF/Xe+cxQfpxgwA8kcipmnUqvI0ZBJUcj/6QQ3g/s9wcMYfE/eEeXdvcK84EDTpoMcPcOuMREAD9YQT28YCq9WN26MxkjQYPNOCygF4LTZeMcs1XRq4OcPk8D+h/xax+cJrXIpYN0pQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 66914113E; Mon, 9 Dec 2024 21:56:58 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BF9253F58B; Mon, 9 Dec 2024 21:56:26 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 37/46] arm64/sysreg: Add register fields for PMZR_EL0 Date: Tue, 10 Dec 2024 11:23:02 +0530 Message-Id: <20241210055311.780688-38-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMZR_EL0 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c87017e69be1..05f548b11470 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3089,6 +3089,43 @@ Res0 19:16 Field 15:0 evtCount EndSysreg =20 +Sysreg PMZR_EL0 3 3 9 13 4 +Res0 63:33 +Field 32 FM +Field 31 C +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BE39E227B9F for ; Tue, 10 Dec 2024 05:56:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810198; cv=none; b=fhxXCWbx9KjtKOGrNGEln6pNSl23w2D5jdY0VIFPjE0EhQJxDUm9UHYFniJGpgK95PdFNUiSYtiLxYeGiz4hgiLt8D0/dEw8rGLLieQL6YGj9zNiWndtMddZYZhsuJv5oqqVoJmIhRIHeoCirKn8pweNhDQXzsOj7rHwCips8Ss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810198; c=relaxed/simple; bh=AKGqnRlsbpGjxwcSvfGpMEawxkUsWP6aZRz3F+X4Q/o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jW7aGphIncOxBLw1DZa8FOmod//SR8C5x+SDA0L66ZI8gmwFj3chRgBU2BM+OcziQm7qYayntkBSGpQyPhA8f+rsuTFizCEMffUG8K/gHN1CjUEiCU6NAJe6ozCLvaum9Ww4Sa7TJFSgq66XE9e0tw7f1ej5l7d6GuqKr4RVeIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B2A2113E; Mon, 9 Dec 2024 21:57:04 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E03233F58B; Mon, 9 Dec 2024 21:56:30 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 38/46] arm64/sysreg: Add register fields for SPMCGCR0_EL1 Date: Tue, 10 Dec 2024 11:23:03 +0530 Message-Id: <20241210055311.780688-39-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCGCR0_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 05f548b11470..e97572c4f370 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,21 @@ Res0 63:1 Field 0 OSLK EndSysreg =20 +SysregFields SPMCGCRx_EL1 +Field 63:56 N7 +Field 55:48 N6 +Field 47:40 N5 +Field 39:32 N4 +Field 31:24 N3 +Field 23:16 N2 +Field 15:8 N1 +Field 7:0 N0 +EndSysregFields + +Sysreg SPMCGCR0_EL1 2 0 9 13 0 +Fields SPMCGCRx_EL1 +EndSysreg + Sysreg SPMACCESSR_EL1 2 0 9 13 3 Field 63:62 P31 Field 61:60 P30 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1BF2522B58B for ; Tue, 10 Dec 2024 05:56:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810203; cv=none; b=FmuMM5yNuzrew4NZ3Q6mmkot+MSvu+hSfgr3KT9c9TfwL1qhn7iEJCHtl6sPAtoFAOgHANclzNPqY+bu/Y/hexDdLt2yFHbSBXrK/vAaUCFv0niSJ2hJlbZ8q9kEgGJpHeS5f2EBhCi3IeO8A5UWymQMye00lVSNmJOUV2vu4QU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810203; c=relaxed/simple; bh=mKSz9G7BgkeSslfEeHzwtZ3pc/2kPz8R8140Lhx69fk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eowjKjw+JYSDAQ3MDf5qy9D4WR1M6tnNnk1dz9zqpMlz79kkYlol3XEnyEH8558gYlyvVdQrtOQJONL97pxBR07Q6Zno0SM0VGH6bJAaJSLUqxsU9YpTG4mP18ROj/td+rVKzskzhfH8NVtDW43w980mnRq465kkRLnc2+cJ0gg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95766113E; Mon, 9 Dec 2024 21:57:08 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F32513F58B; Mon, 9 Dec 2024 21:56:36 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 39/46] arm64/sysreg: Add register fields for SPMCGCR1_EL1 Date: Tue, 10 Dec 2024 11:23:04 +0530 Message-Id: <20241210055311.780688-40-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCGCR1_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e97572c4f370..819163d1c673 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -129,6 +129,10 @@ Sysreg SPMCGCR0_EL1 2 0 9 13 0 Fields SPMCGCRx_EL1 EndSysreg =20 +Sysreg SPMCGCR1_EL1 2 0 9 13 1 +Fields SPMCGCRx_EL1 +EndSysreg + Sysreg SPMACCESSR_EL1 2 0 9 13 3 Field 63:62 P31 Field 61:60 P30 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1831A231C95 for ; Tue, 10 Dec 2024 05:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810206; cv=none; b=ZMnI1ARujko1C2Co/7CE6jswFpAJl+EMZZAVKb6uz6PStfYil3Mo+/XUQcnjXzvE0olcRoUbKBFajn4XKFzEv27mPZRvyes8UjzwNUnzkEYgIG4XPMty1CfDv+te9LqSzJ5P4rRg1p47Lluw6i6FOGzUBG7CTthfZw5MSdbHQ3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810206; c=relaxed/simple; bh=BixFpmFLItxpdF+oFHfPyHaVTrrds02OLKwPMyKXOLA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ivr81OFoqU/WEWSOYidBX+yEdyPWWTSG8kYiS2PVDafmqvcHp2WOEnpp602itK5Iva9x7baXOetNx+CSpAK5J486vRBtbq4Da+nMrMmTwf4fsccP2TmjgsdJXUtDXMAVZYz0fBY669naxbhxDLrxPpsEEEOHIzuaRtAkcjPswZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6DDA113E; Mon, 9 Dec 2024 21:57:12 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1B04F3F58B; Mon, 9 Dec 2024 21:56:40 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 40/46] arm64/sysreg: Add register fields for MDSTEPOP_EL1 Date: Tue, 10 Dec 2024 11:23:05 +0530 Message-Id: <20241210055311.780688-41-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSTEPOP_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 819163d1c673..68dee898743e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -104,6 +104,11 @@ EndEnum Res0 3:0 EndSysreg =20 +Sysreg MDSTEPOP_EL1 2 0 0 5 2 +Res0 63:32 +Field 31:0 OPCODE +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 271BE22B589 for ; Tue, 10 Dec 2024 05:56:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810210; cv=none; b=Ojcqqvm37TD3d1GzG/MwEArLqzxGJU7exO2+xh0RqTtbWQGRv12w6F/80Qth1ZhquIQMZNCy8HW3P4cGoXjgU9VTopKswx3PekCp8BULrJueR7XLgt9ugFQZHw0vn2Oa0d51dZ33NNzcBtlh3YY0PgHTIksCu/v4W4DuCFTTxMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810210; c=relaxed/simple; bh=wkYu2P+rzPLa46JVxDVrYtZNh+5yUIabgO7rUEIIDqY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AXf0BNPYJK7rkp8aHwPgoSLbLgSZcvFBmR4e/wrAY2yHF+Y36yXVtNT8rs8rENdZjTx4dN8q1VeFUsVIJk8IWn3WcpbIzea4GifP5hS0Za1BHFSe9p4Rh2LrsXXycDwtC89UBGtUQdiHW/AS4ZyUUPOCOIwnBz2Fz5xMoaj/EFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5321339; Mon, 9 Dec 2024 21:57:16 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4BD173F58B; Mon, 9 Dec 2024 21:56:45 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 41/46] arm64/sysreg: Add register fields for ERXGSR_EL1 Date: Tue, 10 Dec 2024 11:23:06 +0530 Message-Id: <20241210055311.780688-42-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for ERXGSR_EL1 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 68dee898743e..2e732ea1dfb1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3928,6 +3928,73 @@ Field 15:8 Attr1 Field 7:0 Attr0 EndSysregFields =20 +Sysreg ERXGSR_EL1 3 0 5 3 2 +Field 63 S63 +Field 62 S62 +Field 61 S61 +Field 60 S60 +Field 59 S59 +Field 58 S58 +Field 57 S57 +Field 56 S56 +Field 55 S55 +Field 54 S54 +Field 53 S53 +Field 52 S52 +Field 51 S51 +Field 50 S50 +Field 49 S49 +Field 48 S48 +Field 47 S47 +Field 46 S46 +Field 45 S45 +Field 44 S44 +Field 43 S43 +Field 42 S42 +Field 41 S41 +Field 40 S40 +Field 39 S39 +Field 38 S38 +Field 37 S37 +Field 36 S36 +Field 35 S35 +Field 34 S34 +Field 33 S33 +Field 32 S32 +Field 31 S31 +Field 30 S30 +Field 29 S29 +Field 28 S28 +Field 27 S27 +Field 26 S26 +Field 25 S25 +Field 24 S24 +Field 23 S23 +Field 22 S22 +Field 21 S21 +Field 20 S20 +Field 19 S19 +Field 18 S18 +Field 17 S17 +Field 16 S16 +Field 15 S15 +Field 14 S14 +Field 13 S13 +Field 12 S12 +Field 11 S11 +Field 10 S10 +Field 9 S9 +Field 8 S8 +Field 7 S7 +Field 6 S6 +Field 5 S5 +Field 4 S4 +Field 3 S3 +Field 2 S2 +Field 1 S1 +Field 0 S0 +EndSysreg + Sysreg MAIR2_EL1 3 0 10 2 1 Fields MAIR2_ELx EndSysreg --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3985922B5A3 for ; Tue, 10 Dec 2024 05:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810214; cv=none; b=A/VFzGRpTNrUCrPbuS7Drj072NfEgdsrqt0gj19Kof5yV6CRRtTChuZQsnhaHVMZ7i14RTWhMQW//cVCxKQulHO18W+fzM4D6NCyZgG1YFwNGgBHo7NUNgkRbiCa0NluKJrc8MIBGFBKGnqj/bf7j46i9NY2u4UXV83fKePGmpE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810214; c=relaxed/simple; bh=vXo6OoNwjF/iFoP7SMLckU7OqQVemdOtBB7G9hQEaXA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E3k+FUuteAIMYcp1jEG6qXXN+7wK+U0XdHDMv8RRjGrpsu315UbNVpoQFHUxyUE/shijUxQ7l8mGwruBWjvmOhkNzLsOzOSTOdmDxVJviMG2ybVijfBmT7qYS0t1+D5QJgA/Lx1R+aGJLIplETXF+USzPdoaac0rreuisCUE4iA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E83C4339; Mon, 9 Dec 2024 21:57:20 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 592E03F58B; Mon, 9 Dec 2024 21:56:49 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 42/46] arm64/sysreg: Add register fields for SPMACCESSR_EL2 Date: Tue, 10 Dec 2024 11:23:07 +0530 Message-Id: <20241210055311.780688-43-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMACCESSR_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 2e732ea1dfb1..8a6957cfa0e4 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -655,6 +655,41 @@ Field 1 P1 Field 0 P0 EndSysreg =20 +Sysreg SPMACCESSR_EL2 2 4 9 13 3 +Field 63:62 P31 +Field 61:60 P30 +Field 59:58 P29 +Field 57:56 P28 +Field 55:54 P27 +Field 53:52 P26 +Field 51:50 P25 +Field 49:48 P24 +Field 47:46 P23 +Field 45:44 P22 +Field 43:42 P21 +Field 41:40 P20 +Field 39:38 P19 +Field 37:36 P18 +Field 35:34 P17 +Field 33:32 P16 +Field 31:30 P15 +Field 29:28 P14 +Field 27:26 P13 +Field 25:24 P12 +Field 23:22 P11 +Field 21:20 P10 +Field 19:18 P9 +Field 17:16 P8 +Field 15:14 P7 +Field 13:12 P6 +Field 11:10 P5 +Field 9:8 P4 +Field 7:6 P3 +Field 5:4 P2 +Field 3:2 P1 +Field 1:0 P0 +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1EF90232788 for ; Tue, 10 Dec 2024 05:56:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810219; cv=none; b=Nz9HYY0Q1o/SVme8T98P9l2lMEVZlQ+awTObyJS/y/p2VPXwZC51mwjatorXjBGt5E2BjCH30O4XvBvVG+ZIALQhK65uxTJN7nrIV5xk7XdX8qvfJzU1bgLZuP0JTsnkaoPD32+LA0XKxbGlACDVQa5VRSJyV8ftI4i2gAe5glY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810219; c=relaxed/simple; bh=11Jq4A+6++f/hpvHdMx6u/W/Y6tK8u04dsLdOSvsX+8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PBpY3up0ph5CV+BgfOKSC/OUOmvqETSyP6I2vDojU4eIPB/WFDNnrCzN/XF7VtApXpoZv6HJGZMQOGTUEc3hrNqayIInmj3JBNhT5+rD6+KHMssNFWynjoel15DZ+guL1XFr34B/c3lQdUoVDc4ioAC8AOa43o0RV89O1S5sFMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FD1E113E; Mon, 9 Dec 2024 21:57:25 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E6123F58B; Mon, 9 Dec 2024 21:56:53 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 43/46] arm64/sysreg: Add remaining debug registers affected by HDFGxTR2_EL2 Date: Tue, 10 Dec 2024 11:23:08 +0530 Message-Id: <20241210055311.780688-44-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The HDFGxTR2_EL2 registers trap a set of debug and trace related registers. Almost all of those register encodings have been added in the tools sysreg format. Let's also add all the remaining encodings which are formula based (and only that, because we really don't care about what these registers actually do at this stage). Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/sysreg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index b8303a83c0bf..d1e3737a8ff8 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -270,6 +270,12 @@ #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) =20 +#define SYS_SPMEVCNTR_EL0(m) sys_reg(2, 3, 14, (0 | (m >> 3)), (m & 7)) +#define SYS_SPMEVTYPER_EL0(m) sys_reg(2, 3, 14, (2 | (m >> 3)), (m & 7)) +#define SYS_SPMEVFILTR_EL0(m) sys_reg(2, 3, 14, (4 | (m >> 3)), (m & 7)) +#define SYS_SPMEVFILT2R_EL0(m) sys_reg(2, 3, 14, (6 | (m >> 3)), (m & 7)) +#define SYS_PMEVCNTSVR_EL1(m) sys_reg(2, 0, 14, (8 | (m >> 3)), (m & 7)) + /* ETM */ #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) =20 --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9478722B5AB for ; Tue, 10 Dec 2024 05:57:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810224; cv=none; b=ORFZKlCdVF0bIlGsgXuJVuWQGr1gSKCFqJANzjcomZIfEJ8lFwZo/q9wNuI7iFoIGntXJg/l13J9QrOEM/HBZGDQ22FH8BajH8rEpRqRCSsnRR/UA8ZLxEnu7oJqMI954Oe8f8TpHbCN25tZ7a8BeeS3PF7qsf6yhF4Dt6Z5+1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810224; c=relaxed/simple; bh=XPh0+Rr+R964H/rZFfWv0puI6J1X0RHc0/MYTvCovHk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Xtcp5AKSHdV8fTwqpPunAnPTIp88SMFq8I8qVg2hrfUmWV8jFpglmaEWJ/uDxO7E82izAMeiAv7oFnaoZ82zFPsARcdh9nDo1mBe8A0PdIFaecZd2fzhMb8QGLQCAtmFn3hbxwBDgSUEZreLYAW98U6dAqiekmbXa9ouMJNE6WI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4477D339; Mon, 9 Dec 2024 21:57:30 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 23A9B3F58B; Mon, 9 Dec 2024 21:56:57 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 44/46] KVM: arm64: nv: Add FEAT_FGT2 registers access from virtual EL2 Date: Tue, 10 Dec 2024 11:23:09 +0530 Message-Id: <20241210055311.780688-45-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds VNCR-capable HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2 and HFGITR2_EL2 FEAT_FGT2 registers into enum vcpu_sysreg, and also enables their access from virtual EL2 environment. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/kvm_host.h | 5 +++++ arch/arm64/include/asm/vncr_mapping.h | 5 +++++ arch/arm64/kvm/sys_regs.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index e18e9244d17a..73ff8772ac22 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -548,6 +548,11 @@ enum vcpu_sysreg { VNCR(HDFGWTR_EL2), VNCR(HAFGRTR_EL2), =20 + VNCR(HDFGRTR2_EL2), + VNCR(HDFGWTR2_EL2), + VNCR(HFGITR2_EL2), + VNCR(HFGRTR2_EL2), + VNCR(HFGWTR2_EL2), VNCR(CNTVOFF_EL2), VNCR(CNTV_CVAL_EL0), VNCR(CNTV_CTL_EL0), diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index 4f9bbd4d6c26..d6110d7c36e2 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -38,6 +38,8 @@ #define VNCR_HFGRTR_EL2 0x1B8 #define VNCR_HFGWTR_EL2 0x1C0 #define VNCR_HFGITR_EL2 0x1C8 +#define VNCR_HDFGRTR2_EL2 0x1A0 +#define VNCR_HDFGWTR2_EL2 0x1B0 #define VNCR_HDFGRTR_EL2 0x1D0 #define VNCR_HDFGWTR_EL2 0x1D8 #define VNCR_ZCR_EL1 0x1E0 @@ -52,6 +54,9 @@ #define VNCR_PIRE0_EL1 0x290 #define VNCR_PIR_EL1 0x2A0 #define VNCR_POR_EL1 0x2A8 +#define VNCR_HFGRTR2_EL2 0x2C0 +#define VNCR_HFGWTR2_EL2 0x2C8 +#define VNCR_HFGITR2_EL2 0x310 #define VNCR_ICH_LR0_EL2 0x400 #define VNCR_ICH_LR1_EL2 0x408 #define VNCR_ICH_LR2_EL2 0x410 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 83c6b4a07ef5..c9e0e9322bd3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3004,9 +3004,14 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG_VNCR(VTCR_EL2, reset_val, 0), =20 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, + EL2_REG_VNCR(HDFGRTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HDFGWTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HFGRTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HFGWTR2_EL2, reset_val, 0), EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), + EL2_REG_VNCR(HFGITR2_EL2, reset_val, 0), EL2_REG_REDIR(SPSR_EL2, reset_val, 0), EL2_REG_REDIR(ELR_EL2, reset_val, 0), { SYS_DESC(SYS_SP_EL1), access_sp_el1}, --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA8012327B5 for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7FD3339; Mon, 9 Dec 2024 21:57:34 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D2AD93F58B; Mon, 9 Dec 2024 21:57:02 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 45/46] KVM: arm64: nv: Add FEAT_FGT2 registers based FGU handling Date: Tue, 10 Dec 2024 11:23:10 +0530 Message-Id: <20241210055311.780688-46-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This enables FEAT_FGT2 registers based FGU handling by adding the following new groups in 'enum fgt_group_id' for all respective FGT control registers and also adding FGU behaviour for their individual managed registers access traps. 1. HDFGRTR2_GROUP 2. HDFGWTR2_GROUP 3. HFGRTR2_GROUP 4. HFGWTR2_GROUP 5. HFGITR2_GROUP Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- Changes in V2: - Added HFGITR2_EL2 register based fields in encoding_to_fgt[] - Updated HFGITR2_EL2_[nDCCIVAPS|TSBCSYNC] in kvm_init_nv_sysregs() - Updated HFGITR2_EL2_[nDCCIVAPS|TSBCSYNC] in kvm_calculate_traps() arch/arm64/include/asm/kvm_arm.h | 20 +++ arch/arm64/include/asm/kvm_host.h | 5 + arch/arm64/include/asm/sysreg.h | 4 + arch/arm64/kvm/emulate-nested.c | 187 ++++++++++++++++++++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 26 ++++ arch/arm64/kvm/nested.c | 58 ++++++++ arch/arm64/kvm/sys_regs.c | 65 ++++++++ 7 files changed, 365 insertions(+) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 3e0f0de1d2da..5f725b7c9114 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -326,6 +326,26 @@ #define __HFGRTR_EL2_MASK GENMASK(49, 0) #define __HFGRTR_EL2_nMASK ~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK) =20 +#define __HDFGRTR2_EL2_RES0 HDFGRTR2_EL2_RES0 +#define __HDFGRTR2_EL2_MASK 0 +#define __HDFGRTR2_EL2_nMASK ~(__HDFGRTR2_EL2_RES0 | __HDFGRTR2_EL2_MASK) + +#define __HDFGWTR2_EL2_RES0 HDFGWTR2_EL2_RES0 +#define __HDFGWTR2_EL2_MASK 0 +#define __HDFGWTR2_EL2_nMASK ~(__HDFGWTR2_EL2_RES0 | __HDFGWTR2_EL2_MASK) + +#define __HFGITR2_EL2_RES0 HFGITR2_EL2_RES0 +#define __HFGITR2_EL2_MASK BIT(0) +#define __HFGITR2_EL2_nMASK ~(__HFGITR2_EL2_RES0 | __HFGITR2_EL2_MASK) + +#define __HFGRTR2_EL2_RES0 HFGRTR2_EL2_RES0 +#define __HFGRTR2_EL2_MASK 0 +#define __HFGRTR2_EL2_nMASK ~(HFGRTR2_EL2_RES0 | __HFGRTR2_EL2_MASK) + +#define __HFGWTR2_EL2_RES0 HFGWTR2_EL2_RES0 +#define __HFGWTR2_EL2_MASK 0 +#define __HFGWTR2_EL2_nMASK ~(HFGWTR2_EL2_RES0 | __HFGWTR2_EL2_MASK) + /* * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any * future additions, define __HFGWTR* macros relative to __HFGRTR* ones. diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 73ff8772ac22..c80c07be3358 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -271,6 +271,11 @@ enum fgt_group_id { HDFGWTR_GROUP =3D HDFGRTR_GROUP, HFGITR_GROUP, HAFGRTR_GROUP, + HDFGRTR2_GROUP, + HDFGWTR2_GROUP =3D HDFGRTR2_GROUP, + HFGRTR2_GROUP, + HFGWTR2_GROUP =3D HFGRTR2_GROUP, + HFGITR2_GROUP, =20 /* Must be last */ __NR_FGT_GROUP_IDS__ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index d1e3737a8ff8..2c10c56dea84 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -686,6 +686,10 @@ #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */ #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */ =20 +#define OP_TSB_CSYNC 0xD503225F +#define OP_DC_CIVAPS sys_insn(2, 0, 7, 15, 1) +#define OP_DC_CIGDVAPS sys_insn(2, 0, 7, 15, 5) + #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0) #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1) #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 1ffbfd1c3cf2..6c63cbfc11ea 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1933,6 +1933,163 @@ static const struct encoding_to_trap_config encodin= g_to_fgt[] __initconst =3D { SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), + + /* HDFGRTR2_EL2 */ + SR_FGT(SYS_MDSTEPOP_EL1, HDFGRTR2, nMDSTEPOP_EL1, 0), + SR_FGT(SYS_TRBMPAM_EL1, HDFGRTR2, nTRBMPAM_EL1, 0), + SR_FGT(SYS_TRCITECR_EL1, HDFGRTR2, nTRCITECR_EL1, 0), + SR_FGT(SYS_PMSDSFR_EL1, HDFGRTR2, nPMSDSFR_EL1, 0), + SR_FGT(SYS_SPMDEVAFF_EL1, HDFGRTR2, nSPMDEVAFF_EL1, 0), + + SR_FGT(SYS_SPMCGCR0_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMCGCR1_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMIIDR_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMDEVARCH_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMCFGR_EL1, HDFGRTR2, nSPMID, 0), + + SR_FGT(SYS_SPMSCR_EL1, HDFGRTR2, nSPMSCR_EL1, 0), + SR_FGT(SYS_SPMACCESSR_EL1, HDFGRTR2, nSPMACCESSR_EL1, 0), + SR_FGT(SYS_SPMCR_EL0, HDFGRTR2, nSPMCR_EL0, 0), + SR_FGT(SYS_SPMOVSCLR_EL0, HDFGRTR2, nSPMOVS, 0), + SR_FGT(SYS_SPMOVSSET_EL0, HDFGRTR2, nSPMOVS, 0), + SR_FGT(SYS_SPMINTENCLR_EL1, HDFGRTR2, nSPMINTEN, 0), + SR_FGT(SYS_SPMINTENSET_EL1, HDFGRTR2, nSPMINTEN, 0), + SR_FGT(SYS_SPMCNTENCLR_EL0, HDFGRTR2, nSPMCNTEN, 0), + SR_FGT(SYS_SPMCNTENSET_EL0, HDFGRTR2, nSPMCNTEN, 0), + SR_FGT(SYS_SPMSELR_EL0, HDFGRTR2, nSPMSELR_EL0, 0), + + SR_FGT(SYS_SPMEVTYPER_EL0(0), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(1), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(2), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(3), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(4), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(5), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(6), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(7), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(8), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(9), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(10), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(11), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(12), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(13), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(14), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(15), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + + SR_FGT(SYS_SPMEVFILTR_EL0(0), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(1), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(2), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(3), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(4), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(5), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(6), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(7), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(8), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(9), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(10), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(11), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(12), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(13), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(14), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(15), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + + SR_FGT(SYS_SPMEVFILT2R_EL0(0), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(1), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(2), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(3), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(4), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(5), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(6), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(7), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(8), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(9), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(10), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(11), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(12), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(13), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(14), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(15), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + + SR_FGT(SYS_SPMEVCNTR_EL0(0), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(1), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(2), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(3), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(4), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(5), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(6), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(7), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(8), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(9), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(10), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(11), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(12), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(13), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(14), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(15), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + + SR_FGT(SYS_PMSSCR_EL1, HDFGRTR2, nPMSSCR_EL1, 0), + SR_FGT(SYS_PMCCNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMICNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(0), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(1), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(2), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(3), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(4), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(5), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(6), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(7), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(8), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(9), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(10), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(11), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(12), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(13), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(14), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(15), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(16), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(17), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(18), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(19), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(20), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(21), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(22), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(23), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(24), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(25), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(26), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(27), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(28), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(29), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(30), HDFGRTR2, nPMSSDATA, 0), + + SR_FGT(SYS_MDSELR_EL1, HDFGRTR2, nMDSELR_EL1, 0), + SR_FGT(SYS_PMUACR_EL1, HDFGRTR2, nPMUACR_EL1, 0), + SR_FGT(SYS_PMICFILTR_EL0, HDFGRTR2, nPMICFILTR_EL0, 0), + SR_FGT(SYS_PMICNTR_EL0, HDFGRTR2, nPMICNTR_EL0, 0), + SR_FGT(SYS_PMIAR_EL1, HDFGRTR2, nPMIAR_EL1, 0), + SR_FGT(SYS_PMECR_EL1, HDFGRTR2, nPMECR_EL1, 0), + + /* + * HDFGWTR2_EL2 + * + * Although HDFGRTR2_EL2 and HDFGWTR2_EL2 registers largely + * overlap in their bit assignment, there are a number of bits + * that are RES0 on one side, and an actual trap bit on the + * other. The policy chosen here is to describe all the + * read-side mappings, and only the write-side mappings that + * differ from the read side, and the trap handler will pick + * the correct shadow register based on the access type. + */ + SR_FGT(SYS_PMZR_EL0, HDFGWTR2, nPMZR_EL0, 0), + + /* HFGRTR2_EL2 */ + SR_FGT(SYS_RCWSMASK_EL1, HFGRTR2, nRCWSMASK_EL1, 0), + SR_FGT(SYS_ERXGSR_EL1, HFGRTR2, nERXGSR_EL1, 0), + SR_FGT(SYS_PFAR_EL1, HFGRTR2, nPFAR_EL1, 0), + + /* HFGITR2_EL2 */ + SR_FGT(OP_DC_CIVAPS, HFGITR2, nDCCIVAPS, 0), + SR_FGT(OP_DC_CIGDVAPS, HFGITR2, nDCCIVAPS, 0), + SR_FGT(OP_TSB_CSYNC, HFGITR2, TSBCSYNC, 1), }; =20 static union trap_config get_trap_config(u32 sysreg) @@ -2197,6 +2354,14 @@ static bool check_fgt_bit(struct kvm_vcpu *vcpu, boo= l is_read, sr =3D is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; break; =20 + case HDFGRTR2_GROUP: + sr =3D is_read ? HDFGRTR2_EL2 : HDFGWTR2_EL2; + break; + + case HFGRTR2_GROUP: + sr =3D is_read ? HFGRTR2_EL2 : HFGWTR2_EL2; + break; + case HAFGRTR_GROUP: sr =3D HAFGRTR_EL2; break; @@ -2205,6 +2370,10 @@ static bool check_fgt_bit(struct kvm_vcpu *vcpu, boo= l is_read, sr =3D HFGITR_EL2; break; =20 + case HFGITR2_GROUP: + sr =3D HFGITR2_EL2; + break; + default: WARN_ONCE(1, "Unhandled FGT group"); return false; @@ -2279,6 +2448,20 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) val =3D __vcpu_sys_reg(vcpu, HDFGWTR_EL2); break; =20 + case HDFGRTR2_GROUP: + if (is_read) + val =3D __vcpu_sys_reg(vcpu, HDFGRTR2_EL2); + else + val =3D __vcpu_sys_reg(vcpu, HDFGWTR2_EL2); + break; + + case HFGRTR2_GROUP: + if (is_read) + val =3D __vcpu_sys_reg(vcpu, HFGRTR2_EL2); + else + val =3D __vcpu_sys_reg(vcpu, HFGWTR2_EL2); + break; + case HAFGRTR_GROUP: val =3D __vcpu_sys_reg(vcpu, HAFGRTR_EL2); break; @@ -2298,6 +2481,10 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) } break; =20 + case HFGITR2_GROUP: + val =3D __vcpu_sys_reg(vcpu, HFGITR2_EL2); + break; + case __NR_FGT_GROUP_IDS__: /* Something is really wrong, bail out */ WARN_ONCE(1, "__NR_FGT_GROUP_IDS__"); diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 34f53707892d..e0da9f45acde 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -84,10 +84,21 @@ static inline void __activate_traps_fpsimd32(struct kvm= _vcpu *vcpu) case HFGITR_EL2: \ id =3D HFGITR_GROUP; \ break; \ + case HFGITR2_EL2: \ + id =3D HFGITR2_GROUP; \ + break; \ case HDFGRTR_EL2: \ case HDFGWTR_EL2: \ id =3D HDFGRTR_GROUP; \ break; \ + case HDFGRTR2_EL2: \ + case HDFGWTR2_EL2: \ + id =3D HDFGRTR2_GROUP; \ + break; \ + case HFGRTR2_EL2: \ + case HFGWTR2_EL2: \ + id =3D HFGRTR2_GROUP; \ + break; \ case HAFGRTR_EL2: \ id =3D HAFGRTR_GROUP; \ break; \ @@ -159,6 +170,11 @@ static inline void __activate_traps_hfgxtr(struct kvm_= vcpu *vcpu) CHECK_FGT_MASKS(HDFGWTR_EL2); CHECK_FGT_MASKS(HAFGRTR_EL2); CHECK_FGT_MASKS(HCRX_EL2); + CHECK_FGT_MASKS(HDFGRTR2_EL2); + CHECK_FGT_MASKS(HDFGWTR2_EL2); + CHECK_FGT_MASKS(HFGITR2_EL2); + CHECK_FGT_MASKS(HFGRTR2_EL2); + CHECK_FGT_MASKS(HFGWTR2_EL2); =20 if (!cpus_have_final_cap(ARM64_HAS_FGT)) return; @@ -170,6 +186,11 @@ static inline void __activate_traps_hfgxtr(struct kvm_= vcpu *vcpu) update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2); update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2); update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HFGITR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HFGRTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HFGWTR2_EL2); =20 if (cpu_has_amu()) update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2); @@ -199,6 +220,11 @@ static inline void __deactivate_traps_hfgxtr(struct kv= m_vcpu *vcpu) __deactivate_fgt(hctxt, vcpu, kvm, HFGITR_EL2); __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR_EL2); __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HFGITR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HFGRTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HFGWTR2_EL2); =20 if (cpu_has_amu()) __deactivate_fgt(hctxt, vcpu, kvm, HAFGRTR_EL2); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 9b36218b48de..c208354aa929 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1155,6 +1155,52 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |=3D HDFGRTR_EL2_nPMSNEVFR_EL1; set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1); =20 + /* HDFG[RW]TR2_EL2 */ + res0 =3D res1 =3D 0; + if (!kvm_has_feat_enum(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + res0 |=3D HDFGRTR2_EL2_nMDSTEPOP_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, ExtTrcBuff, IMP)) + res0 |=3D HDFGRTR2_EL2_nTRBMPAM_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, ITE, IMP)) + res0 |=3D HDFGRTR2_EL2_nTRCITECR_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, PMSVer, V1P4)) + res0 |=3D HDFGRTR2_EL2_nPMSDSFR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + res0 |=3D (HDFGRTR2_EL2_nSPMDEVAFF_EL1 | HDFGRTR2_EL2_nSPMID | + HDFGRTR2_EL2_nSPMSCR_EL1 | HDFGRTR2_EL2_nSPMACCESSR_EL1 | + HDFGRTR2_EL2_nSPMCR_EL0 | HDFGRTR2_EL2_nSPMOVS | + HDFGRTR2_EL2_nSPMINTEN | HDFGRTR2_EL2_nSPMCNTEN | + HDFGRTR2_EL2_nSPMSELR_EL0 | HDFGRTR2_EL2_nSPMEVTYPERn_EL0 | + HDFGRTR2_EL2_nSPMEVCNTRn_EL0); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + res0 |=3D (HDFGRTR2_EL2_nPMSSCR_EL1 | HDFGRTR2_EL2_nPMSSDATA); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + res0 |=3D HDFGRTR2_EL2_nMDSELR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) + res0 |=3D HDFGRTR2_EL2_nPMUACR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) + res0 |=3D (HDFGRTR2_EL2_nPMICFILTR_EL0 | HDFGRTR2_EL2_nPMICNTR_EL0); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, SEBEP, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMIAR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP) && + !kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMECR_EL1; + set_sysreg_masks(kvm, HDFGRTR2_EL2, res0 | HDFGRTR2_EL2_RES0, res1 | HDFG= RTR2_EL2_RES1); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) + res0 |=3D HDFGWTR2_EL2_nPMZR_EL0; + set_sysreg_masks(kvm, HDFGWTR2_EL2, res0 | HDFGWTR2_EL2_RES0, res1 | HDFG= WTR2_EL2_RES1); + + /* HFG[R|W]TR2_EL2 */ + res0 =3D res1 =3D 0; + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, THE, IMP)) + res0 |=3D HFGRTR2_EL2_nRCWSMASK_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, V2)) + res0 |=3D HFGRTR2_EL2_nERXGSR_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, PFAR, IMP)) + res0 |=3D HFGRTR2_EL2_nPFAR_EL1; + set_sysreg_masks(kvm, HFGRTR2_EL2, res0 | HFGRTR2_EL2_RES0, res1 | HFGRTR= 2_EL2_RES1); + set_sysreg_masks(kvm, HFGWTR2_EL2, res0 | HFGWTR2_EL2_RES0, res1 | HFGWTR= 2_EL2_RES1); + /* Reuse the bits from the read-side and add the write-specific stuff */ if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) res0 |=3D (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0); @@ -1198,6 +1244,18 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |=3D HFGITR_EL2_ATS1E1A; set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); =20 + /* HFGITR2_EL2 */ + res0 =3D HFGITR2_EL2_RES0; + res1 =3D HFGITR2_EL2_RES1; + if (!kvm_has_feat_enum(kvm, ID_AA64MMFR4_EL1, PoPS, IMP)) + res0 |=3D HFGITR2_EL2_nDCCIVAPS; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1)) + res0 |=3D HFGITR2_EL2_TSBCSYNC; + + set_sysreg_masks(kvm, HFGITR2_EL2, res0 | HFGITR2_EL2_RES0, res1 | HFGITR= 2_EL2_RES1); + set_sysreg_masks(kvm, HFGITR2_EL2, res0 | HFGITR2_EL2_RES0, res1 | HFGITR= 2_EL2_RES1); + /* HAFGRTR_EL2 - not a lot to see here */ res0 =3D HAFGRTR_EL2_RES0; res1 =3D HAFGRTR_EL2_RES1; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c9e0e9322bd3..b6d34023729c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4977,6 +4977,71 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) kvm->arch.fgu[HAFGRTR_GROUP] |=3D ~(HAFGRTR_EL2_RES0 | HAFGRTR_EL2_RES1); =20 + if (!kvm_has_feat_enum(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nMDSTEPOP_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, ExtTrcBuff, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nTRBMPAM_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, ITE, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nTRCITECR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, PMSVer, V1P4)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMSDSFR_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nSPMDEVAFF_EL1 | + HDFGRTR2_EL2_nSPMID | + HDFGRTR2_EL2_nSPMSCR_EL1 | + HDFGRTR2_EL2_nSPMACCESSR_EL1 | + HDFGRTR2_EL2_nSPMCR_EL0 | + HDFGRTR2_EL2_nSPMOVS | + HDFGRTR2_EL2_nSPMINTEN | + HDFGRTR2_EL2_nSPMCNTEN | + HDFGRTR2_EL2_nSPMSELR_EL0 | + HDFGRTR2_EL2_nSPMEVTYPERn_EL0 | + HDFGRTR2_EL2_nSPMEVCNTRn_EL0; + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) { + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMSSCR_EL1; + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMSSDATA; + } + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nMDSELR_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) { + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMUACR_EL1; + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGWTR2_EL2_nPMZR_EL0; + } + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) { + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMICFILTR_EL0; + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMICNTR_EL0; + } + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, SEBEP, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMIAR_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP) && + !kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMECR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, THE, IMP)) + kvm->arch.fgu[HFGRTR2_GROUP] |=3D HFGRTR2_EL2_nRCWSMASK_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, V2)) + kvm->arch.fgu[HFGRTR2_GROUP] |=3D HFGRTR2_EL2_nERXGSR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, PFAR, IMP)) + kvm->arch.fgu[HFGRTR2_GROUP] |=3D HFGRTR2_EL2_nPFAR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64MMFR4_EL1, PoPS, IMP)) + kvm->arch.fgu[HFGITR2_GROUP] |=3D HFGITR2_EL2_nDCCIVAPS; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1)) + kvm->arch.fgu[HFGITR2_GROUP] |=3D HFGITR2_EL2_TSBCSYNC; + set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); out: mutex_unlock(&kvm->arch.config_lock); --=20 2.25.1 From nobody Sun Feb 8 11:18:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5ADAA2327B9 for ; Tue, 10 Dec 2024 05:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810233; cv=none; b=QeDlO+J6b+nums1psZ7Xj9+GDiYL+I1sVZvPETi/DfdP4iv6wmE9OSyFvOY5pIsNRUqtF95cU+m0eQyUtjVJynsnVQcOSnUiF9oCefhigsB6onGgYWgmNJP7YvjP+Jg50s2K0ELyU1KlqDyuH4miBMitvrnT/5bFzh+UVMI58ks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733810233; c=relaxed/simple; bh=/9O1FK5jKdCuDUfy5HXrYwNIfEr6/M6d8NZtZ408gp4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h1yS+6AcWiC2dhg4+qI24Xo8eQfetM0QfKF0JpoEhocgt8Z8SoJLVc1zLtywHSXG3RPbSQGBob/1XNOsVIVSUcNLzSQjUgBmlQ/V3gOhwpH6d4fYnOSqZ6rqADk9/SF4ykSa5Onow+igGCTKNgM09QzmDmjHGs6AwmOj5gPcqDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E34DC339; Mon, 9 Dec 2024 21:57:38 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.48.173]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 44A433F58B; Mon, 9 Dec 2024 21:57:07 -0800 (PST) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH V2 46/46] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers Date: Tue, 10 Dec 2024 11:23:11 +0530 Message-Id: <20241210055311.780688-47-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241210055311.780688-1-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe remaining MDCR_EL2 register, and associate that with all FEAT_FGT2 exposed system registers it allows to trap. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- Changes in V2: - Dropped check_cntr_accessible_N and CGT_CNTR_ACCESSIBLE_N constructs - SYS_PMEVCNTSVR_EL1(N) access traps have been forwarded to CGT_MDCR_HPMN - Updated check_mdcr_hpmn() to handle SYS_PMEVCNTSVR_EL1(N) registers - Changed behaviour as BEHAVE_FORWARD_RW for CGT_MDCR_EnSPM arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/emulate-nested.c | 158 ++++++++++++++++++++++++++++++ 2 files changed, 160 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index c80c07be3358..4cdce62642d1 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -441,6 +441,7 @@ enum vcpu_sysreg { PMINTENSET_EL1, /* Interrupt Enable Set Register */ PMOVSSET_EL0, /* Overflow Flag Status Set Register */ PMUSERENR_EL0, /* User Enable Register */ + SPMSELR_EL0, /* System PMU Select Register */ =20 /* Pointer Authentication Registers in a strict increasing order. */ APIAKEYLO_EL1, @@ -501,6 +502,7 @@ enum vcpu_sysreg { CNTHP_CVAL_EL2, CNTHV_CTL_EL2, CNTHV_CVAL_EL2, + SPMACCESSR_EL2, /* System PMU Access Register */ =20 /* Anything from this can be RES0/RES1 sanitised */ MARKER(__SANITISED_REG_START__), diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 6c63cbfc11ea..c7d6d2034f27 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -79,6 +79,7 @@ enum cgt_group_id { CGT_MDCR_TDRA, CGT_MDCR_E2PB, CGT_MDCR_TPMS, + CGT_MDCR_EnSPM, CGT_MDCR_TTRF, CGT_MDCR_E2TB, CGT_MDCR_TDCC, @@ -125,6 +126,7 @@ enum cgt_group_id { CGT_CNTHCTL_EL1PCTEN =3D __COMPLEX_CONDITIONS__, CGT_CNTHCTL_EL1PTEN, =20 + CGT_SPMSEL_SPMACCESS, CGT_CPTR_TTA, CGT_MDCR_HPMN, =20 @@ -351,6 +353,12 @@ static const struct trap_bits coarse_trap_bits[] =3D { .mask =3D MDCR_EL2_TPMS, .behaviour =3D BEHAVE_FORWARD_RW, }, + [CGT_MDCR_EnSPM] =3D { + .index =3D MDCR_EL2, + .value =3D MDCR_EL2_EnSPM, + .mask =3D MDCR_EL2_EnSPM, + .behaviour =3D BEHAVE_FORWARD_RW, + }, [CGT_MDCR_TTRF] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TTRF, @@ -509,6 +517,7 @@ static enum trap_behaviour check_mdcr_hpmn(struct kvm_v= cpu *vcpu) switch (sysreg) { case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30): case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30): + case SYS_PMEVCNTSVR_EL1(0) ... SYS_PMEVCNTSVR_EL1(30): idx =3D (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg); break; case SYS_PMXEVTYPER_EL0: @@ -528,6 +537,22 @@ static enum trap_behaviour check_mdcr_hpmn(struct kvm_= vcpu *vcpu) return BEHAVE_HANDLE_LOCALLY; } =20 +static enum trap_behaviour check_spmsel_spmaccess(struct kvm_vcpu *vcpu) +{ + u64 spmaccessr_el2, spmselr_el2; + int syspmusel; + + if (__vcpu_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_EnSPM) { + spmselr_el2 =3D __vcpu_sys_reg(vcpu, SPMSELR_EL0); + spmaccessr_el2 =3D __vcpu_sys_reg(vcpu, SPMACCESSR_EL2); + syspmusel =3D FIELD_GET(SPMSELR_EL0_SYSPMUSEL_MASK, spmselr_el2); + + if (((spmaccessr_el2 >> (syspmusel * 2)) & 0x3) =3D=3D 0x0) + return BEHAVE_FORWARD_RW; + } + return BEHAVE_HANDLE_LOCALLY; +} + #define CCC(id, fn) \ [id - __COMPLEX_CONDITIONS__] =3D fn =20 @@ -536,6 +561,7 @@ static const complex_condition_check ccc[] =3D { CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), CCC(CGT_CPTR_TTA, check_cptr_tta), CCC(CGT_MDCR_HPMN, check_mdcr_hpmn), + CCC(CGT_SPMSEL_SPMACCESS, check_spmsel_spmaccess), }; =20 /* @@ -947,6 +973,7 @@ static const struct encoding_to_trap_config encoding_to= _cgt[] __initconst =3D { SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN), SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN), SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN), + SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR), SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM), @@ -1120,6 +1147,7 @@ static const struct encoding_to_trap_config encoding_= to_cgt[] __initconst =3D { SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), + SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), @@ -1127,6 +1155,136 @@ static const struct encoding_to_trap_config encodin= g_to_cgt[] __initconst =3D { SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB), + + SR_TRAP(SYS_MDSTEPOP_EL1, CGT_MDCR_TDE_TDA), + SR_TRAP(SYS_TRBMPAM_EL1, CGT_MDCR_E2TB), + SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS), + + SR_TRAP(SYS_SPMDEVAFF_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCGCR0_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCGCR1_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMIIDR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMDEVARCH_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCFGR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMSCR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMACCESSR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCR_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMOVSCLR_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMOVSSET_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMINTENCLR_EL1, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMINTENSET_EL1, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMCNTENCLR_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMCNTENSET_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMSELR_EL0, CGT_MDCR_EnSPM), + + SR_TRAP(SYS_SPMEVTYPER_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_SPMEVFILTR_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_SPMEVFILT2R_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_SPMEVCNTR_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_PMEVCNTSVR_EL1(0), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(1), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(2), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(3), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(4), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(5), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(6), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(7), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(8), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(9), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(10), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(11), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(12), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(13), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(14), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(15), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(16), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(17), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(18), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(19), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(20), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(21), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(22), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(23), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(24), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(25), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(26), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(27), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(28), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(29), CGT_MDCR_HPMN), + SR_TRAP(SYS_PMEVCNTSVR_EL1(30), CGT_MDCR_HPMN), + + SR_TRAP(SYS_MDSELR_EL1, CGT_MDCR_TDE_TDA), + SR_TRAP(SYS_PMUACR_EL1, CGT_MDCR_TPM), + SR_TRAP(SYS_PMICFILTR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_PMICNTR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_PMIAR_EL1, CGT_MDCR_TPM), + SR_TRAP(SYS_PMECR_EL1, CGT_MDCR_TPM), + SR_TRAP(SYS_PMZR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC), SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM), SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM), --=20 2.25.1