From nobody Sun Dec 14 21:54:07 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D59581D5CD4 for ; Tue, 10 Dec 2024 03:28:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733801311; cv=none; b=bJFn9KfecBXC8aZrmXMxLpr9BKS/reOHzYouKiPZ/r0R4BjCiQ40TurmZDSJz35hRy/uxCpjC1p4WafXNknIK+ekGfzGs5B1dG4JvvGmtLYqtPM7PjctFI20Cz49APSKZ1qE6I4gTmRkgCOkLo9pOtB6aQRUrQA5tF/LmUnX618= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733801311; c=relaxed/simple; bh=+La+t7A+6zWJkVUphxCKu3qpxJLDhiQyjwcJjJDRU1Y=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=AknvppTI6oN6zDHlxGdWTwp9wyUFa+ukDdPetULWdWFZsO5YiiPDLh4VVvrl4cAGoRjSP660Nh2XCAj1B1gGsG863W2MUcPvwh/z93TpH24zBQcSQnO/l0TZbE4hICcig4zo5fqDlYYAUzMwXUUrLQx14RILLvtlTD5ARhHs7DU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=XKWJTHIX; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XKWJTHIX" X-UUID: cef9bf88b6a611efbd192953cf12861f-20241210 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=wZvcyFRVkuqRr5SEg06ypecfiNx410N5+o6HRphjK58=; b=XKWJTHIX+M8HC8xACHbOsHwORGt72PsxDrKzS2cKGeQEVaXA9F7BvP5vQyb69VXsu/APh+TDHU0IwyH1q+XsyCJJ0z1didheHC3nT8R+Tyi0gAng/51NP+9s1KvWl7NiXQMbVz5Pjzr28lMadVISHc07G2oFUrVsf546cvsTjhk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.45,REQID:6bed342c-d74d-4772-b882-556b05571f00,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6493067,CLOUDID:4208b53b-e809-4df3-83cd-88f012b9e9ba,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: cef9bf88b6a611efbd192953cf12861f-20241210 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1127726090; Tue, 10 Dec 2024 11:28:22 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 10 Dec 2024 11:28:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 10 Dec 2024 11:28:21 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , AngeloGioacchino Del Regno CC: , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , Subject: [PATCH v3] drm/mediatek: Move mtk_crtc_finish_page_flip() to ddp_cmdq_cb() Date: Tue, 10 Dec 2024 11:28:20 +0800 Message-ID: <20241210032820.10958-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mtk_crtc_finish_page_flip() is used to notify userspace that a page flip has been completed, allowing userspace to free the frame buffer of the last frame and commit the next frame. In MediaTek's hardware design for configuring display hardware by using GCE, `DRM_EVENT_FLIP_COMPLETE` should be notified to userspace after GCE has finished configuring all display hardware settings for each atomic_commit(). Currently, mtk_crtc_finish_page_flip() cannot guarantee that GCE has configured all the display hardware settings of the last frame. Therefore, to increase the accuracy of the timing for notifying `DRM_EVENT_FLIP_COMPLETE` to userspace, mtk_crtc_finish_page_flip() should be moved to ddp_cmdq_cb(). Fixes: 7f82d9c43879 ("drm/mediatek: Clear pending flag when cmdq packet is = done") Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_crtc.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index eb0e1233ad04..dabc2f8086b6 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -109,9 +109,14 @@ static void mtk_crtc_finish_page_flip(struct mtk_crtc = *mtk_crtc) static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc) { unsigned long flags; + struct drm_crtc *crtc =3D &mtk_crtc->base; + struct mtk_drm_private *priv =3D crtc->dev->dev_private; =20 drm_crtc_handle_vblank(&mtk_crtc->base); =20 + if (!priv->data->shadow_register) + return; + spin_lock_irqsave(&mtk_crtc->config_lock, flags); if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { mtk_crtc_finish_page_flip(mtk_crtc); @@ -284,10 +289,8 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *= mssg) state =3D to_mtk_crtc_state(mtk_crtc->base.state); =20 spin_lock_irqsave(&mtk_crtc->config_lock, flags); - if (mtk_crtc->config_updating) { - spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); + if (mtk_crtc->config_updating) goto ddp_cmdq_cb_out; - } =20 state->pending_config =3D false; =20 @@ -315,10 +318,15 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void = *mssg) mtk_crtc->pending_async_planes =3D false; } =20 - spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); - ddp_cmdq_cb_out: =20 + if (mtk_crtc->pending_needs_vblank) { + mtk_crtc_finish_page_flip(mtk_crtc); + mtk_crtc->pending_needs_vblank =3D false; + } + + spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); + mtk_crtc->cmdq_vblank_cnt =3D 0; wake_up(&mtk_crtc->cb_blocking_queue); } @@ -584,6 +592,10 @@ static void mtk_crtc_update_config(struct mtk_crtc *mt= k_crtc, bool needs_vblank) mtk_mutex_acquire(mtk_crtc->mutex); mtk_crtc_ddp_config(crtc, NULL); mtk_mutex_release(mtk_crtc->mutex); + + spin_lock_irqsave(&mtk_crtc->config_lock, flags); + mtk_crtc->config_updating =3D false; + spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); } #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (mtk_crtc->cmdq_client.chan) { @@ -606,13 +618,14 @@ static void mtk_crtc_update_config(struct mtk_crtc *m= tk_crtc, bool needs_vblank) */ mtk_crtc->cmdq_vblank_cnt =3D 3; =20 + spin_lock_irqsave(&mtk_crtc->config_lock, flags); + mtk_crtc->config_updating =3D false; + spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); + mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); } #endif - spin_lock_irqsave(&mtk_crtc->config_lock, flags); - mtk_crtc->config_updating =3D false; - spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); =20 mutex_unlock(&mtk_crtc->hw_lock); } --=20 2.43.0