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This involves checking msi-map and iommu-map device tree properties to ensure consistent mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related registers are configured. In the absence of an msi-map, the built-in MSI controller is utilized as a fallback. Register a PCI bus callback function to handle enable_device() and disable_device() operations, setting up the LUT whenever a new PCI device is enabled. Acked-by: Richard Zhu Signed-off-by: Frank Li --- Change from v7 to v8 - update comment message according to Lorenzo Pieralisi's suggestion. - rework err target table - improve err=3D=3D0 && target =3D=3DNULL description, use 1:1 map RID to stream ID. - invalidate case -> unexisted case, never happen - sid_i will not do mask, add comments said only MSI glue layer add controller id. - rework iommu map and msi map return value check logic according to Lorenzo Pieralisi's suggestion Change from v5 to v7 - change comment rid to RID - some mini change according to mani's feedback Change from v4 to v5 - rework commt message - add comment for mutex - s/reqid/rid/ - keep only one loop when enable lut - add warning when try to add duplicate rid - Replace hardcode 0xffff with IMX95_PE0_LUT_MASK - Fix some error message Change from v3 to v4 - Check target value at of_map_id(). - of_node_put() for target. - add case for msi-map exist, but rid entry is not exist. Change from v2 to v3 - Use the "target" argument of of_map_id() - Check if rid already in lut table when enable device change from v1 to v2 - set callback to pci_host_bridge instead pci->ops. --- drivers/pci/controller/dwc/pci-imx6.c | 186 ++++++++++++++++++++++++++++++= +++- 1 file changed, 185 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index c8d5c90aa4d45..d325f4fb279c8 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) =20 +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) =20 enum imx_pcie_variants { @@ -87,6 +103,7 @@ enum imx_pcie_variants { * workaround suspend resume on some devices which are affected by this er= rata. */ #define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9) +#define IMX_PCIE_FLAG_HAS_LUT BIT(10) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -139,6 +156,9 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + + /* Ensure that only one device's LUT is configured at any given time */ + struct mutex lock; }; =20 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -930,6 +950,162 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } =20 +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 rid, u8 sid) +{ + struct dw_pcie *pci =3D imx_pcie->pci; + struct device *dev =3D pci->dev; + u32 data1, data2; + int free =3D -1; + int i; + + if (sid >=3D 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + /* + * Iterate through all LUT entries to check for duplicate RID and + * identify the first available entry. Configure this available entry + * immediately after verification to avoid rescanning it. + */ + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + + if (!(data1 & IMX95_PE0_LUT_VLD)) { + if (free < 0) + free =3D i; + continue; + } + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + + /* Do not add duplicate RID */ + if (rid =3D=3D FIELD_GET(IMX95_PE0_LUT_REQID, data2)) { + dev_warn(dev, "Existing LUT entry available for RID (%d)", rid); + return 0; + } + } + + if (free < 0) { + dev_err(dev, "LUT entry is not available\n"); + return -ENOSPC; + } + + data1 =3D FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |=3D FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |=3D IMX95_PE0_LUT_VLD; + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 =3D IMX95_PE0_LUT_MASK; /* Match all bits of RID */ + data2 |=3D FIELD_PREP(IMX95_PE0_LUT_REQID, rid); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); + + return 0; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) +{ + u32 data2; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) =3D=3D rid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + break; + } + } +} + +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct p= ci_dev *pdev) +{ + struct imx_pcie *imx_pcie =3D to_imx_pcie(to_dw_pcie_from_pp(bridge->sysd= ata)); + u32 sid_i, sid_m, rid =3D pci_dev_id(pdev); + struct device_node *target; + struct device *dev; + int err_i, err_m; + u32 sid; + + dev =3D imx_pcie->pci->dev; + + target =3D NULL; + err_i =3D of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &ta= rget, &sid_i); + if (target) { + of_node_put(target); + } else { + /* + * "target =3D=3D NULL && err_i =3D=3D 0" means use 1:1 map RID to + * stream ID. Hardware can't support this because stream ID + * only 5bits + */ + err_i =3D -EINVAL; + } + + target =3D NULL; + err_m =3D of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target= , &sid_m); + + /* + * err_m target + * 0 NULL Use 1:1 map RID to stream ID, + * Current hardware can't support it, + * So return -EINVAL. + * !=3D 0 NULL msi-map not exist, use built-in MSI. + * 0 !=3D NULL Get correct streamID from RID. + * !=3D 0 !=3D NULL Unexisted case, never happen. + */ + if (!err_m && !target) + return -EINVAL; + else if (target) + of_node_put(target); /* Find stream ID map entry for RID in msi-map */ + + /* + * msi-map iommu-map + * N N DWC MSI Ctrl + * Y Y ITS + SMMU, require the same sid + * Y N ITS + * N Y DWC MSI Ctrl + SMMU + */ + if (err_i && err_m) + return 0; + + if (!err_i && !err_m) { + /* + * MSI glue layer auto add 2 bits controller ID ahead of stream + * ID, so mask this 2bits to get stream ID. + * But IOMMU glue layer doesn't do that. + */ + if (sid_i !=3D (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); + return -EINVAL; + } + } + + sid =3D sid_i; + if (!err_m) + sid =3D sid_m & IMX95_SID_MASK; + + return imx_pcie_add_lut(imx_pcie, rid, sid); +} + +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct= pci_dev *pdev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie =3D to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -946,6 +1122,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } =20 + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->enable_device =3D imx_pcie_enable_device; + pp->bridge->disable_device =3D imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); =20 if (imx_pcie->drvdata->init_phy) @@ -1330,6 +1511,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) imx_pcie->pci =3D pci; imx_pcie->drvdata =3D of_device_get_match_data(dev); =20 + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np =3D of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1627,7 +1810,8 @@ static const struct imx_pcie_drvdata drvdata[] =3D { }, [IMX95] =3D { .variant =3D IMX95, - .flags =3D IMX_PCIE_FLAG_HAS_SERDES, + .flags =3D IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names =3D imx8mq_clks, .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, --=20 2.34.1