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Signed-off-by: Xiangxu Yin --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 107 +++++++++++++++++++++++++++++++= +++- 1 file changed, 105 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 0a629c44e960e38891f48a8a021b86a6c1dadea1..dbd6eae267d7470d9b9a6c303ea= c03b64c3df3fc 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -2889,6 +2890,7 @@ ports { port@0 { reg =3D <0>; dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; }; }; =20 @@ -3002,6 +3004,107 @@ mdss_dsi0_phy: phy@ae94400 { =20 status =3D "disabled"; }; + + mdss_dp0: displayport-controller@ae90000 { + compatible =3D "qcom,sm6150-dp"; + + reg =3D <0x0 0xae90000 0x0 0x200>, + <0x0 0xae90200 0x0 0x200>, + <0x0 0xae90400 0x0 0x600>, + <0x0 0xae90a00 0x0 0x600>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dp_phy QMP_USB43DP_DP_LINK_CLK>, + <&mdss_dp_phy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys =3D <&mdss_dp_phy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dp0_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dp_phy: phy@88e9000 { + compatible =3D "qcom,qcs615-qmp-dp-phy"; + + reg =3D <0x0 0x88e9000 0x0 0x200>, + <0x0 0x88e9400 0x0 0x10c>, + <0x0 0x88e9800 0x0 0x10c>, + <0x0 0x88e9c00 0x0 0x200>; + + clocks =3D <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names =3D "cfg_ahb", + "ref"; + clock-output-names =3D "dp_phy_link_clk", + "dp_phy_vco_div_clk"; + + resets =3D <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names =3D "phy"; + + qcom,tcsr-reg =3D <&tcsr 0xb24c>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + status =3D "disabled"; + }; }; =20 dispcc: clock-controller@af00000 { @@ -3013,8 +3116,8 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, <0>, - <0>, - <0>; + <&mdss_dp_phy QMP_USB43DP_DP_LINK_CLK>, + <&mdss_dp_phy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 #clock-cells =3D <1>; #reset-cells =3D <1>; --=20 2.34.1